2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 * Based on davinci_dvevm.h. Original Copyrights follow:
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 * SPDX-License-Identifier: GPL-2.0+
17 #define CONFIG_DRIVER_TI_EMAC
18 /* check if direct NOR boot config is used */
19 #ifndef CONFIG_DIRECT_NOR_BOOT
20 #define CONFIG_USE_SPIFLASH
27 #define CONFIG_MACH_DAVINCI_DA850_EVM
28 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
29 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
30 #define CONFIG_SYS_OSCIN_FREQ 24000000
31 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
32 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
33 #define CONFIG_SYS_DA850_PLL_INIT
34 #define CONFIG_SYS_DA850_DDR_INIT
36 #ifdef CONFIG_DIRECT_NOR_BOOT
37 #define CONFIG_ARCH_CPU_INIT
38 #define CONFIG_DA8XX_GPIO
39 #define CONFIG_SYS_TEXT_BASE 0x60000000
40 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
41 #define CONFIG_DA850_LOWLEVEL
43 #define CONFIG_SYS_TEXT_BASE 0xc1080000
49 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
50 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
51 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
52 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
54 /* memtest start addr */
55 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
57 /* memtest will be run on 16MB */
58 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
60 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
62 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
63 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
64 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
65 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
66 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
67 DAVINCI_SYSCFG_SUSPSRC_I2C)
72 #define CONFIG_SYS_DV_CLKMODE 0
73 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1
74 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
75 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
76 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
77 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
78 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
79 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
80 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
82 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1
83 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
84 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
85 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
87 #define CONFIG_SYS_DA850_PLL0_PLLM 24
88 #define CONFIG_SYS_DA850_PLL1_PLLM 21
91 * DDR2 memory configuration
93 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
94 DV_DDR_PHY_EXT_STRBEN | \
95 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
97 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
98 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
99 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
100 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
101 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
102 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
103 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
104 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
106 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
107 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
109 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
110 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
111 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
112 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
113 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
114 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
115 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
116 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
117 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
119 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
120 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
121 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
122 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
123 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
124 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
125 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
126 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
128 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
129 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
134 #define CONFIG_SYS_NS16550
135 #define CONFIG_SYS_NS16550_SERIAL
136 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
137 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
138 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
139 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
140 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
143 #define CONFIG_SPI_FLASH_STMICRO
144 #define CONFIG_SPI_FLASH_WINBOND
145 #define CONFIG_CMD_SF
146 #define CONFIG_DAVINCI_SPI
147 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
148 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
149 #define CONFIG_SF_DEFAULT_SPEED 30000000
150 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
152 #ifdef CONFIG_USE_SPIFLASH
153 #define CONFIG_SPL_SPI_SUPPORT
154 #define CONFIG_SPL_SPI_FLASH_SUPPORT
155 #define CONFIG_SPL_SPI_LOAD
156 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
157 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
163 #define CONFIG_SYS_I2C
164 #define CONFIG_SYS_I2C_DAVINCI
165 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
166 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
167 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
170 * Flash & Environment
172 #ifdef CONFIG_USE_NAND
173 #undef CONFIG_ENV_IS_IN_FLASH
174 #define CONFIG_NAND_DAVINCI
175 #define CONFIG_SYS_NO_FLASH
176 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
177 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
178 #define CONFIG_ENV_SIZE (128 << 10)
179 #define CONFIG_SYS_NAND_USE_FLASH_BBT
180 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
181 #define CONFIG_SYS_NAND_PAGE_2K
182 #define CONFIG_SYS_NAND_CS 3
183 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
184 #define CONFIG_SYS_NAND_MASK_CLE 0x10
185 #define CONFIG_SYS_NAND_MASK_ALE 0x8
186 #undef CONFIG_SYS_NAND_HW_ECC
187 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
188 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
189 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
190 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
191 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
192 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
193 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
194 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
195 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
196 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
197 CONFIG_SYS_NAND_U_BOOT_SIZE - \
198 CONFIG_SYS_MALLOC_LEN - \
199 GENERATED_GBL_DATA_SIZE)
200 #define CONFIG_SYS_NAND_ECCPOS { \
201 24, 25, 26, 27, 28, \
202 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
203 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
204 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
206 #define CONFIG_SYS_NAND_PAGE_COUNT 64
207 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
208 #define CONFIG_SYS_NAND_ECCSIZE 512
209 #define CONFIG_SYS_NAND_ECCBYTES 10
210 #define CONFIG_SYS_NAND_OOBSIZE 64
211 #define CONFIG_SPL_NAND_SUPPORT
212 #define CONFIG_SPL_NAND_BASE
213 #define CONFIG_SPL_NAND_DRIVERS
214 #define CONFIG_SPL_NAND_ECC
215 #define CONFIG_SPL_NAND_SIMPLE
216 #define CONFIG_SPL_NAND_LOAD
220 * Network & Ethernet Configuration
222 #ifdef CONFIG_DRIVER_TI_EMAC
224 #define CONFIG_BOOTP_DNS
225 #define CONFIG_BOOTP_DNS2
226 #define CONFIG_BOOTP_SEND_HOSTNAME
227 #define CONFIG_NET_RETRY_COUNT 10
230 #ifdef CONFIG_USE_NOR
231 #define CONFIG_ENV_IS_IN_FLASH
232 #define CONFIG_FLASH_CFI_DRIVER
233 #define CONFIG_SYS_FLASH_CFI
234 #define CONFIG_SYS_FLASH_PROTECTION
235 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
236 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
237 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
238 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
239 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
240 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
241 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
243 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
246 #ifdef CONFIG_USE_SPIFLASH
247 #undef CONFIG_ENV_IS_IN_FLASH
248 #undef CONFIG_ENV_IS_IN_NAND
249 #define CONFIG_ENV_IS_IN_SPI_FLASH
250 #define CONFIG_ENV_SIZE (64 << 10)
251 #define CONFIG_ENV_OFFSET (512 << 10)
252 #define CONFIG_ENV_SECT_SIZE (64 << 10)
253 #define CONFIG_SYS_NO_FLASH
257 * U-Boot general configuration
259 #define CONFIG_SYS_GENERIC_BOARD
260 #define CONFIG_MISC_INIT_R
261 #define CONFIG_BOARD_EARLY_INIT_F
262 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
263 #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
264 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
265 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
266 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
267 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
268 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
269 #define CONFIG_VERSION_VARIABLE
270 #define CONFIG_AUTO_COMPLETE
271 #define CONFIG_SYS_HUSH_PARSER
272 #define CONFIG_CMDLINE_EDITING
273 #define CONFIG_SYS_LONGHELP
274 #define CONFIG_CRC32_VERIFY
275 #define CONFIG_MX_CYCLIC
276 #define CONFIG_OF_LIBFDT
281 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
282 #define CONFIG_HWCONFIG /* enable hwconfig */
283 #define CONFIG_CMDLINE_TAG
284 #define CONFIG_REVISION_TAG
285 #define CONFIG_SETUP_MEMORY_TAGS
286 #define CONFIG_BOOTARGS \
287 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
288 #define CONFIG_BOOTDELAY 3
289 #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
294 #define CONFIG_CMD_ENV
295 #define CONFIG_CMD_ASKENV
296 #define CONFIG_CMD_DHCP
297 #define CONFIG_CMD_DIAG
298 #define CONFIG_CMD_MII
299 #define CONFIG_CMD_PING
300 #define CONFIG_CMD_SAVES
302 #ifdef CONFIG_CMD_BDI
303 #define CONFIG_CLOCKS
306 #ifndef CONFIG_DRIVER_TI_EMAC
307 #undef CONFIG_CMD_DHCP
308 #undef CONFIG_CMD_MII
309 #undef CONFIG_CMD_PING
312 #ifdef CONFIG_USE_NAND
313 #define CONFIG_CMD_NAND
315 #define CONFIG_CMD_MTDPARTS
316 #define CONFIG_MTD_DEVICE
317 #define CONFIG_MTD_PARTITIONS
319 #define CONFIG_RBTREE
320 #define CONFIG_CMD_UBI
321 #define CONFIG_CMD_UBIFS
324 #ifdef CONFIG_USE_SPIFLASH
325 #define CONFIG_CMD_SPI
328 #if !defined(CONFIG_USE_NAND) && \
329 !defined(CONFIG_USE_NOR) && \
330 !defined(CONFIG_USE_SPIFLASH)
331 #define CONFIG_ENV_IS_NOWHERE
332 #define CONFIG_SYS_NO_FLASH
333 #define CONFIG_ENV_SIZE (16 << 10)
334 #undef CONFIG_CMD_ENV
337 /* SD/MMC configuration */
338 #ifndef CONFIG_USE_NOR
340 #define CONFIG_DAVINCI_MMC_SD1
341 #define CONFIG_GENERIC_MMC
342 #define CONFIG_DAVINCI_MMC
346 * Enable MMC commands only when
347 * MMC support is present
350 #define CONFIG_DOS_PARTITION
351 #define CONFIG_CMD_EXT2
352 #define CONFIG_CMD_FAT
353 #define CONFIG_CMD_MMC
356 #ifndef CONFIG_DIRECT_NOR_BOOT
357 /* defines for SPL */
358 #define CONFIG_SPL_FRAMEWORK
359 #define CONFIG_SPL_BOARD_INIT
360 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
361 CONFIG_SYS_MALLOC_LEN)
362 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
363 #define CONFIG_SPL_SPI_SUPPORT
364 #define CONFIG_SPL_SPI_FLASH_SUPPORT
365 #define CONFIG_SPL_SPI_LOAD
366 #define CONFIG_SPL_SERIAL_SUPPORT
367 #define CONFIG_SPL_LIBCOMMON_SUPPORT
368 #define CONFIG_SPL_LIBGENERIC_SUPPORT
369 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
370 #define CONFIG_SPL_STACK 0x8001ff00
371 #define CONFIG_SPL_TEXT_BASE 0x80000000
372 #define CONFIG_SPL_MAX_FOOTPRINT 32768
373 #define CONFIG_SPL_PAD_TO 32768
376 /* Load U-Boot Image From MMC */
377 #ifdef CONFIG_SPL_MMC_LOAD
378 #define CONFIG_SPL_MMC_SUPPORT
379 #define CONFIG_SPL_LIBDISK_SUPPORT
380 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75
381 #undef CONFIG_SPL_SPI_SUPPORT
382 #undef CONFIG_SPL_SPI_LOAD
385 /* additions for new relocation code, must added to all boards */
386 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
388 #ifdef CONFIG_DIRECT_NOR_BOOT
389 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
391 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
392 GENERATED_GBL_DATA_SIZE)
393 #endif /* CONFIG_DIRECT_NOR_BOOT */
394 #endif /* __CONFIG_H */