2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 * Based on davinci_dvevm.h. Original Copyrights follow:
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 #define CONFIG_DRIVER_TI_EMAC
30 #define CONFIG_USE_SPIFLASH
35 #define CONFIG_MACH_DAVINCI_DA850_EVM
36 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
37 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
38 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
39 #define CONFIG_SYS_OSCIN_FREQ 24000000
40 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
41 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
42 #define CONFIG_SYS_HZ 1000
43 #define CONFIG_SKIP_LOWLEVEL_INIT
44 #define CONFIG_SYS_TEXT_BASE 0xc1080000
45 #define CONFIG_SYS_ICACHE_OFF
46 #define CONFIG_SYS_DCACHE_OFF
47 #define CONFIG_SYS_L2CACHE_OFF
52 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
53 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
54 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
55 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
57 /* memtest start addr */
58 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
60 /* memtest will be run on 16MB */
61 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
63 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
64 #define CONFIG_STACKSIZE (256*1024) /* regular stack */
69 #define CONFIG_SYS_NS16550
70 #define CONFIG_SYS_NS16550_SERIAL
71 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
72 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
73 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
74 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
75 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
76 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
79 #define CONFIG_SPI_FLASH
80 #define CONFIG_SPI_FLASH_STMICRO
81 #define CONFIG_DAVINCI_SPI
82 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
83 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
84 #define CONFIG_SF_DEFAULT_SPEED 30000000
85 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
90 #define CONFIG_HARD_I2C
91 #define CONFIG_DRIVER_DAVINCI_I2C
92 #define CONFIG_SYS_I2C_SPEED 25000
93 #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
94 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
99 #ifdef CONFIG_USE_NAND
100 #undef CONFIG_ENV_IS_IN_FLASH
101 #define CONFIG_NAND_DAVINCI
102 #define CONFIG_SYS_NO_FLASH
103 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
104 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
105 #define CONFIG_ENV_SIZE (128 << 10)
106 #define CONFIG_SYS_NAND_USE_FLASH_BBT
107 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
108 #define CONFIG_SYS_NAND_PAGE_2K
109 #define CONFIG_SYS_NAND_CS 3
110 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
111 #define CONFIG_SYS_CLE_MASK 0x10
112 #define CONFIG_SYS_ALE_MASK 0x8
113 #undef CONFIG_SYS_NAND_HW_ECC
114 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
115 #define NAND_MAX_CHIPS 1
119 * Network & Ethernet Configuration
121 #ifdef CONFIG_DRIVER_TI_EMAC
122 #define CONFIG_EMAC_MDIO_PHY_NUM 0
124 #define CONFIG_BOOTP_DEFAULT
125 #define CONFIG_BOOTP_DNS
126 #define CONFIG_BOOTP_DNS2
127 #define CONFIG_BOOTP_SEND_HOSTNAME
128 #define CONFIG_NET_RETRY_COUNT 10
129 #define CONFIG_NET_MULTI
132 #ifdef CONFIG_USE_SPIFLASH
133 #undef CONFIG_ENV_IS_IN_FLASH
134 #undef CONFIG_ENV_IS_IN_NAND
135 #define CONFIG_ENV_IS_IN_SPI_FLASH
136 #define CONFIG_ENV_SIZE (64 << 10)
137 #define CONFIG_ENV_OFFSET (256 << 10)
138 #define CONFIG_ENV_SECT_SIZE (64 << 10)
139 #define CONFIG_SYS_NO_FLASH
143 * U-Boot general configuration
145 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
146 #define CONFIG_SYS_PROMPT "DA850-evm > " /* Command Prompt */
147 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
148 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
149 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
151 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
152 #define CONFIG_VERSION_VARIABLE
153 #define CONFIG_AUTO_COMPLETE
154 #define CONFIG_SYS_HUSH_PARSER
155 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
156 #define CONFIG_CMDLINE_EDITING
157 #define CONFIG_SYS_LONGHELP
158 #define CONFIG_CRC32_VERIFY
159 #define CONFIG_MX_CYCLIC
164 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
165 #define CONFIG_CMDLINE_TAG
166 #define CONFIG_REVISION_TAG
167 #define CONFIG_SETUP_MEMORY_TAGS
168 #define CONFIG_BOOTARGS \
169 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
170 #define CONFIG_BOOTDELAY 3
175 #include <config_cmd_default.h>
176 #define CONFIG_CMD_ENV
177 #define CONFIG_CMD_ASKENV
178 #define CONFIG_CMD_DHCP
179 #define CONFIG_CMD_DIAG
180 #define CONFIG_CMD_MII
181 #define CONFIG_CMD_PING
182 #define CONFIG_CMD_SAVES
183 #define CONFIG_CMD_MEMORY
185 #ifndef CONFIG_DRIVER_TI_EMAC
186 #undef CONFIG_CMD_NET
187 #undef CONFIG_CMD_DHCP
188 #undef CONFIG_CMD_MII
189 #undef CONFIG_CMD_PING
192 #ifdef CONFIG_USE_NAND
193 #undef CONFIG_CMD_FLASH
194 #undef CONFIG_CMD_IMLS
195 #define CONFIG_CMD_NAND
197 #define CONFIG_CMD_MTDPARTS
198 #define CONFIG_MTD_DEVICE
199 #define CONFIG_MTD_PARTITIONS
201 #define CONFIG_RBTREE
202 #define CONFIG_CMD_UBI
203 #define CONFIG_CMD_UBIFS
206 #ifdef CONFIG_USE_SPIFLASH
207 #undef CONFIG_CMD_IMLS
208 #undef CONFIG_CMD_FLASH
209 #define CONFIG_CMD_SPI
210 #define CONFIG_CMD_SF
211 #define CONFIG_CMD_SAVEENV
214 #if !defined(CONFIG_USE_NAND) && \
215 !defined(CONFIG_USE_NOR) && \
216 !defined(CONFIG_USE_SPIFLASH)
217 #define CONFIG_ENV_IS_NOWHERE
218 #define CONFIG_SYS_NO_FLASH
219 #define CONFIG_ENV_SIZE (16 << 10)
220 #undef CONFIG_CMD_IMLS
221 #undef CONFIG_CMD_ENV
224 /* additions for new relocation code, must added to all boards */
225 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
226 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
227 GENERATED_GBL_DATA_SIZE)
228 #endif /* __CONFIG_H */