2 * Copyright (C) 2009 David Brownell
4 * SPDX-License-Identifier: GPL-2.0+
10 /* Spectrum Digital TMS320DM355 EVM board */
11 #define DAVINCI_DM355EVM
13 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
14 #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
15 #define CONFIG_SYS_CONSOLE_INFO_QUIET
17 /* SoC Configuration */
18 #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
19 #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
22 #define CONFIG_NR_DRAM_BANKS 1
23 #define PHYS_SDRAM_1 0x80000000
24 #define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
26 /* Serial Driver info: UART0 for console */
27 #define CONFIG_SYS_NS16550
28 #define CONFIG_SYS_NS16550_SERIAL
29 #define CONFIG_SYS_NS16550_REG_SIZE -4
30 #define CONFIG_SYS_NS16550_COM1 0x01c20000
31 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
32 #define CONFIG_CONS_INDEX 1
33 #define CONFIG_BAUDRATE 115200
35 /* Ethernet: external DM9000 */
36 #define CONFIG_DRIVER_DM9000 1
37 #define CONFIG_DM9000_BASE 0x04014000
38 #define DM9000_IO CONFIG_DM9000_BASE
39 #define DM9000_DATA (CONFIG_DM9000_BASE + 2)
42 #define CONFIG_SYS_I2C
43 #define CONFIG_SYS_I2C_DAVINCI
44 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
45 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
47 /* NAND: socketed, two chipselects, normally 2 GBytes */
48 #define CONFIG_NAND_DAVINCI
49 #define CONFIG_SYS_NAND_CS 2
50 #define CONFIG_SYS_NAND_USE_FLASH_BBT
51 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
52 #define CONFIG_SYS_NAND_PAGE_2K
54 #define CONFIG_SYS_NAND_LARGEPAGE
55 #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
56 /* socket has two chipselects, nCE0 gated by address BIT(14) */
57 #define CONFIG_SYS_MAX_NAND_DEVICE 1
58 #define CONFIG_SYS_NAND_MAX_CHIPS 2
62 #define CONFIG_GENERIC_MMC
63 #define CONFIG_DAVINCI_MMC
64 #define CONFIG_DAVINCI_MMC_SD1
65 #define CONFIG_MMC_MBLOCK
67 /* USB: OTG connector */
68 /* NYET -- #define CONFIG_USB_DAVINCI */
70 /* U-Boot command configuration */
71 #include <config_cmd_default.h>
74 #undef CONFIG_CMD_FLASH
75 #undef CONFIG_CMD_FPGA
76 #undef CONFIG_CMD_SETGETDCR
78 #define CONFIG_CMD_ASKENV
79 #define CONFIG_CMD_DHCP
80 #define CONFIG_CMD_I2C
81 #define CONFIG_CMD_PING
82 #define CONFIG_CMD_SAVES
89 #define CONFIG_DOS_PARTITION
90 #define CONFIG_CMD_EXT2
91 #define CONFIG_CMD_FAT
92 #define CONFIG_CMD_MMC
95 #ifdef CONFIG_NAND_DAVINCI
96 #define CONFIG_CMD_MTDPARTS
97 #define CONFIG_MTD_PARTITIONS
98 #define CONFIG_MTD_DEVICE
99 #define CONFIG_CMD_NAND
100 #define CONFIG_CMD_UBI
101 #define CONFIG_RBTREE
104 #ifdef CONFIG_USB_DAVINCI
105 #define CONFIG_MUSB_HCD
106 #define CONFIG_CMD_USB
107 #define CONFIG_USB_STORAGE
109 #undef CONFIG_MUSB_HCD
110 #undef CONFIG_CMD_USB
111 #undef CONFIG_USB_STORAGE
114 #define CONFIG_CRC32_VERIFY
115 #define CONFIG_MX_CYCLIC
117 /* U-Boot general configuration */
118 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
119 #define CONFIG_SYS_PROMPT "DM355 EVM # " /* Monitor Command Prompt */
120 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
121 #define CONFIG_SYS_PBSIZE /* Print buffer size */ \
122 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
123 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
124 #define CONFIG_SYS_HUSH_PARSER
125 #define CONFIG_SYS_LONGHELP
127 #ifdef CONFIG_NAND_DAVINCI
128 #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
129 #define CONFIG_ENV_IS_IN_NAND
130 #define CONFIG_ENV_OFFSET 0x3C0000
131 #undef CONFIG_ENV_IS_IN_FLASH
134 #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
135 #define CONFIG_CMD_ENV
136 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
137 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
138 #define CONFIG_ENV_IS_IN_MMC
139 #undef CONFIG_ENV_IS_IN_FLASH
142 #define CONFIG_BOOTDELAY 5
143 #define CONFIG_BOOTCOMMAND \
145 #define CONFIG_BOOTARGS \
146 "console=ttyS0,115200n8 " \
147 "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
149 #define CONFIG_CMDLINE_EDITING
150 #define CONFIG_VERSION_VARIABLE
151 #define CONFIG_TIMESTAMP
153 #define CONFIG_NET_RETRY_COUNT 10
155 /* U-Boot memory configuration */
156 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
157 #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
158 #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
160 /* Linux interfacing */
161 #define CONFIG_CMDLINE_TAG
162 #define CONFIG_SETUP_MEMORY_TAGS
163 #define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
164 #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
167 /* NAND configuration ... socketed with two chipselects. It normally comes
168 * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
169 * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
170 * pretty much demands the 4-bit ECC support.) You can of course swap in
171 * other parts, including small page ones.
173 * This presents a single read-only partition for all bootloader stuff.
174 * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
175 * some extra space to help cope with bad blocks in that data. Linux
176 * shouldn't care about its detailed layout, and will probably want to use
177 * UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to
178 * override this default partitioning using MTDPARTS and cmdlinepart.
180 #define MTDIDS_DEFAULT "nand0=davinci_nand.0"
182 #ifdef CONFIG_SYS_NAND_LARGEPAGE
183 /* Use same layout for 128K/256K blocks; allow some bad blocks */
184 #define PART_BOOT "2m(bootloader)ro,"
186 /* Assume 16K erase blocks; allow a few bad ones. */
187 #define PART_BOOT "512k(bootloader)ro,"
190 #define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
191 #define PART_REST "-(filesystem)"
193 #define MTDPARTS_DEFAULT \
194 "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
196 #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
198 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
199 #define CONFIG_SYS_INIT_SP_ADDR \
200 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
202 #endif /* __CONFIG_H */