2 * Copyright (C) 2009 Texas Instruments Incorporated
4 * SPDX-License-Identifier: GPL-2.0+
10 #define DAVINCI_DM355LEOPARD
12 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
13 #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
14 #define CONFIG_SYS_CONSOLE_INFO_QUIET
16 /* SoC Configuration */
17 #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
18 #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
21 #define CONFIG_NR_DRAM_BANKS 1
22 #define PHYS_SDRAM_1 0x80000000
23 #define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
25 /* Serial Driver info: UART0 for console */
26 #define CONFIG_SYS_NS16550
27 #define CONFIG_SYS_NS16550_SERIAL
28 #define CONFIG_SYS_NS16550_REG_SIZE -4
29 #define CONFIG_SYS_NS16550_COM1 0x01c20000
30 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
31 #define CONFIG_CONS_INDEX 1
32 #define CONFIG_BAUDRATE 115200
34 /* Ethernet: external DM9000 */
35 #define CONFIG_DRIVER_DM9000 1
36 #define CONFIG_DM9000_BASE 0x04000000
37 #define DM9000_IO CONFIG_DM9000_BASE
38 #define DM9000_DATA (CONFIG_DM9000_BASE + 16)
41 #define CONFIG_SYS_I2C
42 #define CONFIG_SYS_I2C_DAVINCI
43 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
44 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10
47 #define CONFIG_NAND_DAVINCI
48 #define CONFIG_SYS_NAND_CS 2
49 #define CONFIG_SYS_NAND_USE_FLASH_BBT
50 #define CONFIG_SYS_NAND_HW_ECC
52 #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
53 #define CONFIG_SYS_MAX_NAND_DEVICE 1
55 /* U-Boot command configuration */
56 #define CONFIG_CMD_ASKENV
57 #define CONFIG_CMD_DHCP
58 #define CONFIG_CMD_I2C
59 #define CONFIG_CMD_PING
60 #define CONFIG_CMD_SAVES
66 #ifdef CONFIG_NAND_DAVINCI
67 #define CONFIG_CMD_MTDPARTS
68 #define CONFIG_MTD_PARTITIONS
69 #define CONFIG_MTD_DEVICE
70 #define CONFIG_CMD_NAND
71 #define CONFIG_CMD_UBI
75 #define CONFIG_CRC32_VERIFY
76 #define CONFIG_MX_CYCLIC
78 /* U-Boot general configuration */
79 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
80 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
81 #define CONFIG_SYS_PBSIZE /* Print buffer size */ \
82 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
83 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
84 #define CONFIG_SYS_HUSH_PARSER
85 #define CONFIG_SYS_LONGHELP
87 #ifdef CONFIG_NAND_DAVINCI
88 #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
89 #define CONFIG_ENV_IS_IN_NAND
90 #define CONFIG_ENV_OFFSET 0x3C0000
91 #undef CONFIG_ENV_IS_IN_FLASH
92 #define CONFIG_ENV_OVERWRITE
95 #define CONFIG_BOOTDELAY 3
96 #define CONFIG_BOOTCOMMAND "dhcp;bootm"
97 #define CONFIG_BOOTARGS \
98 "console=ttyS0,115200n8 " \
99 "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
101 #define CONFIG_CMDLINE_EDITING
102 #define CONFIG_VERSION_VARIABLE
103 #define CONFIG_TIMESTAMP
105 #define CONFIG_NET_RETRY_COUNT 10
107 /* U-Boot memory configuration */
108 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
109 #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
110 #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
112 /* Linux interfacing */
113 #define CONFIG_CMDLINE_TAG
114 #define CONFIG_SETUP_MEMORY_TAGS
115 #define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
116 #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
118 #define MTDIDS_DEFAULT "nand0=davinci_nand.0"
120 #ifdef CONFIG_SYS_NAND_LARGEPAGE
121 #define PART_BOOT "2m(bootloader)ro,"
123 /* Assume 16K erase blocks; allow a few bad ones. */
124 #define PART_BOOT "512k(bootloader)ro,"
127 #define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
128 #define PART_REST "-(filesystem)"
130 #define MTDPARTS_DEFAULT \
131 "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
133 #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
135 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
136 #define CONFIG_SYS_INIT_SP_ADDR \
137 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
139 #endif /* __CONFIG_H */