3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_DBAU1X00 1
17 #define CONFIG_DISPLAY_BOARDINFO
19 #ifdef CONFIG_DBAU1000
20 /* Also known as Merlot */
22 #ifdef CONFIG_DBAU1100
24 #ifdef CONFIG_DBAU1500
26 #ifdef CONFIG_DBAU1550
29 #error "No valid board set"
35 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
37 #define CONFIG_BAUDRATE 115200
41 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
42 #undef CONFIG_BOOTARGS
44 #define CONFIG_EXTRA_ENV_SETTINGS \
45 "addmisc=setenv bootargs ${bootargs} " \
46 "console=ttyS0,${baudrate} " \
48 "bootfile=/tftpboot/vmlinux.srec\0" \
49 "load=tftp 80500000 ${u-boot}\0" \
52 #ifdef CONFIG_DBAU1550
53 /* Boot from flash by default, revert to bootp */
54 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
55 #else /* CONFIG_DBAU1550 */
56 #define CONFIG_BOOTCOMMAND "bootp;bootm"
57 #endif /* CONFIG_DBAU1550 */
63 #define CONFIG_BOOTP_BOOTFILESIZE
64 #define CONFIG_BOOTP_BOOTPATH
65 #define CONFIG_BOOTP_GATEWAY
66 #define CONFIG_BOOTP_HOSTNAME
70 * Command line configuration.
72 #undef CONFIG_CMD_BEDBUG
77 #ifdef CONFIG_DBAU1550
81 #undef CONFIG_CMD_PCMCIA
85 #define CONFIG_CMD_IDE
86 #define CONFIG_CMD_DHCP
92 * Miscellaneous configurable options
94 #define CONFIG_SYS_LONGHELP /* undef to save memory */
96 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
97 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
98 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
100 #define CONFIG_SYS_MALLOC_LEN 128*1024
102 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
104 #define CONFIG_SYS_MHZ 396
106 #if (CONFIG_SYS_MHZ % 12) != 0
107 #error "Invalid CPU frequency - must be multiple of 12!"
110 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
112 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
114 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
116 #define CONFIG_SYS_MEMTEST_START 0x80100000
117 #define CONFIG_SYS_MEMTEST_END 0x80800000
119 /*-----------------------------------------------------------------------
120 * FLASH and environment organization
122 #ifdef CONFIG_DBAU1550
124 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
125 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
127 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
128 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
130 #else /* CONFIG_DBAU1550 */
132 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
133 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
135 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
136 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
138 #endif /* CONFIG_DBAU1550 */
140 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
142 #define CONFIG_SYS_FLASH_CFI 1
143 #define CONFIG_FLASH_CFI_DRIVER 1
145 /* The following #defines are needed to get flash environment right */
146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
147 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
149 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
151 /* We boot from this flash, selected with dip switch */
152 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
154 /* timeout values are in ticks */
155 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
156 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
158 #define CONFIG_ENV_IS_NOWHERE 1
160 /* Address and size of Primary Environment Sector */
161 #define CONFIG_ENV_ADDR 0xB0030000
162 #define CONFIG_ENV_SIZE 0x10000
164 #define CONFIG_FLASH_16BIT
166 #define CONFIG_NR_DRAM_BANKS 2
169 #ifdef CONFIG_DBAU1550
175 #define CONFIG_MEMSIZE_IN_BYTES
177 #ifndef CONFIG_DBAU1550
178 /*---ATA PCMCIA ------------------------------------*/
179 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
180 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
181 #define CONFIG_PCMCIA_SLOT_A
183 #define CONFIG_ATAPI 1
184 #define CONFIG_MAC_PARTITION 1
186 /* We run CF in "true ide" mode or a harddrive via pcmcia */
187 #define CONFIG_IDE_PCMCIA 1
189 /* We only support one slot for now */
190 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
191 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
193 #undef CONFIG_IDE_LED /* LED for ide not supported */
194 #undef CONFIG_IDE_RESET /* reset for ide not supported */
196 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
198 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
200 /* Offset for data I/O */
201 #define CONFIG_SYS_ATA_DATA_OFFSET 8
203 /* Offset for normal register accesses */
204 #define CONFIG_SYS_ATA_REG_OFFSET 0
206 /* Offset for alternate registers */
207 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
208 #endif /* CONFIG_DBAU1550 */
210 /*-----------------------------------------------------------------------
211 * Cache Configuration
213 #define CONFIG_SYS_DCACHE_SIZE 16384
214 #define CONFIG_SYS_ICACHE_SIZE 16384
215 #define CONFIG_SYS_CACHELINE_SIZE 32
217 #endif /* __CONFIG_H */