2 * (C) Copyright 2007-2010
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef __KM82XX_COMMON
25 #define __KM82XX_COMMON
28 * Select serial console configuration
30 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
31 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
34 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
35 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
36 #undef CONFIG_CONS_NONE /* It's not on external UART */
37 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
38 #define CONFIG_SYS_SMC_RXBUFLEN 128
39 #define CONFIG_SYS_MAXIDLE 10
42 * Select ethernet configuration
44 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
45 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
48 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
49 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
52 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
53 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
54 #undef CONFIG_ETHER_NONE /* No external Ethernet */
55 #define CONFIG_NET_MULTI
57 #define CONFIG_ETHER_INDEX 4
58 #define CONFIG_HAS_ETH0
59 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000
61 #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
63 #ifndef CONFIG_8260_CLKIN
64 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
67 #define BOOTFLASH_START 0xFE000000
69 #define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
71 #define MTDPARTS_DEFAULT "mtdparts=" \
77 "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
80 * Default environment settings
82 #define CONFIG_EXTRA_ENV_SETTINGS \
84 "EEprom_ivm=pca9544a:70:4 \0" \
87 "prot off 0xFE0C0000 +0x40000 && " \
88 "era 0xFE0C0000 +0x40000\0" \
89 "rootpath=/opt/eldk/ppc_82xx\0" \
92 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
93 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
94 #define CONFIG_SYS_RAMBOOT
97 #define CONFIG_SYS_MONITOR_LEN (768 << 10)
99 #define CONFIG_ENV_IS_IN_FLASH
101 #ifdef CONFIG_ENV_IS_IN_FLASH
102 #define CONFIG_ENV_SECT_SIZE 0x20000
103 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
104 CONFIG_SYS_MONITOR_LEN)
105 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
107 /* Address and size of Redundant Environment Sector */
108 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
109 CONFIG_ENV_SECT_SIZE)
110 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
111 #endif /* CONFIG_ENV_IS_IN_FLASH */
113 /* enable I2C and select the hardware/software driver */
114 #undef CONFIG_HARD_I2C /* I2C with hardware support */
115 #define CONFIG_SOFT_I2C /* I2C bit-banged */
116 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */
117 #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
120 * Software (bit-bang) I2C driver configuration
123 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
124 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
125 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
126 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
127 #define I2C_SDA(bit) do { \
129 iop->pdat |= 0x00010000; \
131 iop->pdat &= ~0x00010000; \
133 #define I2C_SCL(bit) do { \
135 iop->pdat |= 0x00020000; \
137 iop->pdat &= ~0x00020000; \
139 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
141 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
142 #define CONFIG_DTT_LM75 /* ON Semi's LM75 */
143 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
144 #define CONFIG_SYS_DTT_MAX_TEMP 70
145 #define CONFIG_SYS_DTT_LOW_TEMP -30
146 #define CONFIG_SYS_DTT_HYSTERESIS 3
147 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
151 #define CONFIG_SYS_IMMR 0xF0000000
153 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
154 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */
155 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
156 GENERATED_GBL_DATA_SIZE)
157 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
159 /* Hard reset configuration word */
160 #define CONFIG_SYS_HRCW_MASTER 0x0604b211
163 #define CONFIG_SYS_HRCW_SLAVE1 0
164 #define CONFIG_SYS_HRCW_SLAVE2 0
165 #define CONFIG_SYS_HRCW_SLAVE3 0
166 #define CONFIG_SYS_HRCW_SLAVE4 0
167 #define CONFIG_SYS_HRCW_SLAVE5 0
168 #define CONFIG_SYS_HRCW_SLAVE6 0
169 #define CONFIG_SYS_HRCW_SLAVE7 0
171 /* Initial Memory map for Linux */
172 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
174 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
175 #if defined(CONFIG_CMD_KGDB)
176 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
179 #define CONFIG_SYS_HID0_INIT 0
180 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
182 #define CONFIG_SYS_HID2 0
184 #define CONFIG_SYS_SIUMCR 0x4020c200
185 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
186 #define CONFIG_SYS_BCR 0x10000000
187 #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
190 *-----------------------------------------------------------------------
191 * RMR - Reset Mode Register 5-5
192 *-----------------------------------------------------------------------
193 * turn on Checkstop Reset Enable
195 #define CONFIG_SYS_RMR 0
198 *-----------------------------------------------------------------------
199 * TMCNTSC - Time Counter Status and Control 4-40
200 *-----------------------------------------------------------------------
201 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
202 * and enable Time Counter
204 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
207 *-----------------------------------------------------------------------
208 * PISCR - Periodic Interrupt Status and Control 4-42
209 *-----------------------------------------------------------------------
210 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
213 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
216 *-----------------------------------------------------------------------
217 * RCCR - RISC Controller Configuration 13-7
218 *-----------------------------------------------------------------------
220 #define CONFIG_SYS_RCCR 0
223 * Init Memory Controller:
225 * Bank Bus Machine PortSz Device
226 * ---- --- ------- ------ ------
227 * 0 60x GPCM 8 bit FLASH
228 * 1 60x SDRAM 32 bit SDRAM
229 * 3 60x GPCM 8 bit GPIO/PIGGY
230 * 5 60x GPCM 16 bit CFG-Flash
235 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
240 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
246 #define CONFIG_SYS_MPTPR 0x1800
249 *-----------------------------------------------------------------------------
250 * Address for Mode Register Set (MRS) command
251 *-----------------------------------------------------------------------------
253 #define CONFIG_SYS_MRS_OFFS 0x00000110
254 #define CONFIG_SYS_PSRT 0x0e
256 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
261 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
264 * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
266 #define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000
267 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
269 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
270 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
272 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
273 ORxG_CSNT | ORxG_ACS_DIV2 |\
274 ORxG_SCY_3_CLK | ORxG_TRLX)
277 * BFTICU board FPGA on CS4 initialization values
279 #define CONFIG_SYS_FPGA_BASE 0x40000000
280 #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
282 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
283 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
285 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
286 ORxG_CSNT | ORxG_ACS_DIV2 |\
287 ORxG_SCY_3_CLK | ORxG_TRLX)
290 * CFG-Flash on CS5 initialization values
292 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
293 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
295 #define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
296 CONFIG_SYS_FLASH_SIZE_2) |\
297 ORxG_CSNT | ORxG_ACS_DIV2 |\
298 ORxG_SCY_5_CLK | ORxG_TRLX)
300 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
302 /* pass open firmware flat tree */
304 #define CONFIG_OF_LIBFDT 1
305 #define CONFIG_OF_BOARD_SETUP 1
307 #define OF_TBCLK (bd->bi_busfreq / 4)
308 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
310 #endif /* __KM82XX_COMMON */