include/configs/kmeter1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008-2011
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_QE               /* Has QE */
  27 #define CONFIG_MPC8360          /* MPC8360 CPU specific */
  28 #define CONFIG_KMETER1          /* KMETER1 board specific */
  29 #define CONFIG_HOSTNAME         kmeter1
  30 #define CONFIG_KM_BOARD_NAME   "kmeter1"
  31
  32 #define CONFIG_SYS_TEXT_BASE    0xF0000000
  33 #define CONFIG_KM_DEF_NETDEV    \
  34         "netdev=eth2\0"         \
  35
  36 /* include common defines/options for all 83xx Keymile boards */
  37 #include "km/km83xx-common.h"
  38
  39 #define CONFIG_MISC_INIT_R
  40 /*
  41  * System IO Setup
  42  */
  43 #define CONFIG_SYS_SICRH                (SICRH_UC1EOBI | SICRH_UC2E1OBI)
  44
  45 /*
  46  * Hardware Reset Configuration Word
  47  */
  48 #define CONFIG_SYS_HRCW_LOW (\
  49         HRCWL_CSB_TO_CLKIN_4X1 | \
  50         HRCWL_CORE_TO_CSB_2X1 | \
  51         HRCWL_CE_PLL_VCO_DIV_2 | \
  52         HRCWL_CE_TO_PLL_1X6)
  53
  54 #define CONFIG_SYS_HRCW_HIGH (\
  55         HRCWH_CORE_ENABLE | \
  56         HRCWH_FROM_0X00000100 | \
  57         HRCWH_BOOTSEQ_DISABLE | \
  58         HRCWH_SW_WATCHDOG_DISABLE | \
  59         HRCWH_ROM_LOC_LOCAL_16BIT | \
  60         HRCWH_BIG_ENDIAN | \
  61         HRCWH_LALE_EARLY | \
  62         HRCWH_LDP_CLEAR)
  63
  64 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  65 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  66                                          SDRAM_CFG_SREN)
  67 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  68 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  69 #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  70                                  (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
  71
  72 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
  73                                          CSCONFIG_ROW_BIT_13 | \
  74                                          CSCONFIG_COL_BIT_10 | \
  75                                          CSCONFIG_ODT_WR_ONLY_CURRENT)
  76
  77 #define CONFIG_SYS_DDRCDR               (DDRCDR_EN | DDRCDR_Q_DRN)
  78                                         /* 0x40000001 */
  79 #define CONFIG_SYS_DDR_MODE             0x47860452
  80 #define CONFIG_SYS_DDR_MODE2            0x8080c000
  81
  82 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  83                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  84                                  (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  85                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  86                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
  87                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
  88                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
  89                                  (0 << TIMING_CFG0_RWT_SHIFT))
  90
  91 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
  92                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  93                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  94                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
  95                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
  96                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  97                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  98                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
  99
 100 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 101                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 102                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 103                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 104                                  (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 105                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 106                                  (5 << TIMING_CFG2_CPO_SHIFT))
 107
 108 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 109
 110 /* PRIO FPGA */
 111 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 112 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 113 /* PAXE FPGA */
 114 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 115 #define CONFIG_SYS_PAXE_SIZE            512
 116
 117 /* EEprom support */
 118 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 119
 120 /*
 121  * Local Bus Configuration & Clock Setup
 122  */
 123 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 124 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_2
 125 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 126
 127 /*
 128  * Init Local Bus Memory Controller:
 129  *
 130  * Bank Bus     Machine PortSz  Size  Device
 131  * ---- ---     ------- ------  -----  ------
 132  *  3   Local   GPCM     8 bit  512MB PAXE
 133  *
 134  */
 135
 136 /*
 137  * PAXE on the local bus CS3
 138  */
 139 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE
 140 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 141
 142 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
 143                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 144                                 BR_V)
 145 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 146                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 147                                 OR_GPCM_SCY_2 | \
 148                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 149
 150 /*
 151  * MMU Setup
 152  */
 153
 154 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 155 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
 156                                  BATL_MEMCOHERENCE)
 157 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
 158                                  BATU_VS | BATU_VP)
 159 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
 160                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 161 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 162
 163 #ifdef CONFIG_PCI
 164 /* PCI MEM space: cacheable */
 165 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE)
 166 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 167 #define CFG_DBAT6L      CFG_IBAT6L
 168 #define CFG_DBAT6U      CFG_IBAT6U
 169 /* PCI MMIO space: cache-inhibit and guarded */
 170 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_RW | \
 171                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 172 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 173 #define CFG_DBAT7L      CFG_IBAT7L
 174 #define CFG_DBAT7U      CFG_IBAT7U
 175 #else /* CONFIG_PCI */
 176 #define CONFIG_SYS_IBAT6L       (0)
 177 #define CONFIG_SYS_IBAT6U       (0)
 178 #define CONFIG_SYS_IBAT7L       (0)
 179 #define CONFIG_SYS_IBAT7U       (0)
 180 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 181 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 182 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 183 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 184 #endif /* CONFIG_PCI */
 185
 186 #endif /* __CONFIG_H */