2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_SYS_GENERIC_BOARD
13 #define CONFIG_DISPLAY_CPUINFO
14 #define CONFIG_DISPLAY_BOARDINFO
16 #define CONFIG_SKIP_LOWLEVEL_INIT
17 #define CONFIG_BOARD_EARLY_INIT_F
19 #define CONFIG_DEEP_SLEEP
20 #if defined(CONFIG_DEEP_SLEEP)
21 #define CONFIG_SILENT_CONSOLE
25 * Size of malloc() pool
27 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
29 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
30 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
33 * Generic Timer Definitions
35 #define GENERIC_TIMER_CLK 12500000
38 unsigned long get_board_sys_clk(void);
39 unsigned long get_board_ddr_clk(void);
42 #ifdef CONFIG_QSPI_BOOT
43 #define CONFIG_SYS_CLK_FREQ 100000000
44 #define CONFIG_DDR_CLK_FREQ 100000000
45 #define CONFIG_QIXIS_I2C_ACCESS
47 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
48 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
51 #ifdef CONFIG_RAMBOOT_PBL
52 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
57 #define CONFIG_SPL_FRAMEWORK
58 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
59 #define CONFIG_SPL_LIBCOMMON_SUPPORT
60 #define CONFIG_SPL_LIBGENERIC_SUPPORT
61 #define CONFIG_SPL_ENV_SUPPORT
62 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
63 #define CONFIG_SPL_I2C_SUPPORT
64 #define CONFIG_SPL_WATCHDOG_SUPPORT
65 #define CONFIG_SPL_SERIAL_SUPPORT
66 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
67 #define CONFIG_SPL_MMC_SUPPORT
68 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
69 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
71 #define CONFIG_SPL_TEXT_BASE 0x10000000
72 #define CONFIG_SPL_MAX_SIZE 0x1a000
73 #define CONFIG_SPL_STACK 0x1001d000
74 #define CONFIG_SPL_PAD_TO 0x1c000
75 #define CONFIG_SYS_TEXT_BASE 0x82000000
77 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
78 CONFIG_SYS_MONITOR_LEN)
79 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
80 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
81 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
82 #define CONFIG_SYS_MONITOR_LEN 0x80000
85 #ifdef CONFIG_QSPI_BOOT
86 #define CONFIG_SYS_TEXT_BASE 0x40010000
87 #define CONFIG_SYS_NO_FLASH
90 #ifdef CONFIG_NAND_BOOT
91 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
92 #define CONFIG_SPL_FRAMEWORK
93 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
94 #define CONFIG_SPL_LIBCOMMON_SUPPORT
95 #define CONFIG_SPL_LIBGENERIC_SUPPORT
96 #define CONFIG_SPL_ENV_SUPPORT
97 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
98 #define CONFIG_SPL_I2C_SUPPORT
99 #define CONFIG_SPL_WATCHDOG_SUPPORT
100 #define CONFIG_SPL_SERIAL_SUPPORT
101 #define CONFIG_SPL_NAND_SUPPORT
102 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
104 #define CONFIG_SPL_TEXT_BASE 0x10000000
105 #define CONFIG_SPL_MAX_SIZE 0x1a000
106 #define CONFIG_SPL_STACK 0x1001d000
107 #define CONFIG_SPL_PAD_TO 0x1c000
108 #define CONFIG_SYS_TEXT_BASE 0x82000000
110 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
111 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
112 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
113 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
114 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
116 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
117 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
118 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
119 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
120 #define CONFIG_SYS_MONITOR_LEN 0x80000
123 #ifndef CONFIG_SYS_TEXT_BASE
124 #define CONFIG_SYS_TEXT_BASE 0x60100000
127 #define CONFIG_NR_DRAM_BANKS 1
129 #define CONFIG_DDR_SPD
130 #define SPD_EEPROM_ADDRESS 0x51
131 #define CONFIG_SYS_SPD_BUS_NUM 0
133 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
134 #ifndef CONFIG_SYS_FSL_DDR4
135 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
136 #define CONFIG_SYS_DDR_RAW_TIMING
138 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
139 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
141 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
142 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
144 #define CONFIG_DDR_ECC
145 #ifdef CONFIG_DDR_ECC
146 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
147 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
150 #define CONFIG_SYS_HAS_SERDES
152 #define CONFIG_FSL_CAAM /* Enable CAAM */
154 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
155 !defined(CONFIG_QSPI_BOOT)
162 #ifndef CONFIG_QSPI_BOOT
163 #define CONFIG_FSL_IFC
164 #define CONFIG_SYS_FLASH_BASE 0x60000000
165 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
167 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
168 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
169 CSPR_PORT_SIZE_16 | \
172 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
173 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
175 CSPR_PORT_SIZE_16 | \
178 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
180 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
182 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
183 FTIM0_NOR_TEADC(0x5) | \
184 FTIM0_NOR_TEAHC(0x5))
185 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
186 FTIM1_NOR_TRAD_NOR(0x1a) | \
187 FTIM1_NOR_TSEQRAD_NOR(0x13))
188 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
189 FTIM2_NOR_TCH(0x4) | \
190 FTIM2_NOR_TWPH(0xe) | \
192 #define CONFIG_SYS_NOR_FTIM3 0
194 #define CONFIG_FLASH_CFI_DRIVER
195 #define CONFIG_SYS_FLASH_CFI
196 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
197 #define CONFIG_SYS_FLASH_QUIET_TEST
198 #define CONFIG_FLASH_SHOW_PROGRESS 45
199 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
200 #define CONFIG_SYS_WRITE_SWAPPED_DATA
202 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
204 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
205 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
207 #define CONFIG_SYS_FLASH_EMPTY_INFO
208 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
209 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
212 * NAND Flash Definitions
214 #define CONFIG_NAND_FSL_IFC
216 #define CONFIG_SYS_NAND_BASE 0x7e800000
217 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
219 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
221 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
225 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
226 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
227 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
228 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
229 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
230 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
231 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
232 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
234 #define CONFIG_SYS_NAND_ONFI_DETECTION
236 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
237 FTIM0_NAND_TWP(0x18) | \
238 FTIM0_NAND_TWCHT(0x7) | \
240 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
241 FTIM1_NAND_TWBE(0x39) | \
242 FTIM1_NAND_TRR(0xe) | \
243 FTIM1_NAND_TRP(0x18))
244 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
245 FTIM2_NAND_TREH(0xa) | \
246 FTIM2_NAND_TWHRE(0x1e))
247 #define CONFIG_SYS_NAND_FTIM3 0x0
249 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
250 #define CONFIG_SYS_MAX_NAND_DEVICE 1
251 #define CONFIG_CMD_NAND
253 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
259 #define CONFIG_FSL_QIXIS
261 #ifdef CONFIG_FSL_QIXIS
262 #define QIXIS_BASE 0x7fb00000
263 #define QIXIS_BASE_PHYS QIXIS_BASE
264 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
265 #define QIXIS_LBMAP_SWITCH 6
266 #define QIXIS_LBMAP_MASK 0x0f
267 #define QIXIS_LBMAP_SHIFT 0
268 #define QIXIS_LBMAP_DFLTBANK 0x00
269 #define QIXIS_LBMAP_ALTBANK 0x04
270 #define QIXIS_RST_CTL_RESET 0x44
271 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
272 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
273 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
275 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
276 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
280 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
281 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
282 CSOR_NOR_NOR_MODE_AVD_NOR | \
286 * QIXIS Timing parameters for IFC GPCM
288 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
289 FTIM0_GPCM_TEADC(0xe) | \
290 FTIM0_GPCM_TEAHC(0xe))
291 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
292 FTIM1_GPCM_TRAD(0x1f))
293 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
294 FTIM2_GPCM_TCH(0xe) | \
295 FTIM2_GPCM_TWP(0xf0))
296 #define CONFIG_SYS_FPGA_FTIM3 0x0
299 #if defined(CONFIG_NAND_BOOT)
300 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
301 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
302 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
303 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
304 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
305 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
306 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
307 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
308 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
309 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
310 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
311 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
312 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
313 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
314 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
315 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
316 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
317 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
318 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
319 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
320 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
321 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
322 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
323 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
324 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
325 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
326 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
327 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
328 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
329 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
330 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
331 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
333 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
334 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
335 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
336 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
337 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
338 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
339 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
340 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
341 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
342 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
343 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
344 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
345 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
346 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
347 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
348 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
349 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
350 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
351 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
352 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
353 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
354 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
355 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
356 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
357 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
358 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
359 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
360 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
361 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
362 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
363 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
364 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
371 #define CONFIG_FSL_LPUART
372 #define CONFIG_LPUART_32B_REG
374 #define CONFIG_CONS_INDEX 1
375 #define CONFIG_SYS_NS16550
376 #define CONFIG_SYS_NS16550_SERIAL
377 #define CONFIG_SYS_NS16550_REG_SIZE 1
378 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
381 #define CONFIG_BAUDRATE 115200
386 #define CONFIG_CMD_I2C
387 #define CONFIG_SYS_I2C
388 #define CONFIG_SYS_I2C_MXC
389 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
392 * I2C bus multiplexer
394 #define I2C_MUX_PCA_ADDR_PRI 0x77
395 #define I2C_MUX_CH_DEFAULT 0x8
396 #define I2C_MUX_CH_CH7301 0xC
402 #define CONFIG_CMD_MMC
403 #define CONFIG_FSL_ESDHC
404 #define CONFIG_GENERIC_MMC
406 #define CONFIG_CMD_FAT
407 #define CONFIG_DOS_PARTITION
410 #ifdef CONFIG_QSPI_BOOT
412 #define CONFIG_FSL_QSPI
413 #define QSPI0_AMBA_BASE 0x40000000
414 #define FSL_QSPI_FLASH_SIZE (1 << 24)
415 #define FSL_QSPI_FLASH_NUM 2
416 #define CONFIG_SPI_FLASH_SPANSION
419 #define CONFIG_FSL_DSPI
422 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
423 #define CONFIG_CMD_SF
424 #define CONFIG_DM_SPI_FLASH
425 #define CONFIG_SPI_FLASH_DATAFLASH
432 #define CONFIG_HAS_FSL_DR_USB
434 #ifdef CONFIG_HAS_FSL_DR_USB
435 #define CONFIG_USB_EHCI
437 #ifdef CONFIG_USB_EHCI
438 #define CONFIG_CMD_USB
439 #define CONFIG_USB_STORAGE
440 #define CONFIG_USB_EHCI_FSL
441 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
442 #define CONFIG_CMD_EXT2
449 #define CONFIG_FSL_DCU_FB
451 #ifdef CONFIG_FSL_DCU_FB
453 #define CONFIG_CMD_BMP
454 #define CONFIG_CFB_CONSOLE
455 #define CONFIG_VGA_AS_SINGLE_DEVICE
456 #define CONFIG_VIDEO_LOGO
457 #define CONFIG_VIDEO_BMP_LOGO
459 #define CONFIG_FSL_DIU_CH7301
460 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
461 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
462 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
468 #define CONFIG_TSEC_ENET
470 #ifdef CONFIG_TSEC_ENET
472 #define CONFIG_MII_DEFAULT_TSEC 3
473 #define CONFIG_TSEC1 1
474 #define CONFIG_TSEC1_NAME "eTSEC1"
475 #define CONFIG_TSEC2 1
476 #define CONFIG_TSEC2_NAME "eTSEC2"
477 #define CONFIG_TSEC3 1
478 #define CONFIG_TSEC3_NAME "eTSEC3"
480 #define TSEC1_PHY_ADDR 1
481 #define TSEC2_PHY_ADDR 2
482 #define TSEC3_PHY_ADDR 3
484 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
485 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
486 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
488 #define TSEC1_PHYIDX 0
489 #define TSEC2_PHYIDX 0
490 #define TSEC3_PHYIDX 0
492 #define CONFIG_ETHPRIME "eTSEC1"
494 #define CONFIG_PHY_GIGE
495 #define CONFIG_PHYLIB
496 #define CONFIG_PHY_REALTEK
498 #define CONFIG_HAS_ETH0
499 #define CONFIG_HAS_ETH1
500 #define CONFIG_HAS_ETH2
502 #define CONFIG_FSL_SGMII_RISER 1
503 #define SGMII_RISER_PHY_OFFSET 0x1b
505 #ifdef CONFIG_FSL_SGMII_RISER
506 #define CONFIG_SYS_TBIPA_VALUE 8
512 #define CONFIG_PCI /* Enable PCI/PCIE */
513 #define CONFIG_PCIE1 /* PCIE controler 1 */
514 #define CONFIG_PCIE2 /* PCIE controler 2 */
515 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
516 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
518 #define CONFIG_SYS_PCI_64BIT
520 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
521 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
522 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
523 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
525 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
526 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
527 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
529 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
530 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
531 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
534 #define CONFIG_PCI_PNP
536 #define CONFIG_PCI_SCAN_SHOW
537 #define CONFIG_CMD_PCI
540 #define CONFIG_CMD_PING
541 #define CONFIG_CMD_DHCP
542 #define CONFIG_CMD_MII
544 #define CONFIG_CMDLINE_TAG
545 #define CONFIG_CMDLINE_EDITING
547 #define CONFIG_ARMV7_NONSEC
548 #define CONFIG_ARMV7_VIRT
549 #define CONFIG_PEN_ADDR_BIG_ENDIAN
550 #define CONFIG_LS102XA_NS_ACCESS
551 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
552 #define CONFIG_TIMER_CLK_FREQ 12500000
553 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
555 #define CONFIG_HWCONFIG
556 #define HWCONFIG_BUFFER_SIZE 128
558 #define CONFIG_BOOTDELAY 3
560 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
563 #define CONFIG_EXTRA_ENV_SETTINGS \
564 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
565 "fdt_high=0xcfffffff\0" \
566 "initrd_high=0xcfffffff\0" \
567 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
569 #define CONFIG_EXTRA_ENV_SETTINGS \
570 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
571 "fdt_high=0xcfffffff\0" \
572 "initrd_high=0xcfffffff\0" \
573 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
577 * Miscellaneous configurable options
579 #define CONFIG_SYS_LONGHELP /* undef to save memory */
580 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
581 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
582 #define CONFIG_AUTO_COMPLETE
583 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
584 #define CONFIG_SYS_PBSIZE \
585 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
586 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
587 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
589 #define CONFIG_CMD_GREPENV
590 #define CONFIG_CMD_MEMINFO
591 #define CONFIG_CMD_MEMTEST
592 #define CONFIG_SYS_MEMTEST_START 0x80000000
593 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
595 #define CONFIG_SYS_LOAD_ADDR 0x82000000
597 #define CONFIG_LS102XA_STREAM_ID
601 * The stack sizes are set up in start.S using the settings below
603 #define CONFIG_STACKSIZE (30 * 1024)
605 #define CONFIG_SYS_INIT_SP_OFFSET \
606 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
607 #define CONFIG_SYS_INIT_SP_ADDR \
608 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
610 #ifdef CONFIG_SPL_BUILD
611 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
613 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
619 #define CONFIG_ENV_OVERWRITE
621 #if defined(CONFIG_SD_BOOT)
622 #define CONFIG_ENV_OFFSET 0x100000
623 #define CONFIG_ENV_IS_IN_MMC
624 #define CONFIG_SYS_MMC_ENV_DEV 0
625 #define CONFIG_ENV_SIZE 0x2000
626 #elif defined(CONFIG_QSPI_BOOT)
627 #define CONFIG_ENV_IS_IN_SPI_FLASH
628 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
629 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
630 #define CONFIG_ENV_SECT_SIZE 0x10000
631 #elif defined(CONFIG_NAND_BOOT)
632 #define CONFIG_ENV_IS_IN_NAND
633 #define CONFIG_ENV_SIZE 0x2000
634 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
636 #define CONFIG_ENV_IS_IN_FLASH
637 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
638 #define CONFIG_ENV_SIZE 0x2000
639 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
642 #define CONFIG_OF_LIBFDT
643 #define CONFIG_OF_BOARD_SETUP
644 #define CONFIG_CMD_BOOTZ
646 #define CONFIG_MISC_INIT_R
648 /* Hash command with SHA acceleration supported in hardware */
649 #define CONFIG_CMD_HASH
650 #define CONFIG_SHA_HW_ACCEL
652 #ifdef CONFIG_SECURE_BOOT
653 #define CONFIG_CMD_BLOB
654 #include <asm/fsl_secure_boot.h>