2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_ARMV7_PSCI
13 #define CONFIG_SYS_GENERIC_BOARD
15 #define CONFIG_DISPLAY_CPUINFO
16 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_SKIP_LOWLEVEL_INIT
19 #define CONFIG_BOARD_EARLY_INIT_F
22 * Size of malloc() pool
24 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
26 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
27 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
34 * EHCI Support - disbaled by default as
35 * there is no signal coming out of soc on
36 * this board for this controller. However,
37 * the silicon still has this controller,
38 * and anyone can use this controller by
39 * taking signals out on their board.
42 /*#define CONFIG_HAS_FSL_DR_USB*/
44 #ifdef CONFIG_HAS_FSL_DR_USB
45 #define CONFIG_USB_EHCI
46 #define CONFIG_USB_EHCI_FSL
47 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
50 /* XHCI Support - enabled by default */
51 #define CONFIG_HAS_FSL_XHCI_USB
53 #ifdef CONFIG_HAS_FSL_XHCI_USB
54 #define CONFIG_USB_XHCI_FSL
55 #define CONFIG_USB_XHCI_DWC3
56 #define CONFIG_USB_XHCI
57 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
58 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
61 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
62 #define CONFIG_CMD_USB
63 #define CONFIG_USB_STORAGE
64 #define CONFIG_CMD_EXT2
68 * Generic Timer Definitions
70 #define GENERIC_TIMER_CLK 12500000
72 #define CONFIG_SYS_CLK_FREQ 100000000
73 #define CONFIG_DDR_CLK_FREQ 100000000
75 #define DDR_SDRAM_CFG 0x470c0008
76 #define DDR_CS0_BNDS 0x008000bf
77 #define DDR_CS0_CONFIG 0x80014302
78 #define DDR_TIMING_CFG_0 0x50550004
79 #define DDR_TIMING_CFG_1 0xbcb38c56
80 #define DDR_TIMING_CFG_2 0x0040d120
81 #define DDR_TIMING_CFG_3 0x010e1000
82 #define DDR_TIMING_CFG_4 0x00000001
83 #define DDR_TIMING_CFG_5 0x03401400
84 #define DDR_SDRAM_CFG_2 0x00401010
85 #define DDR_SDRAM_MODE 0x00061c60
86 #define DDR_SDRAM_MODE_2 0x00180000
87 #define DDR_SDRAM_INTERVAL 0x18600618
88 #define DDR_DDR_WRLVL_CNTL 0x8655f605
89 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
90 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
91 #define DDR_DDR_CDR1 0x80040000
92 #define DDR_DDR_CDR2 0x00000001
93 #define DDR_SDRAM_CLK_CNTL 0x02000000
94 #define DDR_DDR_ZQ_CNTL 0x89080600
95 #define DDR_CS0_CONFIG_2 0
96 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
98 #ifdef CONFIG_RAMBOOT_PBL
99 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
102 #ifdef CONFIG_SD_BOOT
103 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
104 #define CONFIG_SPL_FRAMEWORK
105 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
106 #define CONFIG_SPL_LIBCOMMON_SUPPORT
107 #define CONFIG_SPL_LIBGENERIC_SUPPORT
108 #define CONFIG_SPL_ENV_SUPPORT
109 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
110 #define CONFIG_SPL_I2C_SUPPORT
111 #define CONFIG_SPL_WATCHDOG_SUPPORT
112 #define CONFIG_SPL_SERIAL_SUPPORT
113 #define CONFIG_SPL_MMC_SUPPORT
114 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
115 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
117 #define CONFIG_SPL_TEXT_BASE 0x10000000
118 #define CONFIG_SPL_MAX_SIZE 0x1a000
119 #define CONFIG_SPL_STACK 0x1001d000
120 #define CONFIG_SPL_PAD_TO 0x1c000
121 #define CONFIG_SYS_TEXT_BASE 0x82000000
123 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
124 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
125 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
126 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
127 #define CONFIG_SYS_MONITOR_LEN 0x80000
130 #ifdef CONFIG_QSPI_BOOT
131 #define CONFIG_SYS_TEXT_BASE 0x40010000
132 #define CONFIG_SYS_NO_FLASH
135 #ifndef CONFIG_SYS_TEXT_BASE
136 #define CONFIG_SYS_TEXT_BASE 0x60100000
139 #define CONFIG_NR_DRAM_BANKS 1
140 #define PHYS_SDRAM 0x80000000
141 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
143 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
146 #define CONFIG_SYS_HAS_SERDES
148 #define CONFIG_FSL_CAAM /* Enable CAAM */
150 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
151 !defined(CONFIG_QSPI_BOOT)
158 #ifndef CONFIG_QSPI_BOOT
159 #define CONFIG_FSL_IFC
160 #define CONFIG_SYS_FLASH_BASE 0x60000000
161 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
163 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
164 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
165 CSPR_PORT_SIZE_16 | \
168 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
170 /* NOR Flash Timing Params */
171 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
173 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
174 FTIM0_NOR_TEADC(0x5) | \
175 FTIM0_NOR_TAVDS(0x0) | \
176 FTIM0_NOR_TEAHC(0x5))
177 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
178 FTIM1_NOR_TRAD_NOR(0x1A) | \
179 FTIM1_NOR_TSEQRAD_NOR(0x13))
180 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
181 FTIM2_NOR_TCH(0x4) | \
182 FTIM2_NOR_TWP(0x1c) | \
183 FTIM2_NOR_TWPH(0x0e))
184 #define CONFIG_SYS_NOR_FTIM3 0
186 #define CONFIG_FLASH_CFI_DRIVER
187 #define CONFIG_SYS_FLASH_CFI
188 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
189 #define CONFIG_SYS_FLASH_QUIET_TEST
190 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
192 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
193 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
194 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
195 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
197 #define CONFIG_SYS_FLASH_EMPTY_INFO
198 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
200 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
201 #define CONFIG_SYS_WRITE_SWAPPED_DATA
206 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
207 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
209 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
210 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
214 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
215 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
216 CSOR_NOR_NOR_MODE_AVD_NOR | \
219 /* CPLD Timing parameters for IFC GPCM */
220 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
221 FTIM0_GPCM_TEADC(0xf) | \
222 FTIM0_GPCM_TEAHC(0xf))
223 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
224 FTIM1_GPCM_TRAD(0x3f))
225 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
226 FTIM2_GPCM_TCH(0xf) | \
227 FTIM2_GPCM_TWP(0xff))
228 #define CONFIG_SYS_FPGA_FTIM3 0x0
229 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
230 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
231 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
232 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
233 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
234 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
235 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
236 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
237 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
238 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
239 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
240 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
241 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
242 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
243 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
244 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
250 #define CONFIG_FSL_LPUART
251 #define CONFIG_LPUART_32B_REG
253 #define CONFIG_CONS_INDEX 1
254 #define CONFIG_SYS_NS16550
255 #define CONFIG_SYS_NS16550_SERIAL
256 #define CONFIG_SYS_NS16550_REG_SIZE 1
257 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
260 #define CONFIG_BAUDRATE 115200
265 #define CONFIG_CMD_I2C
266 #define CONFIG_SYS_I2C
267 #define CONFIG_SYS_I2C_MXC
268 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
271 #ifndef CONFIG_SD_BOOT
272 #define CONFIG_ID_EEPROM
273 #define CONFIG_SYS_I2C_EEPROM_NXID
274 #define CONFIG_SYS_EEPROM_BUS_NUM 1
275 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
276 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
277 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
278 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
285 #define CONFIG_CMD_MMC
286 #define CONFIG_FSL_ESDHC
287 #define CONFIG_GENERIC_MMC
289 #define CONFIG_CMD_FAT
290 #define CONFIG_DOS_PARTITION
293 #ifdef CONFIG_QSPI_BOOT
295 #define CONFIG_FSL_QSPI
296 #define QSPI0_AMBA_BASE 0x40000000
297 #define FSL_QSPI_FLASH_SIZE (1 << 24)
298 #define FSL_QSPI_FLASH_NUM 2
299 #define CONFIG_SPI_FLASH_STMICRO
302 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
303 #define CONFIG_CMD_SF
304 #define CONFIG_DM_SPI_FLASH
311 #define CONFIG_FSL_DCU_FB
313 #ifdef CONFIG_FSL_DCU_FB
315 #define CONFIG_CMD_BMP
316 #define CONFIG_CFB_CONSOLE
317 #define CONFIG_VGA_AS_SINGLE_DEVICE
318 #define CONFIG_VIDEO_LOGO
319 #define CONFIG_VIDEO_BMP_LOGO
321 #define CONFIG_FSL_DCU_SII9022A
322 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
323 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
329 #define CONFIG_TSEC_ENET
331 #ifdef CONFIG_TSEC_ENET
333 #define CONFIG_MII_DEFAULT_TSEC 1
334 #define CONFIG_TSEC1 1
335 #define CONFIG_TSEC1_NAME "eTSEC1"
336 #define CONFIG_TSEC2 1
337 #define CONFIG_TSEC2_NAME "eTSEC2"
338 #define CONFIG_TSEC3 1
339 #define CONFIG_TSEC3_NAME "eTSEC3"
341 #define TSEC1_PHY_ADDR 2
342 #define TSEC2_PHY_ADDR 0
343 #define TSEC3_PHY_ADDR 1
345 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
346 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
347 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
349 #define TSEC1_PHYIDX 0
350 #define TSEC2_PHYIDX 0
351 #define TSEC3_PHYIDX 0
353 #define CONFIG_ETHPRIME "eTSEC1"
355 #define CONFIG_PHY_GIGE
356 #define CONFIG_PHYLIB
357 #define CONFIG_PHY_ATHEROS
359 #define CONFIG_HAS_ETH0
360 #define CONFIG_HAS_ETH1
361 #define CONFIG_HAS_ETH2
365 #define CONFIG_PCI /* Enable PCI/PCIE */
366 #define CONFIG_PCIE1 /* PCIE controler 1 */
367 #define CONFIG_PCIE2 /* PCIE controler 2 */
368 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
369 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
371 #define CONFIG_SYS_PCI_64BIT
373 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
374 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
375 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
376 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
378 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
379 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
380 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
382 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
383 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
384 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
387 #define CONFIG_PCI_PNP
389 #define CONFIG_PCI_SCAN_SHOW
390 #define CONFIG_CMD_PCI
393 #define CONFIG_CMD_PING
394 #define CONFIG_CMD_DHCP
395 #define CONFIG_CMD_MII
397 #define CONFIG_CMDLINE_TAG
398 #define CONFIG_CMDLINE_EDITING
400 #define CONFIG_ARMV7_NONSEC
401 #define CONFIG_ARMV7_VIRT
402 #define CONFIG_PEN_ADDR_BIG_ENDIAN
403 #define CONFIG_LS102XA_NS_ACCESS
404 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
405 #define CONFIG_TIMER_CLK_FREQ 12500000
406 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
408 #define CONFIG_HWCONFIG
409 #define HWCONFIG_BUFFER_SIZE 128
411 #define CONFIG_BOOTDELAY 3
414 #define CONFIG_EXTRA_ENV_SETTINGS \
415 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
416 "initrd_high=0xcfffffff\0" \
417 "fdt_high=0xcfffffff\0"
419 #define CONFIG_EXTRA_ENV_SETTINGS \
420 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
421 "initrd_high=0xcfffffff\0" \
422 "fdt_high=0xcfffffff\0"
426 * Miscellaneous configurable options
428 #define CONFIG_SYS_LONGHELP /* undef to save memory */
429 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
430 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
431 #define CONFIG_AUTO_COMPLETE
432 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
433 #define CONFIG_SYS_PBSIZE \
434 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
435 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
436 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
438 #define CONFIG_CMD_GREPENV
439 #define CONFIG_CMD_MEMINFO
440 #define CONFIG_CMD_MEMTEST
441 #define CONFIG_SYS_MEMTEST_START 0x80000000
442 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
444 #define CONFIG_SYS_LOAD_ADDR 0x82000000
446 #define CONFIG_LS102XA_STREAM_ID
450 * The stack sizes are set up in start.S using the settings below
452 #define CONFIG_STACKSIZE (30 * 1024)
454 #define CONFIG_SYS_INIT_SP_OFFSET \
455 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
456 #define CONFIG_SYS_INIT_SP_ADDR \
457 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
459 #ifdef CONFIG_SPL_BUILD
460 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
462 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
465 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
470 #define CONFIG_ENV_OVERWRITE
472 #if defined(CONFIG_SD_BOOT)
473 #define CONFIG_ENV_OFFSET 0x100000
474 #define CONFIG_ENV_IS_IN_MMC
475 #define CONFIG_SYS_MMC_ENV_DEV 0
476 #define CONFIG_ENV_SIZE 0x20000
477 #elif defined(CONFIG_QSPI_BOOT)
478 #define CONFIG_ENV_IS_IN_SPI_FLASH
479 #define CONFIG_ENV_SIZE 0x2000
480 #define CONFIG_ENV_OFFSET 0x100000
481 #define CONFIG_ENV_SECT_SIZE 0x10000
483 #define CONFIG_ENV_IS_IN_FLASH
484 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
485 #define CONFIG_ENV_SIZE 0x20000
486 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
489 #define CONFIG_OF_LIBFDT
490 #define CONFIG_OF_BOARD_SETUP
491 #define CONFIG_CMD_BOOTZ
493 #define CONFIG_MISC_INIT_R
495 /* Hash command with SHA acceleration supported in hardware */
496 #define CONFIG_CMD_HASH
497 #define CONFIG_SHA_HW_ACCEL
499 #ifdef CONFIG_SECURE_BOOT
500 #define CONFIG_CMD_BLOB