2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_SYS_GENERIC_BOARD
13 #define CONFIG_DISPLAY_CPUINFO
14 #define CONFIG_DISPLAY_BOARDINFO
16 #define CONFIG_SKIP_LOWLEVEL_INIT
17 #define CONFIG_BOARD_EARLY_INIT_F
20 * Size of malloc() pool
22 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
24 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
25 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
28 * Generic Timer Definitions
30 #define GENERIC_TIMER_CLK 12500000
32 #define CONFIG_SYS_CLK_FREQ 100000000
33 #define CONFIG_DDR_CLK_FREQ 100000000
35 #define DDR_SDRAM_CFG 0x470c0008
36 #define DDR_CS0_BNDS 0x008000bf
37 #define DDR_CS0_CONFIG 0x80014302
38 #define DDR_TIMING_CFG_0 0x50550004
39 #define DDR_TIMING_CFG_1 0xbcb38c56
40 #define DDR_TIMING_CFG_2 0x0040d120
41 #define DDR_TIMING_CFG_3 0x010e1000
42 #define DDR_TIMING_CFG_4 0x00000001
43 #define DDR_TIMING_CFG_5 0x03401400
44 #define DDR_SDRAM_CFG_2 0x00401010
45 #define DDR_SDRAM_MODE 0x00061c60
46 #define DDR_SDRAM_MODE_2 0x00180000
47 #define DDR_SDRAM_INTERVAL 0x18600618
48 #define DDR_DDR_WRLVL_CNTL 0x8655f605
49 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
50 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
51 #define DDR_DDR_CDR1 0x80040000
52 #define DDR_DDR_CDR2 0x00000001
53 #define DDR_SDRAM_CLK_CNTL 0x02000000
54 #define DDR_DDR_ZQ_CNTL 0x89080600
55 #define DDR_CS0_CONFIG_2 0
56 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
58 #ifdef CONFIG_RAMBOOT_PBL
59 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
64 #define CONFIG_SPL_FRAMEWORK
65 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
66 #define CONFIG_SPL_LIBCOMMON_SUPPORT
67 #define CONFIG_SPL_LIBGENERIC_SUPPORT
68 #define CONFIG_SPL_ENV_SUPPORT
69 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
70 #define CONFIG_SPL_I2C_SUPPORT
71 #define CONFIG_SPL_WATCHDOG_SUPPORT
72 #define CONFIG_SPL_SERIAL_SUPPORT
73 #define CONFIG_SPL_MMC_SUPPORT
74 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
75 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
77 #define CONFIG_SPL_TEXT_BASE 0x10000000
78 #define CONFIG_SPL_MAX_SIZE 0x1a000
79 #define CONFIG_SPL_STACK 0x1001d000
80 #define CONFIG_SPL_PAD_TO 0x1c000
81 #define CONFIG_SYS_TEXT_BASE 0x82000000
83 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
84 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
85 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
86 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
87 #define CONFIG_SYS_MONITOR_LEN 0x80000
90 #ifdef CONFIG_QSPI_BOOT
91 #define CONFIG_SYS_TEXT_BASE 0x40010000
92 #define CONFIG_SYS_NO_FLASH
95 #ifndef CONFIG_SYS_TEXT_BASE
96 #define CONFIG_SYS_TEXT_BASE 0x60100000
99 #define CONFIG_NR_DRAM_BANKS 1
100 #define PHYS_SDRAM 0x80000000
101 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
106 #define CONFIG_SYS_HAS_SERDES
108 #define CONFIG_FSL_CAAM /* Enable CAAM */
110 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
111 !defined(CONFIG_QSPI_BOOT)
118 #ifndef CONFIG_QSPI_BOOT
119 #define CONFIG_FSL_IFC
120 #define CONFIG_SYS_FLASH_BASE 0x60000000
121 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
123 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
124 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
125 CSPR_PORT_SIZE_16 | \
128 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
130 /* NOR Flash Timing Params */
131 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
133 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
134 FTIM0_NOR_TEADC(0x5) | \
135 FTIM0_NOR_TAVDS(0x0) | \
136 FTIM0_NOR_TEAHC(0x5))
137 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
138 FTIM1_NOR_TRAD_NOR(0x1A) | \
139 FTIM1_NOR_TSEQRAD_NOR(0x13))
140 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
141 FTIM2_NOR_TCH(0x4) | \
142 FTIM2_NOR_TWP(0x1c) | \
143 FTIM2_NOR_TWPH(0x0e))
144 #define CONFIG_SYS_NOR_FTIM3 0
146 #define CONFIG_FLASH_CFI_DRIVER
147 #define CONFIG_SYS_FLASH_CFI
148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
149 #define CONFIG_SYS_FLASH_QUIET_TEST
150 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
153 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
154 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
155 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
157 #define CONFIG_SYS_FLASH_EMPTY_INFO
158 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
160 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
161 #define CONFIG_SYS_WRITE_SWAPPED_DATA
166 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
167 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
169 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
170 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
174 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
175 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
176 CSOR_NOR_NOR_MODE_AVD_NOR | \
179 /* CPLD Timing parameters for IFC GPCM */
180 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
181 FTIM0_GPCM_TEADC(0xf) | \
182 FTIM0_GPCM_TEAHC(0xf))
183 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
184 FTIM1_GPCM_TRAD(0x3f))
185 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
186 FTIM2_GPCM_TCH(0xf) | \
187 FTIM2_GPCM_TWP(0xff))
188 #define CONFIG_SYS_FPGA_FTIM3 0x0
189 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
190 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
191 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
192 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
193 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
194 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
195 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
196 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
197 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
198 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
199 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
200 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
201 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
202 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
203 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
204 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
210 #define CONFIG_FSL_LPUART
211 #define CONFIG_LPUART_32B_REG
213 #define CONFIG_CONS_INDEX 1
214 #define CONFIG_SYS_NS16550
215 #define CONFIG_SYS_NS16550_SERIAL
216 #define CONFIG_SYS_NS16550_REG_SIZE 1
217 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
220 #define CONFIG_BAUDRATE 115200
225 #define CONFIG_CMD_I2C
226 #define CONFIG_SYS_I2C
227 #define CONFIG_SYS_I2C_MXC
228 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
231 #ifndef CONFIG_SD_BOOT
232 #define CONFIG_ID_EEPROM
233 #define CONFIG_SYS_I2C_EEPROM_NXID
234 #define CONFIG_SYS_EEPROM_BUS_NUM 1
235 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
236 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
245 #define CONFIG_CMD_MMC
246 #define CONFIG_FSL_ESDHC
247 #define CONFIG_GENERIC_MMC
249 #define CONFIG_CMD_FAT
250 #define CONFIG_DOS_PARTITION
253 #ifdef CONFIG_QSPI_BOOT
254 #define CONFIG_FSL_QSPI
255 #define QSPI0_AMBA_BASE 0x40000000
256 #define FSL_QSPI_FLASH_SIZE (1 << 24)
257 #define FSL_QSPI_FLASH_NUM 2
259 #define CONFIG_CMD_SF
260 #define CONFIG_SPI_FLASH_STMICRO
266 #define CONFIG_FSL_DCU_FB
268 #ifdef CONFIG_FSL_DCU_FB
270 #define CONFIG_CMD_BMP
271 #define CONFIG_CFB_CONSOLE
272 #define CONFIG_VGA_AS_SINGLE_DEVICE
273 #define CONFIG_VIDEO_LOGO
274 #define CONFIG_VIDEO_BMP_LOGO
276 #define CONFIG_FSL_DCU_SII9022A
277 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
278 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
284 #define CONFIG_TSEC_ENET
286 #ifdef CONFIG_TSEC_ENET
288 #define CONFIG_MII_DEFAULT_TSEC 1
289 #define CONFIG_TSEC1 1
290 #define CONFIG_TSEC1_NAME "eTSEC1"
291 #define CONFIG_TSEC2 1
292 #define CONFIG_TSEC2_NAME "eTSEC2"
293 #define CONFIG_TSEC3 1
294 #define CONFIG_TSEC3_NAME "eTSEC3"
296 #define TSEC1_PHY_ADDR 2
297 #define TSEC2_PHY_ADDR 0
298 #define TSEC3_PHY_ADDR 1
300 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
301 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
302 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
304 #define TSEC1_PHYIDX 0
305 #define TSEC2_PHYIDX 0
306 #define TSEC3_PHYIDX 0
308 #define CONFIG_ETHPRIME "eTSEC1"
310 #define CONFIG_PHY_GIGE
311 #define CONFIG_PHYLIB
312 #define CONFIG_PHY_ATHEROS
314 #define CONFIG_HAS_ETH0
315 #define CONFIG_HAS_ETH1
316 #define CONFIG_HAS_ETH2
320 #define CONFIG_PCI /* Enable PCI/PCIE */
321 #define CONFIG_PCIE1 /* PCIE controler 1 */
322 #define CONFIG_PCIE2 /* PCIE controler 2 */
323 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
324 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
326 #define CONFIG_SYS_PCI_64BIT
328 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
329 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
330 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
331 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
333 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
334 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
335 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
337 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
338 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
339 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
342 #define CONFIG_PCI_PNP
344 #define CONFIG_PCI_SCAN_SHOW
345 #define CONFIG_CMD_PCI
348 #define CONFIG_CMD_PING
349 #define CONFIG_CMD_DHCP
350 #define CONFIG_CMD_MII
352 #define CONFIG_CMDLINE_TAG
353 #define CONFIG_CMDLINE_EDITING
355 #define CONFIG_ARMV7_NONSEC
356 #define CONFIG_ARMV7_VIRT
357 #define CONFIG_PEN_ADDR_BIG_ENDIAN
358 #define CONFIG_LS102XA_NS_ACCESS
359 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
360 #define CONFIG_TIMER_CLK_FREQ 12500000
361 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
363 #define CONFIG_HWCONFIG
364 #define HWCONFIG_BUFFER_SIZE 128
366 #define CONFIG_BOOTDELAY 3
369 #define CONFIG_EXTRA_ENV_SETTINGS \
370 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
371 "initrd_high=0xcfffffff\0" \
372 "fdt_high=0xcfffffff\0"
374 #define CONFIG_EXTRA_ENV_SETTINGS \
375 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
376 "initrd_high=0xcfffffff\0" \
377 "fdt_high=0xcfffffff\0"
381 * Miscellaneous configurable options
383 #define CONFIG_SYS_LONGHELP /* undef to save memory */
384 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
385 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
386 #define CONFIG_AUTO_COMPLETE
387 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
388 #define CONFIG_SYS_PBSIZE \
389 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
390 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
391 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
393 #define CONFIG_CMD_GREPENV
394 #define CONFIG_CMD_MEMINFO
395 #define CONFIG_CMD_MEMTEST
396 #define CONFIG_SYS_MEMTEST_START 0x80000000
397 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
399 #define CONFIG_SYS_LOAD_ADDR 0x82000000
401 #define CONFIG_LS102XA_STREAM_ID
405 * The stack sizes are set up in start.S using the settings below
407 #define CONFIG_STACKSIZE (30 * 1024)
409 #define CONFIG_SYS_INIT_SP_OFFSET \
410 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
411 #define CONFIG_SYS_INIT_SP_ADDR \
412 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
414 #ifdef CONFIG_SPL_BUILD
415 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
417 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
420 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
425 #define CONFIG_ENV_OVERWRITE
427 #if defined(CONFIG_SD_BOOT)
428 #define CONFIG_ENV_OFFSET 0x100000
429 #define CONFIG_ENV_IS_IN_MMC
430 #define CONFIG_SYS_MMC_ENV_DEV 0
431 #define CONFIG_ENV_SIZE 0x20000
432 #elif defined(CONFIG_QSPI_BOOT)
433 #define CONFIG_ENV_IS_IN_SPI_FLASH
434 #define CONFIG_ENV_SIZE 0x2000
435 #define CONFIG_ENV_OFFSET 0x100000
436 #define CONFIG_ENV_SECT_SIZE 0x10000
438 #define CONFIG_ENV_IS_IN_FLASH
439 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
440 #define CONFIG_ENV_SIZE 0x20000
441 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
444 #define CONFIG_OF_LIBFDT
445 #define CONFIG_OF_BOARD_SETUP
446 #define CONFIG_CMD_BOOTZ
448 #define CONFIG_MISC_INIT_R
450 /* Hash command with SHA acceleration supported in hardware */
451 #define CONFIG_CMD_HASH
452 #define CONFIG_SHA_HW_ACCEL
454 #ifdef CONFIG_SECURE_BOOT
455 #define CONFIG_CMD_BLOB