2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #include "ls2085a_common.h"
11 #include <config_cmd_default.h>
13 #define CONFIG_IDENT_STRING " LS2085A-RDB"
14 #define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-RDB"
16 #undef CONFIG_CONS_INDEX
17 #define CONFIG_CONS_INDEX 2
19 #define CONFIG_DISPLAY_BOARDINFO
22 unsigned long get_board_sys_clk(void);
25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
26 #define CONFIG_DDR_CLK_FREQ 133333333
27 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
29 #define CONFIG_DDR_SPD
30 #define CONFIG_DDR_ECC
31 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
32 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
33 #define SPD_EEPROM_ADDRESS1 0x51
34 #define SPD_EEPROM_ADDRESS2 0x52
35 #define SPD_EEPROM_ADDRESS3 0x54
36 #define SPD_EEPROM_ADDRESS4 0x53 /* Board error */
37 #define SPD_EEPROM_ADDRESS5 0x55
38 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
39 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
40 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
41 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
42 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
43 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
44 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
46 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
48 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
49 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
50 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
52 #define CONFIG_SYS_NOR0_CSPR \
53 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
57 #define CONFIG_SYS_NOR0_CSPR_EARLY \
58 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
62 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
63 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
64 FTIM0_NOR_TEADC(0x5) | \
66 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
67 FTIM1_NOR_TRAD_NOR(0x1a) |\
68 FTIM1_NOR_TSEQRAD_NOR(0x13))
69 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
70 FTIM2_NOR_TCH(0x4) | \
71 FTIM2_NOR_TWPH(0x0E) | \
73 #define CONFIG_SYS_NOR_FTIM3 0x04000000
74 #define CONFIG_SYS_IFC_CCR 0x01000000
76 #ifndef CONFIG_SYS_NO_FLASH
77 #define CONFIG_FLASH_CFI_DRIVER
78 #define CONFIG_SYS_FLASH_CFI
79 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
80 #define CONFIG_SYS_FLASH_QUIET_TEST
81 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
83 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
84 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
85 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
86 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
88 #define CONFIG_SYS_FLASH_EMPTY_INFO
89 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
90 CONFIG_SYS_FLASH_BASE + 0x40000000}
93 #define CONFIG_NAND_FSL_IFC
94 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
95 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
98 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
99 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
100 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
101 | CSPR_MSEL_NAND /* MSEL = NAND */ \
103 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
105 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
106 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
107 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
108 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
109 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
110 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
111 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
113 #define CONFIG_SYS_NAND_ONFI_DETECTION
115 /* ONFI NAND Flash mode0 Timing Params */
116 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
117 FTIM0_NAND_TWP(0x30) | \
118 FTIM0_NAND_TWCHT(0x0e) | \
119 FTIM0_NAND_TWH(0x14))
120 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
121 FTIM1_NAND_TWBE(0xab) | \
122 FTIM1_NAND_TRR(0x1c) | \
123 FTIM1_NAND_TRP(0x30))
124 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
125 FTIM2_NAND_TREH(0x14) | \
126 FTIM2_NAND_TWHRE(0x3c))
127 #define CONFIG_SYS_NAND_FTIM3 0x0
129 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
130 #define CONFIG_SYS_MAX_NAND_DEVICE 1
131 #define CONFIG_MTD_NAND_VERIFY_WRITE
132 #define CONFIG_CMD_NAND
134 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
136 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
137 #define QIXIS_LBMAP_SWITCH 0x06
138 #define QIXIS_LBMAP_MASK 0x0f
139 #define QIXIS_LBMAP_SHIFT 0
140 #define QIXIS_LBMAP_DFLTBANK 0x00
141 #define QIXIS_LBMAP_ALTBANK 0x04
142 #define QIXIS_RST_CTL_RESET 0x31
143 #define QIXIS_RST_CTL_RESET_EN 0x30
144 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
145 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
146 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
147 #define QIXIS_RST_FORCE_MEM 0x01
149 #define CONFIG_SYS_CSPR3_EXT (0x0)
150 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
154 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
159 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
160 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
161 /* QIXIS Timing parameters for IFC CS3 */
162 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
163 FTIM0_GPCM_TEADC(0x0e) | \
164 FTIM0_GPCM_TEAHC(0x0e))
165 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
166 FTIM1_GPCM_TRAD(0x3f))
167 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
168 FTIM2_GPCM_TCH(0xf) | \
169 FTIM2_GPCM_TWP(0x3E))
170 #define CONFIG_SYS_CS3_FTIM3 0x0
172 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
173 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
174 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
175 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
176 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
177 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
178 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
179 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
180 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
181 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
182 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
183 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
184 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
185 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
186 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
187 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
188 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
190 /* Debug Server firmware */
191 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
192 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
195 #define CONFIG_SYS_LS_MC_FW_IN_NOR
196 #define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL
198 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
199 #define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL
201 #define CONFIG_SYS_LS_MC_DPC_IN_NOR
202 #define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL
204 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
209 #define I2C_MUX_PCA_ADDR 0x77
210 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
212 /* I2C bus multiplexer */
213 #define I2C_MUX_CH_DEFAULT 0x8
219 #define CONFIG_RTC_DS3231 1
220 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
223 #define CONFIG_ID_EEPROM
224 #define CONFIG_CMD_EEPROM
225 #define CONFIG_SYS_I2C_EEPROM_NXID
226 #define CONFIG_SYS_EEPROM_BUS_NUM 0
227 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
228 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
232 #define CONFIG_ENV_IS_IN_FLASH
233 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
234 #define CONFIG_ENV_SECT_SIZE 0x20000
235 #define CONFIG_ENV_SIZE 0x2000
237 #define CONFIG_FSL_MEMAC
238 #define CONFIG_PCI /* Enable PCIE */
239 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
242 #define CONFIG_NET_MULTI
243 #define CONFIG_PCI_PNP
245 #define CONFIG_PCI_SCAN_SHOW
246 #define CONFIG_CMD_PCI
247 #define CONFIG_CMD_NET
252 /* Initial environment variables */
253 #undef CONFIG_EXTRA_ENV_SETTINGS
254 #define CONFIG_EXTRA_ENV_SETTINGS \
255 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
256 "loadaddr=0x80100000\0" \
257 "kernel_addr=0x100000\0" \
258 "ramdisk_addr=0x800000\0" \
259 "ramdisk_size=0x2000000\0" \
260 "fdt_high=0xa0000000\0" \
261 "initrd_high=0xffffffffffffffff\0" \
262 "kernel_start=0x581100000\0" \
263 "kernel_load=0xa0000000\0" \
264 "kernel_size=0x1000000\0"
266 #endif /* __LS2_RDB_H */