2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
9 * Configuration settings for the Freescale i.MX31 PDK board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/imx-regs.h>
19 /* High Level Configuration Options */
21 #define CONFIG_SYS_GENERIC_BOARD
23 #define CONFIG_DISPLAY_CPUINFO
24 #define CONFIG_DISPLAY_BOARDINFO
26 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
27 #define CONFIG_SETUP_MEMORY_TAGS
28 #define CONFIG_INITRD_TAG
30 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
33 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
34 #define CONFIG_SPL_MAX_SIZE 2048
35 #define CONFIG_SPL_NAND_SUPPORT
36 #define CONFIG_SPL_LIBGENERIC_SUPPORT
38 #define CONFIG_SPL_TEXT_BASE 0x87dc0000
39 #define CONFIG_SYS_TEXT_BASE 0x87e00000
41 #ifndef CONFIG_SPL_BUILD
42 #define CONFIG_SKIP_LOWLEVEL_INIT
46 * Size of malloc() pool
48 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
54 #define CONFIG_MXC_UART
55 #define CONFIG_MXC_UART_BASE UART1_BASE
56 #define CONFIG_MXC_GPIO
58 #define CONFIG_HARD_SPI
59 #define CONFIG_MXC_SPI
60 #define CONFIG_DEFAULT_SPI_BUS 1
61 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
65 #define CONFIG_POWER_SPI
66 #define CONFIG_POWER_FSL
67 #define CONFIG_FSL_PMIC_BUS 1
68 #define CONFIG_FSL_PMIC_CS 2
69 #define CONFIG_FSL_PMIC_CLK 1000000
70 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
71 #define CONFIG_FSL_PMIC_BITLEN 32
72 #define CONFIG_RTC_MC13XXX
74 /* allow to overwrite serial and ethaddr */
75 #define CONFIG_ENV_OVERWRITE
76 #define CONFIG_CONS_INDEX 1
77 #define CONFIG_BAUDRATE 115200
79 /***********************************************************
81 ***********************************************************/
82 #define CONFIG_CMD_MII
83 #define CONFIG_CMD_PING
84 #define CONFIG_CMD_DHCP
85 #define CONFIG_CMD_SPI
86 #define CONFIG_CMD_DATE
87 #define CONFIG_CMD_NAND
88 #define CONFIG_CMD_BOOTZ
90 #define CONFIG_BOARD_LATE_INIT
92 #define CONFIG_BOOTDELAY 1
94 #define CONFIG_EXTRA_ENV_SETTINGS \
95 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
96 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
97 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
98 "bootcmd=run bootcmd_net\0" \
99 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
100 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
101 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
102 "nand erase 0x0 0x40000; " \
103 "nand write 0x81000000 0x0 0x40000\0"
105 #define CONFIG_SMC911X
106 #define CONFIG_SMC911X_BASE 0xB6000000
107 #define CONFIG_SMC911X_32_BIT
110 * Miscellaneous configurable options
112 #define CONFIG_SYS_LONGHELP /* undef to save memory */
113 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
114 /* max number of command args */
115 #define CONFIG_SYS_MAXARGS 16
116 /* Boot Argument Buffer Size */
117 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
119 /* memtest works on */
120 #define CONFIG_SYS_MEMTEST_START 0x80000000
121 #define CONFIG_SYS_MEMTEST_END 0x80010000
123 /* default load address */
124 #define CONFIG_SYS_LOAD_ADDR 0x81000000
126 #define CONFIG_CMDLINE_EDITING
128 /*-----------------------------------------------------------------------
129 * Physical Memory Map
131 #define CONFIG_NR_DRAM_BANKS 1
132 #define PHYS_SDRAM_1 CSD0_BASE
133 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
134 #define CONFIG_BOARD_EARLY_INIT_F
136 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
137 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
138 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
139 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
140 GENERATED_GBL_DATA_SIZE)
141 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
142 CONFIG_SYS_INIT_RAM_SIZE)
144 /*-----------------------------------------------------------------------
145 * FLASH and environment organization
147 /* No NOR flash present */
148 #define CONFIG_SYS_NO_FLASH
150 #define CONFIG_ENV_IS_IN_NAND
151 #define CONFIG_ENV_OFFSET 0x40000
152 #define CONFIG_ENV_OFFSET_REDUND 0x60000
153 #define CONFIG_ENV_SIZE (128 * 1024)
158 #define CONFIG_NAND_MXC
159 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
160 #define CONFIG_SYS_MAX_NAND_DEVICE 1
161 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
162 #define CONFIG_MXC_NAND_HWECC
163 #define CONFIG_SYS_NAND_LARGEPAGE
165 /* NAND configuration for the NAND_SPL */
167 /* Start copying real U-boot from the second page */
168 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
169 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
170 /* Load U-Boot to this address */
171 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
172 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
174 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
175 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
176 #define CONFIG_SYS_NAND_PAGE_COUNT 64
177 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
178 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
181 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
182 #define CCM_CCMR_SETUP 0x074B0BF5
183 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
184 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
185 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
186 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
187 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
190 #define ESDMISC_MDDR_SETUP 0x00000004
191 #define ESDMISC_MDDR_RESET_DL 0x0000000c
192 #define ESDCFG0_MDDR_SETUP 0x006ac73a
194 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
195 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
196 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
197 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
198 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
199 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
200 #define ESDCTL_RW ESDCTL_SETTINGS
202 #endif /* __CONFIG_H */