2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 * Configuration settings for the MX31ADS Freescale board.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/mx35.h>
29 /* High Level Configuration Options */
30 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
32 #define CONFIG_MX35 1 /* in a mx31 */
33 #define CONFIG_MX35_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
35 #define CONFIG_DISPLAY_CPUINFO
36 #define CONFIG_DISPLAY_BOARDINFO
38 #define CONFIG_SYS_64BIT_VSPRINTF
40 #define BOARD_LATE_INIT
42 * Disabled for now due to build problems under Debian and a significant increase
43 * in the final file size: 144260 vs. 109536 Bytes.
46 #define CONFIG_OF_LIBFDT 1
48 #define CONFIG_FIT_VERBOSE 1
51 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
52 #define CONFIG_REVISION_TAG 1
53 #define CONFIG_SETUP_MEMORY_TAGS 1
54 #define CONFIG_INITRD_TAG 1
57 * Size of malloc() pool
59 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
60 #define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for initial data */
65 #define CONFIG_HARD_I2C 1
66 #define CONFIG_I2C_MXC 1
67 #define CONFIG_SYS_I2C_PORT I2C_BASE_ADDR
68 #define CONFIG_SYS_I2C_SPEED 100000
69 #define CONFIG_SYS_I2C_SLAVE 0xfe
71 #define CONFIG_MX35_UART UART1_BASE_ADDR
73 /* allow to overwrite serial and ethaddr */
74 #define CONFIG_ENV_OVERWRITE
75 #define CONFIG_CONS_INDEX 1
76 #define CONFIG_BAUDRATE 115200
77 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
79 /***********************************************************
81 ***********************************************************/
83 #include <config_cmd_default.h>
85 #define CONFIG_CMD_PING
86 #define CONFIG_CMD_DHCP
87 #define CONFIG_BOOTP_SUBNETMASK
88 #define CONFIG_BOOTP_GATEWAY
89 #define CONFIG_BOOTP_DNS
90 /*#define CONFIG_CMD_SPI*/
91 /*#define CONFIG_CMD_DATE*/
92 #define CONFIG_CMD_NAND
93 #define CONFIG_MXC_NAND
95 #define CONFIG_CMD_I2C
96 #define CONFIG_CMD_MII
97 #define CONFIG_CMD_NET
98 #define CONFIG_NET_RETRY_COUNT 100
100 #define CONFIG_BOOTDELAY 3
102 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
104 #define CONFIG_EXTRA_ENV_SETTINGS \
106 "ethprime=smc911x\0" \
107 "uboot_addr=0xa0000000\0" \
108 "uboot=u-boot.bin\0" \
110 "nfsroot=/opt/eldk/arm\0" \
111 "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
112 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
113 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
114 "bootcmd=run bootcmd_net\0" \
115 "bootcmd_net=run bootargs_base bootargs_nfs; " \
116 "tftpboot ${loadaddr} ${kernel}; bootm\0" \
117 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
118 "protect off ${uboot_addr} 0xa003ffff; " \
119 "erase ${uboot_addr} 0xa003ffff; " \
120 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
121 "setenv filesize; saveenv\0"
124 #define CONFIG_SMC911X 1
125 #define CONFIG_SMC911X_16_BIT 1
126 #define CONFIG_SMC911X_BASE CS5_BASE_ADDR
128 #define CONFIG_HAS_ETH1
129 #define CONFIG_NET_MULTI 1
130 #define CONFIG_ETHPRIME
131 #define CONFIG_MXC_FEC
133 #define CONFIG_DISCOVER_PHY
135 #define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
136 #define CONFIG_FEC0_PINMUX -1
137 #define CONFIG_FEC0_PHY_ADDR 0x1F
138 #define CONFIG_FEC0_MIIBASE -1
141 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
142 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
143 * controller inverted. The controller is capable of detecting and correcting
144 * this, but it needs 4 network packets for that. Which means, at startup, you
145 * will not receive answers to the first 4 packest, unless there have been some
146 * broadcasts on the network, or your board is on a hub. Reducing the ARP
147 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
148 * transfer, should the user wish one, significantly.
150 #define CONFIG_ARP_TIMEOUT 200UL
153 * Miscellaneous configurable options
155 #define CONFIG_SYS_LONGHELP /* undef to save memory */
156 #define CONFIG_SYS_PROMPT "MX35 U-Boot > "
157 #define CONFIG_ARCH_CPU_INIT
158 #define CONFIG_ARCH_MMU
159 #define CONFIG_AUTO_COMPLETE
160 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
161 /* Print Buffer Size */
162 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
163 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
164 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
166 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
167 #define CONFIG_SYS_MEMTEST_END 0x10000
169 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
171 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
173 #define CONFIG_SYS_HZ 1000
175 #define CONFIG_CMDLINE_EDITING 1
177 /*-----------------------------------------------------------------------
180 * The stack sizes are set up in start.S using the settings below
182 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
184 /*-----------------------------------------------------------------------
185 * Physical Memory Map
187 #define CONFIG_NR_DRAM_BANKS 1
188 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
189 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
190 #define iomem_valid_addr(addr, size) \
191 (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
193 /*-----------------------------------------------------------------------
194 * FLASH and environment organization
196 #define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
197 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
198 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
199 /* Monitor at beginning of flash */
200 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
201 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256KiB */
203 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
204 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
206 /* Address and size of Redundant Environment Sector */
207 #define CONFIG_ENV_OFFSET_REDUND (2 * 1024 * 1024)
208 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
211 * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the
212 * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low
213 * 4 sectors, if we put environment next to it, we will have to occupy 128KiB
214 * for it. Putting it at the top of flash we use only 32KiB.
216 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
218 #if defined(CONFIG_CMD_NAND)
219 #define CONFIG_FSL_ENV_IN_NAND
221 #define CONFIG_ENV_IS_IN_FLASH 1
224 #if defined(CONFIG_FSL_ENV_IN_NAND)
225 #define CONFIG_ENV_IS_IN_NAND 1
226 #define CONFIG_ENV_OFFSET (1024 * 1024)
227 #elif defined(CONFIG_FSL_ENV_IS_IN_FLASH)
228 #define CONFIG_ENV_IS_IN_FLASH 1
231 /*-----------------------------------------------------------------------
232 * CFI FLASH driver setup
234 #define CONFIG_SYS_FLASH_CFI 1/* Flash memory is CFI compliant */
235 #define CONFIG_FLASH_CFI_DRIVER 1/* Use drivers/cfi_flash.c */
236 /* A non-standard buffered write algorithm */
237 #define CONFIG_FLASH_SPANSION_S29WS_N 1
238 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* Use buffered writes (~10x faster) */
239 #define CONFIG_SYS_FLASH_PROTECTION 1/* Use hardware sector protection */
241 /*-----------------------------------------------------------------------
242 * NAND FLASH driver setup
244 #define NAND_MAX_CHIPS 1
245 #define CONFIG_SYS_MAX_NAND_DEVICE 1
246 #define CONFIG_SYS_NAND_BASE 0x40000000
250 #undef CONFIG_JFFS2_CMDLINE
251 #define CONFIG_JFFS2_DEV "nor0"
253 #endif /* __CONFIG_H */