2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
6 * Configuration settings for the MX51-3Stack Freescale board.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/mx51.h>
29 /* High Level Configuration Options */
30 #define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
33 #define CONFIG_MX51_BBG 1 /* in a mx51 */
34 #define CONFIG_FLASH_HEADER 1
35 #define CONFIG_FLASH_HEADER_OFFSET 0x400
36 #define CONFIG_FLASH_HEADER_BARKER 0xB1
38 #define CONFIG_SKIP_RELOCATE_UBOOT
40 #define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
42 #define CONFIG_ARCH_CPU_INIT
43 #define CONFIG_ARCH_MMU
45 #define CONFIG_DISPLAY_CPUINFO
46 #define CONFIG_DISPLAY_BOARDINFO
48 #define CONFIG_SYS_64BIT_VSPRINTF
50 #define BOARD_LATE_INIT
52 * Disabled for now due to build problems under Debian and a significant
53 * increase in the final file size: 144260 vs. 109536 Bytes.
56 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
57 #define CONFIG_REVISION_TAG 1
58 #define CONFIG_SETUP_MEMORY_TAGS 1
59 #define CONFIG_INITRD_TAG 1
62 * Size of malloc() pool
64 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
65 /* size in bytes reserved for initial data */
66 #define CONFIG_SYS_GBL_DATA_SIZE 128
71 #define CONFIG_MX51_UART 1
72 #define CONFIG_MX51_UART1 1
74 /* allow to overwrite serial and ethaddr */
75 #define CONFIG_ENV_OVERWRITE
76 #define CONFIG_CONS_INDEX 1
77 #define CONFIG_BAUDRATE 115200
78 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
80 /***********************************************************
82 ***********************************************************/
84 #include <config_cmd_default.h>
86 #define CONFIG_CMD_PING
87 #define CONFIG_CMD_DHCP
88 #define CONFIG_BOOTP_SUBNETMASK
89 #define CONFIG_BOOTP_GATEWAY
90 #define CONFIG_BOOTP_DNS
91 #define CONFIG_CMD_MII
92 #define CONFIG_CMD_NET
93 #define CONFIG_NET_RETRY_COUNT 100
94 #define CONFIG_CMD_SPI
96 #define CONFIG_CMD_MMC
97 #define CONFIG_CMD_IIM
98 #define CONFIG_CMD_I2C
103 #ifdef CONFIG_CMD_IIM
104 #define CONFIG_IMX_IIM
105 #define IMX_IIM_BASE IIM_BASE_ADDR
106 #define CONFIG_IIM_MAC_BANK 1
107 #define CONFIG_IIM_MAC_ROW 9
114 #define CONFIG_FSL_SF 1
115 #define CONFIG_SPI_FLASH_IMX_ATMEL 1
116 #define CONFIG_SPI_FLASH_CS 1
117 #define CONFIG_IMX_ECSPI
118 #define IMX_CSPI_VER_2_3 1
119 #define CONFIG_IMX_SPI_PMIC
120 #define CONFIG_IMX_SPI_PMIC_CS 0
122 #define MAX_SPI_BYTES (64 * 4)
128 #ifdef CONFIG_CMD_MMC
130 #define CONFIG_GENERIC_MMC
131 #define CONFIG_IMX_MMC
132 #define CONFIG_SYS_FSL_ESDHC_NUM 2
133 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
134 #define CONFIG_SYS_MMC_ENV_DEV 0
135 #define CONFIG_DOS_PARTITION 1
136 #define CONFIG_CMD_FAT 1
137 #define CONFIG_DYNAMIC_MMC_DEVNO
143 #ifdef CONFIG_CMD_I2C
144 #define CONFIG_HARD_I2C 1
145 #define CONFIG_I2C_MXC 1
146 #define CONFIG_SYS_I2C_PORT I2C1_BASE_ADDR
147 #define CONFIG_SYS_I2C_SPEED 400000
148 #define CONFIG_SYS_I2C_SLAVE 0xfe
154 #define CONFIG_HAS_ETH1
155 #define CONFIG_NET_MULTI 1
156 #define CONFIG_MXC_FEC
158 #define CONFIG_DISCOVER_PHY
160 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
161 #define CONFIG_IIM_MAC_ADDR_OFFSET 0x24
163 #define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
164 #define CONFIG_FEC0_PINMUX -1
165 #define CONFIG_FEC0_PHY_ADDR 0x1F
166 #define CONFIG_FEC0_MIIBASE -1
170 /* Enable below configure when supporting nand */
171 #define CONFIG_CMD_ENV
173 #undef CONFIG_CMD_IMLS
175 #define CONFIG_BOOTDELAY 3
177 #define CONFIG_PRIME "FEC0"
179 #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
181 #define CONFIG_EXTRA_ENV_SETTINGS \
184 "uboot_addr=0xa0000000\0" \
185 "uboot=u-boot.bin\0" \
187 "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
188 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
189 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
190 "bootcmd=run bootcmd_net\0" \
191 "bootcmd_net=run bootargs_base bootargs_nfs; " \
192 "tftpboot ${loadaddr} ${kernel}; bootm\0" \
193 "load_uboot=tftpboot ${loadaddr} ${uboot}\0" \
196 * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
197 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
198 * controller inverted. The controller is capable of detecting and correcting
199 * this, but it needs 4 network packets for that. Which means, at startup, you
200 * will not receive answers to the first 4 packest, unless there have been some
201 * broadcasts on the network, or your board is on a hub. Reducing the ARP
202 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
203 * transfer, should the user wish one, significantly.
205 #define CONFIG_ARP_TIMEOUT 200UL
208 * Miscellaneous configurable options
210 #define CONFIG_SYS_LONGHELP /* undef to save memory */
211 #define CONFIG_SYS_PROMPT "BBG U-Boot > "
212 #define CONFIG_AUTO_COMPLETE
213 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
214 /* Print Buffer Size */
215 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
216 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
217 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
219 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
220 #define CONFIG_SYS_MEMTEST_END 0x10000
222 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
224 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
226 #define CONFIG_SYS_HZ 1000
228 #define CONFIG_CMDLINE_EDITING 1
230 /*-----------------------------------------------------------------------
233 * The stack sizes are set up in start.S using the settings below
235 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
237 /*-----------------------------------------------------------------------
238 * Physical Memory Map
240 #define CONFIG_NR_DRAM_BANKS 1
241 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
242 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
243 #define iomem_valid_addr(addr, size) \
244 (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
246 /*-----------------------------------------------------------------------
247 * FLASH and environment organization
249 #define CONFIG_SYS_NO_FLASH
251 /* Monitor at beginning of flash */
252 /* #define CONFIG_FSL_ENV_IN_SF */
253 #define CONFIG_FSL_ENV_IN_MMC
255 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
256 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
258 #if defined(CONFIG_FSL_ENV_IN_MMC)
259 #define CONFIG_ENV_IS_IN_MMC 1
260 #define CONFIG_ENV_OFFSET (768 * 1024)
261 #elif defined(CONFIG_FSL_ENV_IN_SF)
262 #define CONFIG_ENV_IS_IN_SPI_FLASH 1
263 #define CONFIG_ENV_SPI_CS 1
264 #define CONFIG_ENV_OFFSET (768 * 1024)
266 #define CONFIG_ENV_IS_NOWHERE 1
271 #undef CONFIG_JFFS2_CMDLINE
272 #define CONFIG_JFFS2_DEV "nand0"
274 #endif /* __CONFIG_H */