2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SX Sabresd board.
6 * SPDX-License-Identifier: GPL-2.0+
13 #include "mx6_common.h"
15 #define CONFIG_DISPLAY_CPUINFO
16 #define CONFIG_DISPLAY_BOARDINFO
19 #define CONFIG_SPL_LIBCOMMON_SUPPORT
20 #define CONFIG_SPL_MMC_SUPPORT
24 #define CONFIG_CMDLINE_TAG
25 #define CONFIG_SETUP_MEMORY_TAGS
26 #define CONFIG_INITRD_TAG
27 #define CONFIG_REVISION_TAG
28 #define CONFIG_SYS_GENERIC_BOARD
30 /* Size of malloc() pool */
31 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
33 #define CONFIG_BOARD_EARLY_INIT_F
34 #define CONFIG_MXC_GPIO
36 #define CONFIG_MXC_UART
37 #define CONFIG_MXC_UART_BASE UART1_BASE
39 /* allow to overwrite serial and ethaddr */
40 #define CONFIG_ENV_OVERWRITE
41 #define CONFIG_CONS_INDEX 1
42 #define CONFIG_BAUDRATE 115200
44 /* Command definition */
46 #define CONFIG_BOOTDELAY 3
48 #define CONFIG_LOADADDR 0x80800000
49 #define CONFIG_SYS_TEXT_BASE 0x87800000
51 #define CONFIG_EXTRA_ENV_SETTINGS \
55 "fdt_high=0xffffffff\0" \
56 "initrd_high=0xffffffff\0" \
57 "fdt_file=imx6sx-sdb.dtb\0" \
58 "fdt_addr=0x88000000\0" \
63 "mmcroot=/dev/mmcblk3p2 rootwait rw\0" \
64 "mmcargs=setenv bootargs console=${console},${baudrate} " \
67 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
68 "bootscript=echo Running bootscript from mmc ...; " \
70 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
71 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
72 "mmcboot=echo Booting from mmc ...; " \
74 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
75 "if run loadfdt; then " \
76 "bootz ${loadaddr} - ${fdt_addr}; " \
78 "if test ${boot_fdt} = try; then " \
81 "echo WARN: Cannot load the DT; " \
87 "netargs=setenv bootargs console=${console},${baudrate} " \
89 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
90 "netboot=echo Booting from net ...; " \
92 "if test ${ip_dyn} = yes; then " \
93 "setenv get_cmd dhcp; " \
95 "setenv get_cmd tftp; " \
97 "${get_cmd} ${image}; " \
98 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
99 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
100 "bootz ${loadaddr} - ${fdt_addr}; " \
102 "if test ${boot_fdt} = try; then " \
105 "echo WARN: Cannot load the DT; " \
112 #define CONFIG_BOOTCOMMAND \
113 "mmc dev ${mmcdev};" \
114 "mmc dev ${mmcdev}; if mmc rescan; then " \
115 "if run loadbootscript; then " \
118 "if run loadimage; then " \
120 "else run netboot; " \
123 "else run netboot; fi"
125 /* Miscellaneous configurable options */
126 #define CONFIG_SYS_LONGHELP
127 #define CONFIG_SYS_HUSH_PARSER
128 #define CONFIG_AUTO_COMPLETE
129 #define CONFIG_SYS_CBSIZE 1024
131 #define CONFIG_SYS_MAXARGS 256
132 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
134 #define CONFIG_SYS_MEMTEST_START 0x80000000
135 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
137 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
139 #define CONFIG_CMDLINE_EDITING
140 #define CONFIG_STACKSIZE SZ_128K
142 /* Physical Memory Map */
143 #define CONFIG_NR_DRAM_BANKS 1
144 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
145 #define PHYS_SDRAM_SIZE SZ_1G
147 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
148 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
149 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
151 #define CONFIG_SYS_INIT_SP_OFFSET \
152 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
153 #define CONFIG_SYS_INIT_SP_ADDR \
154 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
156 /* MMC Configuration */
157 #define CONFIG_FSL_ESDHC
158 #define CONFIG_FSL_USDHC
159 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
162 #define CONFIG_CMD_MMC
163 #define CONFIG_GENERIC_MMC
164 #define CONFIG_BOUNCE_BUFFER
165 #define CONFIG_CMD_EXT2
166 #define CONFIG_CMD_FAT
167 #define CONFIG_DOS_PARTITION
170 #define CONFIG_CMD_I2C
171 #define CONFIG_SYS_I2C
172 #define CONFIG_SYS_I2C_MXC
173 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
174 #define CONFIG_SYS_I2C_SPEED 100000
178 #define CONFIG_POWER_I2C
179 #define CONFIG_POWER_PFUZE100
180 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
183 #define CONFIG_CMD_PING
184 #define CONFIG_CMD_DHCP
185 #define CONFIG_CMD_MII
186 #define CONFIG_CMD_NET
187 #define CONFIG_FEC_MXC
190 #define IMX_FEC_BASE ENET_BASE_ADDR
191 #define CONFIG_FEC_MXC_PHYADDR 0x1
193 #define CONFIG_FEC_XCV_TYPE RGMII
194 #define CONFIG_ETHPRIME "FEC"
196 #define CONFIG_PHYLIB
197 #define CONFIG_PHY_ATHEROS
200 #define CONFIG_CMD_USB
201 #ifdef CONFIG_CMD_USB
202 #define CONFIG_USB_EHCI
203 #define CONFIG_USB_EHCI_MX6
204 #define CONFIG_USB_STORAGE
205 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
206 #define CONFIG_USB_HOST_ETHER
207 #define CONFIG_USB_ETHER_ASIX
208 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
209 #define CONFIG_MXC_USB_FLAGS 0
210 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
213 #define CONFIG_CMD_PCI
214 #ifdef CONFIG_CMD_PCI
216 #define CONFIG_PCI_PNP
217 #define CONFIG_PCI_SCAN_SHOW
218 #define CONFIG_PCIE_IMX
219 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
220 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
223 #define CONFIG_IMX6_THERMAL
225 #define CONFIG_CMD_FUSE
226 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
227 #define CONFIG_MXC_OCOTP
230 #define CONFIG_CMD_TIME
232 #define CONFIG_FSL_QSPI
234 #ifdef CONFIG_FSL_QSPI
235 #define CONFIG_CMD_SF
236 #define CONFIG_SPI_FLASH
237 #define CONFIG_SPI_FLASH_BAR
238 #define CONFIG_SPI_FLASH_SPANSION
239 #define CONFIG_SPI_FLASH_STMICRO
240 #define CONFIG_SYS_FSL_QSPI_LE
241 #define CONFIG_SYS_FSL_QSPI_AHB
242 #ifdef CONFIG_MX6SX_SABRESD_REVA
243 #define FSL_QSPI_FLASH_SIZE SZ_16M
245 #define FSL_QSPI_FLASH_SIZE SZ_32M
247 #define FSL_QSPI_FLASH_NUM 2
250 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
251 #define CONFIG_ENV_SIZE SZ_8K
252 #define CONFIG_ENV_IS_IN_MMC
254 #define CONFIG_OF_LIBFDT
255 #define CONFIG_CMD_BOOTZ
257 #ifndef CONFIG_SYS_DCACHE_OFF
258 #define CONFIG_CMD_CACHE
261 #define CONFIG_SYS_FSL_USDHC_NUM 3
262 #if defined(CONFIG_ENV_IS_IN_MMC)
263 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
266 #endif /* __CONFIG_H */