2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SX Sabresd board.
6 * SPDX-License-Identifier: GPL-2.0+
13 #include "mx6_common.h"
16 #define CONFIG_SPL_LIBCOMMON_SUPPORT
17 #define CONFIG_SPL_MMC_SUPPORT
21 /* Size of malloc() pool */
22 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
24 #define CONFIG_BOARD_EARLY_INIT_F
25 #define CONFIG_MXC_GPIO
27 #define CONFIG_MXC_UART
28 #define CONFIG_MXC_UART_BASE UART1_BASE
30 /* allow to overwrite serial and ethaddr */
31 #define CONFIG_ENV_OVERWRITE
32 #define CONFIG_CONS_INDEX 1
33 #define CONFIG_BAUDRATE 115200
35 /* Command definition */
37 #define CONFIG_BOOTDELAY 3
39 #define CONFIG_LOADADDR 0x80800000
40 #define CONFIG_SYS_TEXT_BASE 0x87800000
42 #define CONFIG_EXTRA_ENV_SETTINGS \
46 "fdt_high=0xffffffff\0" \
47 "initrd_high=0xffffffff\0" \
48 "fdt_file=imx6sx-sdb.dtb\0" \
49 "fdt_addr=0x88000000\0" \
54 "mmcroot=/dev/mmcblk3p2 rootwait rw\0" \
55 "mmcargs=setenv bootargs console=${console},${baudrate} " \
58 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
59 "bootscript=echo Running bootscript from mmc ...; " \
61 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
62 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
63 "mmcboot=echo Booting from mmc ...; " \
65 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
66 "if run loadfdt; then " \
67 "bootz ${loadaddr} - ${fdt_addr}; " \
69 "if test ${boot_fdt} = try; then " \
72 "echo WARN: Cannot load the DT; " \
78 "netargs=setenv bootargs console=${console},${baudrate} " \
80 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
81 "netboot=echo Booting from net ...; " \
83 "if test ${ip_dyn} = yes; then " \
84 "setenv get_cmd dhcp; " \
86 "setenv get_cmd tftp; " \
88 "${get_cmd} ${image}; " \
89 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
90 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
91 "bootz ${loadaddr} - ${fdt_addr}; " \
93 "if test ${boot_fdt} = try; then " \
96 "echo WARN: Cannot load the DT; " \
103 #define CONFIG_BOOTCOMMAND \
104 "mmc dev ${mmcdev};" \
105 "mmc dev ${mmcdev}; if mmc rescan; then " \
106 "if run loadbootscript; then " \
109 "if run loadimage; then " \
111 "else run netboot; " \
114 "else run netboot; fi"
116 /* Miscellaneous configurable options */
117 #define CONFIG_SYS_LONGHELP
118 #define CONFIG_SYS_HUSH_PARSER
119 #define CONFIG_AUTO_COMPLETE
120 #define CONFIG_SYS_CBSIZE 1024
122 #define CONFIG_SYS_MAXARGS 256
123 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
125 #define CONFIG_SYS_MEMTEST_START 0x80000000
126 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
128 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
130 #define CONFIG_CMDLINE_EDITING
131 #define CONFIG_STACKSIZE SZ_128K
133 /* Physical Memory Map */
134 #define CONFIG_NR_DRAM_BANKS 1
135 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
136 #define PHYS_SDRAM_SIZE SZ_1G
138 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
139 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
140 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
142 #define CONFIG_SYS_INIT_SP_OFFSET \
143 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
144 #define CONFIG_SYS_INIT_SP_ADDR \
145 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
147 /* MMC Configuration */
148 #define CONFIG_FSL_ESDHC
149 #define CONFIG_FSL_USDHC
150 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
153 #define CONFIG_CMD_MMC
154 #define CONFIG_GENERIC_MMC
155 #define CONFIG_BOUNCE_BUFFER
156 #define CONFIG_CMD_EXT2
157 #define CONFIG_CMD_FAT
158 #define CONFIG_DOS_PARTITION
161 #define CONFIG_CMD_I2C
162 #define CONFIG_SYS_I2C
163 #define CONFIG_SYS_I2C_MXC
164 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
165 #define CONFIG_SYS_I2C_SPEED 100000
169 #define CONFIG_POWER_I2C
170 #define CONFIG_POWER_PFUZE100
171 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
174 #define CONFIG_CMD_PING
175 #define CONFIG_CMD_DHCP
176 #define CONFIG_CMD_MII
177 #define CONFIG_CMD_NET
178 #define CONFIG_FEC_MXC
181 #define IMX_FEC_BASE ENET_BASE_ADDR
182 #define CONFIG_FEC_MXC_PHYADDR 0x1
184 #define CONFIG_FEC_XCV_TYPE RGMII
185 #define CONFIG_ETHPRIME "FEC"
187 #define CONFIG_PHYLIB
188 #define CONFIG_PHY_ATHEROS
191 #define CONFIG_CMD_USB
192 #ifdef CONFIG_CMD_USB
193 #define CONFIG_USB_EHCI
194 #define CONFIG_USB_EHCI_MX6
195 #define CONFIG_USB_STORAGE
196 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
197 #define CONFIG_USB_HOST_ETHER
198 #define CONFIG_USB_ETHER_ASIX
199 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
200 #define CONFIG_MXC_USB_FLAGS 0
201 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
204 #define CONFIG_CMD_PCI
205 #ifdef CONFIG_CMD_PCI
207 #define CONFIG_PCI_PNP
208 #define CONFIG_PCI_SCAN_SHOW
209 #define CONFIG_PCIE_IMX
210 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
211 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
214 #define CONFIG_IMX6_THERMAL
216 #define CONFIG_CMD_FUSE
217 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
218 #define CONFIG_MXC_OCOTP
221 #define CONFIG_CMD_TIME
223 #define CONFIG_FSL_QSPI
225 #ifdef CONFIG_FSL_QSPI
226 #define CONFIG_CMD_SF
227 #define CONFIG_SPI_FLASH
228 #define CONFIG_SPI_FLASH_BAR
229 #define CONFIG_SPI_FLASH_SPANSION
230 #define CONFIG_SPI_FLASH_STMICRO
231 #define CONFIG_SYS_FSL_QSPI_LE
232 #define CONFIG_SYS_FSL_QSPI_AHB
233 #ifdef CONFIG_MX6SX_SABRESD_REVA
234 #define FSL_QSPI_FLASH_SIZE SZ_16M
236 #define FSL_QSPI_FLASH_SIZE SZ_32M
238 #define FSL_QSPI_FLASH_NUM 2
241 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
242 #define CONFIG_ENV_SIZE SZ_8K
243 #define CONFIG_ENV_IS_IN_MMC
245 #define CONFIG_OF_LIBFDT
246 #define CONFIG_CMD_BOOTZ
248 #ifndef CONFIG_SYS_DCACHE_OFF
249 #define CONFIG_CMD_CACHE
252 #define CONFIG_SYS_FSL_USDHC_NUM 3
253 #if defined(CONFIG_ENV_IS_IN_MMC)
254 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
257 #endif /* __CONFIG_H */