2 * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
4 * Configuration settings for the Dave/DENX QongEVB-LITE board.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
14 /* High Level Configuration Options */
17 #define CONFIG_DISPLAY_CPUINFO
18 #define CONFIG_DISPLAY_BOARDINFO
20 #define CONFIG_SYS_TEXT_BASE 0xa0000000
22 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23 #define CONFIG_SETUP_MEMORY_TAGS
24 #define CONFIG_INITRD_TAG
27 * Size of malloc() pool
29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
35 #define CONFIG_MXC_UART
36 #define CONFIG_MXC_UART_BASE UART1_BASE
38 #define CONFIG_MXC_GPIO
39 #define CONFIG_HW_WATCHDOG
40 #define CONFIG_IMX_WATCHDOG
42 #define CONFIG_MXC_SPI
43 #define CONFIG_DEFAULT_SPI_BUS 1
44 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
45 #define CONFIG_RTC_MC13XXX
48 #define CONFIG_POWER_SPI
49 #define CONFIG_POWER_FSL
50 #define CONFIG_FSL_PMIC_BUS 1
51 #define CONFIG_FSL_PMIC_CS 0
52 #define CONFIG_FSL_PMIC_CLK 100000
53 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
54 #define CONFIG_FSL_PMIC_BITLEN 32
58 #define CONFIG_QONG_FPGA
59 #define CONFIG_FPGA_BASE (CS1_BASE)
60 #define CONFIG_FPGA_LATTICE
61 #define CONFIG_FPGA_COUNT 1
63 #ifdef CONFIG_QONG_FPGA
66 #define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
68 /* Framebuffer and LCD */
70 #define CONFIG_CFB_CONSOLE
71 #define CONFIG_VIDEO_MX3
72 #define CONFIG_VIDEO_LOGO
73 #define CONFIG_VIDEO_SW_CURSOR
74 #define CONFIG_VGA_AS_SINGLE_DEVICE
75 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
76 #define CONFIG_SPLASH_SCREEN
77 #define CONFIG_CMD_BMP
78 #define CONFIG_BMP_16BPP
79 #define CONFIG_VIDEO_BMP_GZIP
80 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
83 #define CONFIG_CMD_USB
85 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
86 #define CONFIG_USB_EHCI_MXC
87 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
88 #define CONFIG_MXC_USB_PORT 2
89 #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
90 #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
91 #define CONFIG_EHCI_IS_TDI
92 #define CONFIG_USB_STORAGE
93 #define CONFIG_DOS_PARTITION
94 #define CONFIG_SUPPORT_VFAT
95 #define CONFIG_CMD_EXT2
96 #define CONFIG_CMD_FAT
97 #endif /* CONFIG_CMD_USB */
100 * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
101 * initial TFTP transfer, should the user wish one, significantly.
103 #define CONFIG_ARP_TIMEOUT 200UL
105 #endif /* CONFIG_QONG_FPGA */
107 #define CONFIG_CONS_INDEX 1
108 #define CONFIG_BAUDRATE 115200
110 /***********************************************************
112 ***********************************************************/
113 #define CONFIG_CMD_CACHE
114 #define CONFIG_CMD_DATE
115 #define CONFIG_CMD_DHCP
116 #define CONFIG_CMD_MII
117 #define CONFIG_CMD_NAND
118 #define CONFIG_CMD_PING
119 #define CONFIG_CMD_SPI
120 #define CONFIG_CMD_UNZIP
122 #define CONFIG_BOARD_LATE_INIT
124 #define CONFIG_BOOTDELAY 5
126 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
128 #define CONFIG_EXTRA_ENV_SETTINGS \
130 "nfsargs=setenv bootargs root=/dev/nfs rw " \
131 "nfsroot=${serverip}:${rootpath}\0" \
132 "ramargs=setenv bootargs root=/dev/ram rw\0" \
133 "addip=setenv bootargs ${bootargs} " \
134 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
135 ":${hostname}:${netdev}:off panic=1\0" \
136 "addtty=setenv bootargs ${bootargs}" \
137 " console=ttymxc0,${baudrate}\0" \
138 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
139 "addmisc=setenv bootargs ${bootargs}\0" \
140 "uboot_addr=A0000000\0" \
141 "kernel_addr=A00C0000\0" \
142 "ramdisk_addr=A0300000\0" \
143 "u-boot=qong/u-boot.bin\0" \
144 "kernel_addr_r=80800000\0" \
146 "bootfile=qong/uImage\0" \
147 "rootpath=/opt/eldk-4.2-arm/armVFP\0" \
148 "flash_self=run ramargs addip addtty addmtd addmisc;" \
149 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
150 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
151 "bootm ${kernel_addr}\0" \
152 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
153 "run nfsargs addip addtty addmtd addmisc;" \
155 "bootcmd=run flash_self\0" \
156 "load=tftp ${loadaddr} ${u-boot}\0" \
157 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
158 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
159 " +${filesize};cp.b ${fileaddr} " \
160 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
161 "upd=run load update\0" \
162 "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
163 "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
167 * Miscellaneous configurable options
169 #define CONFIG_SYS_LONGHELP /* undef to save memory */
170 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
171 /* Print Buffer Size */
172 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
173 sizeof(CONFIG_SYS_PROMPT) + 16)
174 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
175 /* Boot Argument Buffer Size */
176 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
178 /* memtest works on first 255MB of RAM */
179 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
180 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
182 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
184 #define CONFIG_CMDLINE_EDITING
185 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
187 #define CONFIG_MISC_INIT_R
189 /*-----------------------------------------------------------------------
190 * Physical Memory Map
192 #define CONFIG_NR_DRAM_BANKS 1
193 #define PHYS_SDRAM_1 CSD0_BASE
194 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
201 extern void qong_nand_plat_init(void *chip);
202 extern int qong_nand_rdy(void *chip);
204 #define CONFIG_NAND_PLAT
205 #define CONFIG_SYS_MAX_NAND_DEVICE 1
206 #define CONFIG_SYS_NAND_BASE CS3_BASE
207 #define NAND_PLAT_INIT() qong_nand_plat_init(nand)
209 #define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
210 #define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
211 #define QONG_NAND_WRITE(addr, cmd) \
213 __REG8(addr) = cmd; \
216 #define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
217 #define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
218 #define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
220 /*-----------------------------------------------------------------------
221 * FLASH and environment organization
223 #define CONFIG_SYS_FLASH_BASE CS0_BASE
224 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
225 /* max number of sectors on one chip */
226 #define CONFIG_SYS_MAX_FLASH_SECT 1024
227 /* Monitor at beginning of flash */
228 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
229 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
231 #define CONFIG_ENV_IS_IN_FLASH
232 #define CONFIG_ENV_SECT_SIZE 0x20000
233 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
234 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
236 /* Address and size of Redundant Environment Sector */
237 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
238 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
240 /*-----------------------------------------------------------------------
241 * CFI FLASH driver setup
243 /* Flash memory is CFI compliant */
244 #define CONFIG_SYS_FLASH_CFI
245 /* Use drivers/cfi_flash.c */
246 #define CONFIG_FLASH_CFI_DRIVER
247 /* Use buffered writes (~10x faster) */
248 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
249 /* Use hardware sector protection */
250 #define CONFIG_SYS_FLASH_PROTECTION
255 #define CONFIG_CMD_JFFS2
256 #define CONFIG_CMD_UBI
257 #define CONFIG_CMD_UBIFS
258 #define CONFIG_RBTREE
259 #define CONFIG_MTD_PARTITIONS
260 #define CONFIG_CMD_MTDPARTS
262 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
263 #define CONFIG_FLASH_CFI_MTD
264 #define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
266 #define MTDPARTS_DEFAULT \
267 "mtdparts=physmap-flash.0:" \
268 "512k(U-Boot),128k(env1),128k(env2)," \
269 "2304k(kernel),13m(ramdisk),-(user);" \
273 /* additions for new relocation code, must be added to all boards */
274 #define CONFIG_SYS_SDRAM_BASE 0x80000000
275 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
276 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
277 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
278 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
280 #define CONFIG_BOARD_EARLY_INIT_F
282 #endif /* __CONFIG_H */