2 * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
4 * Configuration settings for the Dave/DENX QongEVB-LITE board.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
14 /* High Level Configuration Options */
17 #define CONFIG_DISPLAY_CPUINFO
18 #define CONFIG_DISPLAY_BOARDINFO
20 #define CONFIG_SYS_TEXT_BASE 0xa0000000
22 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23 #define CONFIG_SETUP_MEMORY_TAGS
24 #define CONFIG_INITRD_TAG
27 * Size of malloc() pool
29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
35 #define CONFIG_MXC_UART
36 #define CONFIG_MXC_UART_BASE UART1_BASE
38 #define CONFIG_MXC_GPIO
39 #define CONFIG_HW_WATCHDOG
40 #define CONFIG_IMX_WATCHDOG
42 #define CONFIG_MXC_SPI
43 #define CONFIG_DEFAULT_SPI_BUS 1
44 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
45 #define CONFIG_RTC_MC13XXX
48 #define CONFIG_POWER_SPI
49 #define CONFIG_POWER_FSL
50 #define CONFIG_FSL_PMIC_BUS 1
51 #define CONFIG_FSL_PMIC_CS 0
52 #define CONFIG_FSL_PMIC_CLK 100000
53 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
54 #define CONFIG_FSL_PMIC_BITLEN 32
58 #define CONFIG_QONG_FPGA
59 #define CONFIG_FPGA_BASE (CS1_BASE)
60 #define CONFIG_FPGA_LATTICE
61 #define CONFIG_FPGA_COUNT 1
63 #ifdef CONFIG_QONG_FPGA
66 #define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
68 /* Framebuffer and LCD */
70 #define CONFIG_CFB_CONSOLE
71 #define CONFIG_VIDEO_MX3
72 #define CONFIG_VIDEO_LOGO
73 #define CONFIG_VIDEO_SW_CURSOR
74 #define CONFIG_VGA_AS_SINGLE_DEVICE
75 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
76 #define CONFIG_SPLASH_SCREEN
77 #define CONFIG_CMD_BMP
78 #define CONFIG_BMP_16BPP
79 #define CONFIG_VIDEO_BMP_GZIP
80 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
83 #define CONFIG_CMD_USB
85 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
86 #define CONFIG_USB_EHCI_MXC
87 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
88 #define CONFIG_MXC_USB_PORT 2
89 #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
90 #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
91 #define CONFIG_EHCI_IS_TDI
92 #define CONFIG_USB_STORAGE
93 #define CONFIG_DOS_PARTITION
94 #define CONFIG_SUPPORT_VFAT
95 #define CONFIG_CMD_EXT2
96 #define CONFIG_CMD_FAT
97 #endif /* CONFIG_CMD_USB */
100 * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
101 * initial TFTP transfer, should the user wish one, significantly.
103 #define CONFIG_ARP_TIMEOUT 200UL
105 #endif /* CONFIG_QONG_FPGA */
107 #define CONFIG_CONS_INDEX 1
108 #define CONFIG_BAUDRATE 115200
110 /***********************************************************
112 ***********************************************************/
114 #include <config_cmd_default.h>
116 #define CONFIG_CMD_CACHE
117 #define CONFIG_CMD_DATE
118 #define CONFIG_CMD_DHCP
119 #define CONFIG_CMD_MII
120 #define CONFIG_CMD_NAND
121 #define CONFIG_CMD_NET
122 #define CONFIG_CMD_PING
123 #define CONFIG_CMD_SETEXPR
124 #define CONFIG_CMD_SPI
125 #define CONFIG_CMD_UNZIP
127 #define CONFIG_BOARD_LATE_INIT
129 #define CONFIG_BOOTDELAY 5
131 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
133 #define CONFIG_EXTRA_ENV_SETTINGS \
135 "nfsargs=setenv bootargs root=/dev/nfs rw " \
136 "nfsroot=${serverip}:${rootpath}\0" \
137 "ramargs=setenv bootargs root=/dev/ram rw\0" \
138 "addip=setenv bootargs ${bootargs} " \
139 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
140 ":${hostname}:${netdev}:off panic=1\0" \
141 "addtty=setenv bootargs ${bootargs}" \
142 " console=ttymxc0,${baudrate}\0" \
143 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
144 "addmisc=setenv bootargs ${bootargs}\0" \
145 "uboot_addr=A0000000\0" \
146 "kernel_addr=A00C0000\0" \
147 "ramdisk_addr=A0300000\0" \
148 "u-boot=qong/u-boot.bin\0" \
149 "kernel_addr_r=80800000\0" \
151 "bootfile=qong/uImage\0" \
152 "rootpath=/opt/eldk-4.2-arm/armVFP\0" \
153 "flash_self=run ramargs addip addtty addmtd addmisc;" \
154 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
155 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
156 "bootm ${kernel_addr}\0" \
157 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
158 "run nfsargs addip addtty addmtd addmisc;" \
160 "bootcmd=run flash_self\0" \
161 "load=tftp ${loadaddr} ${u-boot}\0" \
162 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
163 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
164 " +${filesize};cp.b ${fileaddr} " \
165 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
166 "upd=run load update\0" \
167 "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
168 "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
172 * Miscellaneous configurable options
174 #define CONFIG_SYS_LONGHELP /* undef to save memory */
175 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
176 /* Print Buffer Size */
177 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
178 sizeof(CONFIG_SYS_PROMPT) + 16)
179 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
180 /* Boot Argument Buffer Size */
181 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
183 /* memtest works on first 255MB of RAM */
184 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
185 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
187 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
189 #define CONFIG_CMDLINE_EDITING
190 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
192 #define CONFIG_MISC_INIT_R
194 /*-----------------------------------------------------------------------
195 * Physical Memory Map
197 #define CONFIG_NR_DRAM_BANKS 1
198 #define PHYS_SDRAM_1 CSD0_BASE
199 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
206 extern void qong_nand_plat_init(void *chip);
207 extern int qong_nand_rdy(void *chip);
209 #define CONFIG_NAND_PLAT
210 #define CONFIG_SYS_MAX_NAND_DEVICE 1
211 #define CONFIG_SYS_NAND_BASE CS3_BASE
212 #define NAND_PLAT_INIT() qong_nand_plat_init(nand)
214 #define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
215 #define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
216 #define QONG_NAND_WRITE(addr, cmd) \
218 __REG8(addr) = cmd; \
221 #define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
222 #define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
223 #define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
225 /*-----------------------------------------------------------------------
226 * FLASH and environment organization
228 #define CONFIG_SYS_FLASH_BASE CS0_BASE
229 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
230 /* max number of sectors on one chip */
231 #define CONFIG_SYS_MAX_FLASH_SECT 1024
232 /* Monitor at beginning of flash */
233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
234 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
236 #define CONFIG_ENV_IS_IN_FLASH
237 #define CONFIG_ENV_SECT_SIZE 0x20000
238 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
239 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
241 /* Address and size of Redundant Environment Sector */
242 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
243 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
245 /*-----------------------------------------------------------------------
246 * CFI FLASH driver setup
248 /* Flash memory is CFI compliant */
249 #define CONFIG_SYS_FLASH_CFI
250 /* Use drivers/cfi_flash.c */
251 #define CONFIG_FLASH_CFI_DRIVER
252 /* Use buffered writes (~10x faster) */
253 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
254 /* Use hardware sector protection */
255 #define CONFIG_SYS_FLASH_PROTECTION
260 #define CONFIG_CMD_JFFS2
261 #define CONFIG_CMD_UBI
262 #define CONFIG_CMD_UBIFS
263 #define CONFIG_RBTREE
264 #define CONFIG_MTD_PARTITIONS
265 #define CONFIG_CMD_MTDPARTS
267 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
268 #define CONFIG_FLASH_CFI_MTD
269 #define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
271 #define MTDPARTS_DEFAULT \
272 "mtdparts=physmap-flash.0:" \
273 "512k(U-Boot),128k(env1),128k(env2)," \
274 "2304k(kernel),13m(ramdisk),-(user);" \
278 /* additions for new relocation code, must be added to all boards */
279 #define CONFIG_SYS_SDRAM_BASE 0x80000000
280 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
281 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
282 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
283 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
285 #define CONFIG_BOARD_EARLY_INIT_F
287 #endif /* __CONFIG_H */