3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_X86 1 /* This is a X86 CPU */
38 #define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */
39 #define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
40 #define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */
42 /* define at most one of these */
43 #undef CFG_SDRAM_CAS_LATENCY_2T
44 #define CFG_SDRAM_CAS_LATENCY_3T
46 #define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
47 #define CFG_RESET_GENERIC 1 /* use tripple-fault to reset cpu */
48 #undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */
49 #undef CFG_TIMER_SC520 /* use SC520 swtimers */
50 #define CFG_TIMER_GENERIC 1 /* use the i8254 PIT timers */
51 #undef CFG_TIMER_TSC /* use the Pentium TSC timers */
52 #define CFG_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
53 * in the SC520 on the CDP */
55 #define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */
57 #define CONFIG_SHOW_BOOT_PROGRESS 1
58 #define CONFIG_LAST_STAGE_INIT 1
61 * Size of malloc() pool
63 #define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
66 /* allow to overwrite serial and ethaddr */
67 #define CONFIG_ENV_OVERWRITE
68 #define CFG_ENV_IS_NOWHERE 1
69 #undef CFG_ENV_IS_IN_FLASH
70 #undef CFG_ENV_IS_IN_NVRAM
71 #undef CFG_ENV_IS_INEEPROM
73 #define CONFIG_BAUDRATE 9600
75 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET)
77 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
78 #include <cmd_confdefs.h>
80 #define CONFIG_BOOTDELAY 15
81 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
82 /* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
84 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
85 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
86 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
89 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
90 #define CFG_JFFS2_NUM_BANKS 1 /* */
93 * Miscellaneous configurable options
95 #define CFG_LONGHELP /* undef to save memory */
96 #define CFG_PROMPT "boot > " /* Monitor Command Prompt */
97 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
98 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
99 #define CFG_MAXARGS 16 /* max number of command args */
100 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
102 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
103 #define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
105 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
107 #define CFG_LOAD_ADDR 0x38000000 /* default load address */
109 #define CFG_HZ 1024 /* incrementer freq: 1kHz */
111 /* valid baudrates */
112 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
115 /*-----------------------------------------------------------------------
116 * Physical Memory Map
118 #define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */
121 #define PHYS_FLASH_1 0x38000000 /* Flash Bank #1 */
122 #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
124 #define CFG_FLASH_BASE PHYS_FLASH_1
126 /*-----------------------------------------------------------------------
127 * FLASH and environment organization
129 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
130 #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
132 /* timeout values are in ticks */
133 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
134 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
136 #define CFG_ENV_IS_IN_FLASH 1
137 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x7a0000) /* Addr of Environment Sector */
138 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
141 /*-----------------------------------------------------------------------
144 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
146 #define CONFIG_PCNET_79C973
147 #define CONFIG_PCNET_79C975
148 #define PCNET_HAS_PROM 1
149 /************************************************************
151 ************************************************************/
152 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
153 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
155 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
156 #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
157 #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
158 #define CFG_ATA_REG_OFFSET 0 /* reg offset */
159 #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
161 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
162 #undef CONFIG_IDE_LED /* no led for ide supported */
163 #undef CONFIG_IDE_RESET /* reset for ide unsupported... */
164 #undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
166 /************************************************************
167 * ATAPI support (experimental)
168 ************************************************************/
169 #define CONFIG_ATAPI /* enable ATAPI Support */
171 /************************************************************
172 * DISK Partition support
173 ************************************************************/
174 #define CONFIG_DOS_PARTITION
175 #define CONFIG_MAC_PARTITION
176 #define CONFIG_ISO_PARTITION /* Experimental */
178 /************************************************************
180 ************************************************************/
181 #define CONFIG_ISA_KEYBOARD
184 /************************************************************
186 ************************************************************/
187 #define CONFIG_VIDEO /*To enable video controller support */
188 #define CONFIG_VIDEO_CT69000
189 #define CONFIG_CFB_CONSOLE
190 #define CONFIG_VIDEO_LOGO
191 #define CONFIG_CONSOLE_EXTRA_INFO
192 #define CONFIG_VGA_AS_SINGLE_DEVICE
193 #define CONFIG_VIDEO_SW_CURSOR
194 #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
197 /************************************************************
199 ***********************************************************/
200 #define CONFIG_RTC_MC146818
201 #undef CONFIG_WATCHDOG /* watchdog disabled */
206 #define CONFIG_PCI /* include pci support */
207 #define CONFIG_PCI_PNP /* pci plug-and-play */
208 #define CONFIG_PCI_SCAN_SHOW
210 #endif /* __CONFIG_H */