2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #define CONFIG_SYS_GENERIC_BOARD
9 /* Virtual target or real hardware */
11 #define CONFIG_SYS_THUMB_BUILD
15 * High level configuration
17 #define CONFIG_DISPLAY_CPUINFO
18 #define CONFIG_DISPLAY_BOARDINFO_LATE
19 #define CONFIG_ARCH_EARLY_INIT_R
20 #define CONFIG_SYS_NO_FLASH
24 #define CONFIG_OF_LIBFDT
25 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
27 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
30 * Memory configurations
32 #define CONFIG_NR_DRAM_BANKS 1
33 #define PHYS_SDRAM_1 0x0
34 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
35 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
36 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
38 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
39 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
40 #define CONFIG_SYS_INIT_SP_ADDR \
41 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
42 GENERATED_GBL_DATA_SIZE)
44 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
45 #define CONFIG_SYS_TEXT_BASE 0x08000040
47 #define CONFIG_SYS_TEXT_BASE 0x01000040
51 * U-Boot general configurations
53 #define CONFIG_SYS_LONGHELP
54 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
55 #define CONFIG_SYS_PBSIZE \
56 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
57 /* Print buffer size */
58 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
60 /* Boot argument buffer size */
61 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
62 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
63 #define CONFIG_CMDLINE_EDITING /* Command history etc */
64 #define CONFIG_SYS_HUSH_PARSER
69 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
70 #define CONFIG_SYS_CACHELINE_SIZE 32
71 #define CONFIG_SYS_L2_PL310
72 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
75 * EPCS/EPCQx1 Serial Flash Controller
77 #ifdef CONFIG_ALTERA_SPI
78 #define CONFIG_CMD_SPI
80 #define CONFIG_SF_DEFAULT_SPEED 30000000
81 #define CONFIG_SPI_FLASH
82 #define CONFIG_SPI_FLASH_STMICRO
83 #define CONFIG_SPI_FLASH_BAR
85 * The base address is configurable in QSys, each board must specify the
86 * base address based on it's particular FPGA configuration. Please note
87 * that the address here is incremented by 0x400 from the Base address
88 * selected in QSys, since the SPI registers are at offset +0x400.
89 * #define CONFIG_SYS_SPI_BASE 0xff240400
94 * Ethernet on SoC (EMAC)
96 #define CONFIG_DESIGNWARE_ETH
97 #define CONFIG_NET_MULTI
98 #define CONFIG_DW_ALTDESCRIPTOR
100 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
101 #define CONFIG_PHYLIB
102 #define CONFIG_PHY_GIGE
108 #ifdef CONFIG_CMD_FPGA
110 #define CONFIG_FPGA_ALTERA
111 #define CONFIG_FPGA_SOCFPGA
112 #define CONFIG_FPGA_COUNT 1
118 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
119 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
120 #define CONFIG_SYS_TIMER_COUNTS_DOWN
121 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
122 #define CONFIG_SYS_TIMER_RATE 2400000
124 #define CONFIG_SYS_TIMER_RATE 25000000
130 #ifdef CONFIG_HW_WATCHDOG
131 #define CONFIG_DESIGNWARE_WATCHDOG
132 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
133 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
134 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000
140 #ifdef CONFIG_CMD_MMC
142 #define CONFIG_BOUNCE_BUFFER
143 #define CONFIG_GENERIC_MMC
146 /* using smaller max blk cnt to avoid flooding the limited stack we have */
147 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
153 #define CONFIG_SYS_I2C
154 #define CONFIG_SYS_I2C_DW
155 #define CONFIG_SYS_I2C_BUS_MAX 4
156 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
157 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
158 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
159 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
160 /* Using standard mode which the speed up to 100Kb/s */
161 #define CONFIG_SYS_I2C_SPEED 100000
162 #define CONFIG_SYS_I2C_SPEED1 100000
163 #define CONFIG_SYS_I2C_SPEED2 100000
164 #define CONFIG_SYS_I2C_SPEED3 100000
165 /* Address of device when used as slave */
166 #define CONFIG_SYS_I2C_SLAVE 0x02
167 #define CONFIG_SYS_I2C_SLAVE1 0x02
168 #define CONFIG_SYS_I2C_SLAVE2 0x02
169 #define CONFIG_SYS_I2C_SLAVE3 0x02
171 /* Clock supplied to I2C controller in unit of MHz */
172 unsigned int cm_get_l4_sp_clk_hz(void);
173 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
175 #define CONFIG_CMD_I2C
180 #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
181 #define CONFIG_CADENCE_QSPI
182 /* Enable multiple SPI NOR flash manufacturers */
183 #define CONFIG_SPI_FLASH /* SPI flash subsystem */
184 #define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
185 #define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
186 #define CONFIG_SPI_FLASH_MTD
187 /* QSPI reference clock */
189 unsigned int cm_get_qspi_controller_clk_hz(void);
190 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
192 #define CONFIG_CQSPI_DECODER 0
193 #define CONFIG_CMD_SF
196 #ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
197 #define CONFIG_DESIGNWARE_SPI
198 #define CONFIG_CMD_SPI
204 #define CONFIG_SYS_NS16550
205 #define CONFIG_SYS_NS16550_SERIAL
206 #define CONFIG_SYS_NS16550_REG_SIZE -4
207 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
208 #define CONFIG_SYS_NS16550_CLK 1000000
210 #define CONFIG_SYS_NS16550_CLK 100000000
212 #define CONFIG_CONS_INDEX 1
213 #define CONFIG_BAUDRATE 115200
218 #ifdef CONFIG_CMD_USB
219 #define CONFIG_USB_DWC2
220 #define CONFIG_USB_STORAGE
222 * NOTE: User must define either of the following to select which
223 * of the two USB controllers available on SoCFPGA to use.
224 * The DWC2 driver doesn't support multiple USB controllers.
225 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS
226 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
231 * USB Gadget (DFU, UMS)
233 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
234 #define CONFIG_USB_GADGET
235 #define CONFIG_USB_GADGET_S3C_UDC_OTG
236 #define CONFIG_USB_GADGET_DUALSPEED
237 #define CONFIG_USB_GADGET_VBUS_DRAW 2
239 /* USB Composite download gadget - g_dnl */
240 #define CONFIG_USBDOWNLOAD_GADGET
241 #define CONFIG_USB_GADGET_MASS_STORAGE
243 #define CONFIG_DFU_FUNCTION
244 #define CONFIG_DFU_MMC
245 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
246 #define DFU_DEFAULT_POLL_TIMEOUT 300
249 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
250 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
251 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
252 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
253 #ifndef CONFIG_G_DNL_MANUFACTURER
254 #define CONFIG_G_DNL_MANUFACTURER "Altera"
261 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
262 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
263 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
264 #define CONFIG_ENV_IS_NOWHERE
265 #define CONFIG_ENV_SIZE 4096
270 * SRAM Memory layout:
272 * 0xFFFF_0000 ...... Start of SRAM
273 * 0xFFFF_xxxx ...... Top of stack (grows down)
274 * 0xFFFF_yyyy ...... Malloc area
275 * 0xFFFF_zzzz ...... Global Data
276 * 0xFFFF_FF00 ...... End of SRAM
278 #define CONFIG_SPL_FRAMEWORK
279 #define CONFIG_SPL_BOARD_INIT
280 #define CONFIG_SPL_RAM_DEVICE
281 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
282 #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
283 #define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
285 #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
286 #define CONFIG_CRC32_VERIFY
288 /* Linker script for SPL */
289 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
291 #define CONFIG_SPL_LIBCOMMON_SUPPORT
292 #define CONFIG_SPL_LIBGENERIC_SUPPORT
293 #define CONFIG_SPL_WATCHDOG_SUPPORT
294 #define CONFIG_SPL_SERIAL_SUPPORT
296 #ifdef CONFIG_SPL_BUILD
297 #undef CONFIG_PARTITIONS