2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/socfpga_base_addrs.h>
10 #include "../../board/altera/socfpga/pinmux_config.h"
11 #include "../../board/altera/socfpga/iocsr_config.h"
12 #include "../../board/altera/socfpga/pll_config.h"
15 * High level configuration
17 /* Virtual target or real hardware */
18 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
21 #define CONFIG_SYS_DCACHE_OFF
24 #define CONFIG_MISC_INIT_R
25 #define CONFIG_SINGLE_BOOTLOADER
26 #define CONFIG_SOCFPGA
29 /* base address for .text section */
30 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
31 #define CONFIG_SYS_TEXT_BASE 0x08000040
33 #define CONFIG_SYS_TEXT_BASE 0x01000040
35 #define CONFIG_SYS_LOAD_ADDR 0x7fc0
37 /* Console I/O Buffer Size */
38 #define CONFIG_SYS_CBSIZE 256
39 /* Monitor Command Prompt */
40 #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
41 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
42 sizeof(CONFIG_SYS_PROMPT) + 16)
45 * Display CPU and Board Info
47 #define CONFIG_DISPLAY_CPUINFO
48 #define CONFIG_DISPLAY_BOARDINFO
51 * Enable early stage initialization at C environment
53 #define CONFIG_BOARD_EARLY_INIT_F
55 /* flat device tree */
56 #define CONFIG_OF_LIBFDT
57 /* skip updating the FDT blob */
58 #define CONFIG_FDT_BLOB_SKIP_UPDATE
59 /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
60 #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
62 #define CONFIG_SPL_RAM_DEVICE
63 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
64 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
65 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
68 * Memory allocation (MALLOC)
70 /* Room required on the stack for the environment data */
71 #define CONFIG_ENV_SIZE 1024
72 /* Size of DRAM reserved for malloc() use */
73 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
75 /* SP location before relocation, must use scratch RAM */
76 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
77 /* Reserving 0x100 space at back of scratch RAM for debug info */
78 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
79 /* Stack pointer prior relocation, must situated at on-chip RAM */
80 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
81 CONFIG_SYS_INIT_RAM_SIZE - \
82 GENERATED_GBL_DATA_SIZE)
86 * Command line configuration.
88 #define CONFIG_SYS_NO_FLASH
89 #include <config_cmd_default.h>
90 /* FAT file system support */
91 #define CONFIG_CMD_FAT
97 #define CONFIG_DOS_PARTITION 1
99 #ifdef CONFIG_SPL_BUILD
100 #undef CONFIG_PARTITIONS
107 /* Delay before automatically booting the default image */
108 #define CONFIG_BOOTDELAY 3
109 /* Enable auto completion of commands using TAB */
110 #define CONFIG_AUTO_COMPLETE
111 /* use "hush" command parser */
112 #define CONFIG_SYS_HUSH_PARSER
113 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
114 #define CONFIG_CMD_RUN
116 #define CONFIG_BOOTCOMMAND "run ramboot"
119 * arguments passed to the bootm command. The value of
120 * CONFIG_BOOTARGS goes into the environment value "bootargs".
121 * Do note the value will overide also the chosen node in FDT blob.
123 #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
125 #define CONFIG_EXTRA_ENV_SETTINGS \
127 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
128 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
129 "bootm ${loadaddr} - ${fdt_addr}\0" \
130 "bootimage=uImage\0" \
132 "fsloadcmd=ext2load\0" \
133 "bootm ${loadaddr} - ${fdt_addr}\0" \
134 "qspiroot=/dev/mtdblock0\0" \
135 "qspirootfstype=jffs2\0" \
136 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
137 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
138 "bootm ${loadaddr} - ${fdt_addr}\0"
140 /* using environment setting for stdin, stdout, stderr */
141 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
142 /* Enable the call to overwrite_console() */
143 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
144 /* Enable overwrite of previous console environment settings */
145 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
147 /* max number of command args */
148 #define CONFIG_SYS_MAXARGS 16
158 /* We have 1 bank of DRAM */
159 #define CONFIG_NR_DRAM_BANKS 1
161 #define CONFIG_SYS_SDRAM_BASE 0x00000000
162 /* SDRAM memory size */
163 #define PHYS_SDRAM_1_SIZE 0x40000000
165 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
166 #define CONFIG_SYS_MEMTEST_START 0x00000000
167 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
170 * NS16550 Configuration
172 #define UART0_BASE SOCFPGA_UART0_ADDRESS
173 #define CONFIG_SYS_NS16550
174 #define CONFIG_SYS_NS16550_SERIAL
175 #define CONFIG_SYS_NS16550_REG_SIZE -4
176 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
177 #define CONFIG_CONS_INDEX 1
178 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
179 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
180 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
181 #define V_NS16550_CLK 1000000
183 #define V_NS16550_CLK 100000000
185 #define CONFIG_BAUDRATE 115200
190 #define CONFIG_SYS_NO_FLASH
195 /* This timer use eosc1 where the clock frequency is fixed
196 * throughout any condition */
197 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
199 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
200 #define CONFIG_SYS_TIMER_RATE 2400000
202 #define CONFIG_SYS_TIMER_RATE 25000000
204 #define CONFIG_SYS_TIMER_COUNTS_DOWN
205 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
207 #define CONFIG_ENV_IS_NOWHERE
212 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
213 #define CONFIG_DESIGNWARE_ETH 1
216 #ifdef CONFIG_DESIGNWARE_ETH
217 #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
218 #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
219 /* console support for network */
220 #define CONFIG_CMD_DHCP
221 #define CONFIG_CMD_MII
222 #define CONFIG_CMD_NET
223 #define CONFIG_CMD_PING
225 #define CONFIG_NET_MULTI
226 #define CONFIG_DW_ALTDESCRIPTOR
228 #define CONFIG_PHY_GIGE
229 #define CONFIG_DW_AUTONEG
230 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
231 #define CONFIG_PHYLIB
232 #define CONFIG_PHY_MICREL
233 #define CONFIG_PHY_MICREL_KSZ9021
234 /* EMAC controller and PHY used */
235 #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
236 #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
237 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
238 #endif /* CONFIG_DESIGNWARE_ETH */
243 #define CONFIG_HW_WATCHDOG
244 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
245 #define CONFIG_DESIGNWARE_WATCHDOG
246 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
247 /* Clocks source frequency to watchdog timer */
248 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
252 * SPL "Second Program Loader" aka Initial Software
255 /* Enable building of SPL globally */
256 #define CONFIG_SPL_FRAMEWORK
258 /* TEXT_BASE for linking the SPL binary */
259 #define CONFIG_SPL_TEXT_BASE 0xFFFF0000
261 /* Stack size for SPL */
262 #define CONFIG_SPL_STACK_SIZE (4 * 1024)
264 /* MALLOC size for SPL */
265 #define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
267 #define CONFIG_SPL_SERIAL_SUPPORT
268 #define CONFIG_SPL_BOARD_INIT
270 #define CHUNKSZ_CRC32 (1 * 1024)
272 #define CONFIG_CRC32_VERIFY
274 /* Linker script for SPL */
275 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
277 /* Support for common/libcommon.o in SPL binary */
278 #define CONFIG_SPL_LIBCOMMON_SUPPORT
279 /* Support for lib/libgeneric.o in SPL binary */
280 #define CONFIG_SPL_LIBGENERIC_SUPPORT
282 /* Support for watchdog */
283 #define CONFIG_SPL_WATCHDOG_SUPPORT
285 #endif /* __CONFIG_H */