2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
9 #include <asm/arch/socfpga_base_addrs.h>
10 #include "../../board/altera/socfpga/pinmux_config.h"
11 #include "../../board/altera/socfpga/iocsr_config.h"
12 #include "../../board/altera/socfpga/pll_config.h"
14 #define CONFIG_SYS_GENERIC_BOARD
16 /* Virtual target or real hardware */
17 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
20 #define CONFIG_SYS_THUMB_BUILD
22 #define CONFIG_SOCFPGA
25 #define CONFIG_SYS_NO_FLASH
26 #include <config_cmd_default.h>
27 #define CONFIG_DOS_PARTITION
28 #define CONFIG_FAT_WRITE
29 #define CONFIG_HW_WATCHDOG
31 #define CONFIG_CMD_ASKENV
32 #define CONFIG_CMD_BOOTZ
33 #define CONFIG_CMD_CACHE
34 #define CONFIG_CMD_DHCP
35 #define CONFIG_CMD_EXT4
36 #define CONFIG_CMD_EXT4_WRITE
37 #define CONFIG_CMD_FAT
38 #define CONFIG_CMD_FPGA
39 #define CONFIG_CMD_GREPENV
40 #define CONFIG_CMD_MII
41 #define CONFIG_CMD_MMC
42 #define CONFIG_CMD_NET
43 #define CONFIG_CMD_PING
44 #define CONFIG_CMD_SETEXPR
46 #define CONFIG_REGEX /* Enable regular expression support */
49 * High level configuration
51 #define CONFIG_DISPLAY_CPUINFO
52 #define CONFIG_DISPLAY_BOARDINFO
53 #define CONFIG_BOARD_EARLY_INIT_F
54 #define CONFIG_MISC_INIT_R
55 #define CONFIG_SYS_NO_FLASH
59 #define CONFIG_OF_LIBFDT
60 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
62 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
65 * Memory configurations
67 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
68 #define CONFIG_NR_DRAM_BANKS 1
69 #define PHYS_SDRAM_1 0x0
70 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
71 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
72 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
74 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
75 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
76 #define CONFIG_SYS_INIT_SP_ADDR \
77 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
78 GENERATED_GBL_DATA_SIZE)
80 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
81 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
82 #define CONFIG_SYS_TEXT_BASE 0x08000040
84 #define CONFIG_SYS_TEXT_BASE 0x01000040
88 #define CONFIG_BOOTDELAY 3
89 #define CONFIG_BOOTFILE "zImage"
90 #define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
91 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
92 #define CONFIG_BOOTCOMMAND "run ramboot"
94 #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
96 #define CONFIG_LOADADDR 0x8000
97 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
100 * U-Boot general configurations
102 #define CONFIG_SYS_LONGHELP
103 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
104 #define CONFIG_SYS_PBSIZE \
105 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
106 /* Print buffer size */
107 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
108 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
109 /* Boot argument buffer size */
110 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
111 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
112 #define CONFIG_CMDLINE_EDITING /* Command history etc */
113 #define CONFIG_SYS_HUSH_PARSER
118 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
119 #define CONFIG_SYS_CACHELINE_SIZE 32
120 #define CONFIG_SYS_L2_PL310
121 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
124 * Ethernet on SoC (EMAC)
126 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
127 #define CONFIG_DESIGNWARE_ETH
128 #define CONFIG_NET_MULTI
129 #define CONFIG_DW_ALTDESCRIPTOR
131 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
132 #define CONFIG_PHYLIB
133 #define CONFIG_PHY_GIGE
135 #define CONFIG_EMAC_BASE SOCFPGA_EMAC0_ADDRESS
136 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
137 #define CONFIG_EPHY0_PHY_ADDR 0
140 #define CONFIG_EPHY1_PHY_ADDR 4
141 #define CONFIG_PHY_MICREL
142 #define CONFIG_PHY_MICREL_KSZ9021
143 #define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
144 #define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
145 #define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
146 #define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
153 #ifdef CONFIG_CMD_FPGA
155 #define CONFIG_FPGA_ALTERA
156 #define CONFIG_FPGA_SOCFPGA
157 #define CONFIG_FPGA_COUNT 1
163 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
164 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
165 #define CONFIG_SYS_TIMER_COUNTS_DOWN
166 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
167 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
168 #define CONFIG_SYS_TIMER_RATE 2400000
170 #define CONFIG_SYS_TIMER_RATE 25000000
176 #ifdef CONFIG_HW_WATCHDOG
177 #define CONFIG_DESIGNWARE_WATCHDOG
178 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
179 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
180 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000
186 #ifdef CONFIG_CMD_MMC
188 #define CONFIG_BOUNCE_BUFFER
189 #define CONFIG_GENERIC_MMC
191 #define CONFIG_SOCFPGA_DWMMC
192 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
193 #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
194 #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
196 /* using smaller max blk cnt to avoid flooding the limited stack we have */
197 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
203 #define CONFIG_SYS_NS16550
204 #define CONFIG_SYS_NS16550_SERIAL
205 #define CONFIG_SYS_NS16550_REG_SIZE -4
206 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
207 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
208 #define CONFIG_SYS_NS16550_CLK 1000000
210 #define CONFIG_SYS_NS16550_CLK 100000000
212 #define CONFIG_CONS_INDEX 1
213 #define CONFIG_BAUDRATE 115200
218 * mw 0xffd05014 0x01bef032
220 #ifdef CONFIG_CMD_USB
221 #define CONFIG_USB_DWC2_OTG
222 /*#define CONFIG_USB_DWC2_REG_ADDR 0xffb00000*/
223 #define CONFIG_USB_DWC2_REG_ADDR 0xffb40000
224 #define CONFIG_USB_STORAGE
230 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
231 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
232 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
233 #define CONFIG_ENV_IS_NOWHERE
234 #define CONFIG_ENV_SIZE 4096
235 #define CONFIG_HOSTNAME socfpga_cyclone5
237 #define CONFIG_EXTRA_ENV_SETTINGS \
239 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
240 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
241 "bootm ${loadaddr} - ${fdt_addr}\0" \
242 "bootimage=zImage\0" \
244 "fdtimage=socfpga.dtb\0" \
245 "fsloadcmd=ext2load\0" \
246 "bootm ${loadaddr} - ${fdt_addr}\0" \
247 "mmcroot=/dev/mmcblk0p2\0" \
248 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
249 " root=${mmcroot} rw rootwait;" \
250 "bootz ${loadaddr} - ${fdt_addr}\0" \
251 "mmcload=mmc rescan;" \
252 "fatload mmc 0:1 ${loadaddr} ${bootimage};" \
253 "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
254 "qspiroot=/dev/mtdblock0\0" \
255 "qspirootfstype=jffs2\0" \
256 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
257 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
258 "bootm ${loadaddr} - ${fdt_addr}\0"
263 #define CONFIG_SPL_FRAMEWORK
264 #define CONFIG_SPL_BOARD_INIT
265 #define CONFIG_SPL_RAM_DEVICE
266 #define CONFIG_SPL_TEXT_BASE 0xFFFF0000
267 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
268 #define CONFIG_SPL_STACK_SIZE (4 * 1024)
269 #define CONFIG_SPL_MALLOC_SIZE (5 * 1024) /* FIXME */
270 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
271 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
273 #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
274 #define CONFIG_CRC32_VERIFY
276 /* Linker script for SPL */
277 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
279 #define CONFIG_SPL_LIBCOMMON_SUPPORT
280 #define CONFIG_SPL_LIBGENERIC_SUPPORT
281 #define CONFIG_SPL_WATCHDOG_SUPPORT
282 #define CONFIG_SPL_SERIAL_SUPPORT
284 #ifdef CONFIG_SPL_BUILD
285 #undef CONFIG_PARTITIONS
288 #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */