include/configs/socfpga_cyclone5.h

   1 /*
   2  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
   7 #define __CONFIG_SOCFPGA_CYCLONE5_H__
   8
   9 #include <asm/arch/socfpga_base_addrs.h>
  10 #include "../../board/altera/socfpga/pinmux_config.h"
  11 #include "../../board/altera/socfpga/iocsr_config.h"
  12 #include "../../board/altera/socfpga/pll_config.h"
  13
  14 /* U-Boot Commands */
  15 #define CONFIG_SYS_NO_FLASH
  16 #include <config_cmd_default.h>
  17 #define CONFIG_DOS_PARTITION
  18 #define CONFIG_FAT_WRITE
  19 #define CONFIG_HW_WATCHDOG
  20
  21 #define CONFIG_CMD_ASKENV
  22 #define CONFIG_CMD_BOOTZ
  23 #define CONFIG_CMD_CACHE
  24 #define CONFIG_CMD_DHCP
  25 #define CONFIG_CMD_EXT4
  26 #define CONFIG_CMD_EXT4_WRITE
  27 #define CONFIG_CMD_FAT
  28 #define CONFIG_CMD_FPGA
  29 #define CONFIG_CMD_GREPENV
  30 #define CONFIG_CMD_MII
  31 #define CONFIG_CMD_MMC
  32 #define CONFIG_CMD_NET
  33 #define CONFIG_CMD_PING
  34 #define CONFIG_CMD_SETEXPR
  35
  36 #define CONFIG_REGEX                    /* Enable regular expression support */
  37
  38 /* Memory configurations */
  39 #define PHYS_SDRAM_1_SIZE               0x40000000      /* 1GiB on SoCDK */
  40
  41 /* Booting Linux */
  42 #define CONFIG_BOOTDELAY        3
  43 #define CONFIG_BOOTFILE         "zImage"
  44 #define CONFIG_BOOTARGS         "console=ttyS0" __stringify(CONFIG_BAUDRATE)
  45 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  46 #define CONFIG_BOOTCOMMAND      "run ramboot"
  47 #else
  48 #define CONFIG_BOOTCOMMAND      "run mmcload; run mmcboot"
  49 #endif
  50 #define CONFIG_LOADADDR         0x8000
  51 #define CONFIG_SYS_LOAD_ADDR    CONFIG_LOADADDR
  52
  53 /* Ethernet on SoC (EMAC) */
  54 #if defined(CONFIG_CMD_NET)
  55 #define CONFIG_EMAC_BASE                SOCFPGA_EMAC0_ADDRESS
  56 #define CONFIG_PHY_INTERFACE_MODE       PHY_INTERFACE_MODE_RGMII
  57 #define CONFIG_EPHY0_PHY_ADDR           0
  58
  59 /* PHY */
  60 #define CONFIG_EPHY1_PHY_ADDR           4
  61 #define CONFIG_PHY_MICREL
  62 #define CONFIG_PHY_MICREL_KSZ9021
  63 #define CONFIG_KSZ9021_CLK_SKEW_ENV     "micrel-ksz9021-clk-skew"
  64 #define CONFIG_KSZ9021_CLK_SKEW_VAL     0xf0f0
  65 #define CONFIG_KSZ9021_DATA_SKEW_ENV    "micrel-ksz9021-data-skew"
  66 #define CONFIG_KSZ9021_DATA_SKEW_VAL    0x0
  67
  68 #endif
  69
  70 /* Extra Environment */
  71 #define CONFIG_HOSTNAME         socfpga_cyclone5
  72
  73 #define CONFIG_EXTRA_ENV_SETTINGS \
  74         "verify=n\0" \
  75         "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  76         "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
  77                 "bootm ${loadaddr} - ${fdt_addr}\0" \
  78         "bootimage=zImage\0" \
  79         "fdt_addr=100\0" \
  80         "fdtimage=socfpga.dtb\0" \
  81                 "fsloadcmd=ext2load\0" \
  82         "bootm ${loadaddr} - ${fdt_addr}\0" \
  83         "mmcroot=/dev/mmcblk0p2\0" \
  84         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  85                 " root=${mmcroot} rw rootwait;" \
  86                 "bootz ${loadaddr} - ${fdt_addr}\0" \
  87         "mmcload=mmc rescan;" \
  88                 "fatload mmc 0:1 ${loadaddr} ${bootimage};" \
  89                 "fatload mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  90         "qspiroot=/dev/mtdblock0\0" \
  91         "qspirootfstype=jffs2\0" \
  92         "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
  93                 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
  94                 "bootm ${loadaddr} - ${fdt_addr}\0"
  95
  96 /* The rest of the configuration is shared */
  97 #include <configs/socfpga_common.h>
  98
  99 #endif  /* __CONFIG_SOCFPGA_CYCLONE5_H__ */