3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * Configuation settings for the TRITON320 board.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * High Level Configuration Options
37 #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
38 #define CONFIG_TRITON320 1 /* Zylonite board */
40 /* #define CONFIG_LCD 1 */
42 #define CONFIG_SHARP_LM8V31
44 /* #define CONFIG_MMC 1 */
45 #define BOARD_LATE_INIT 1
47 #define CONFIG_SKIP_RELOCATE_UBOOT 1
48 #undef CONFIG_SKIP_LOWLEVEL_INIT
49 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
52 * Size of malloc() pool
54 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
55 #define CFG_GBL_DATA_SIZE 512 /* size in bytes reserved for initial data */
62 #define CONFIG_DRIVER_DM9000 1
63 #define CONFIG_DM9000_BASE 0x10000300
64 #define DM9000_IO CONFIG_DM9000_BASE
65 #define DM9000_DATA (CONFIG_DM9000_BASE+0x8000)
66 #define CONFIG_DM9000_USE_16BIT
71 * select serial console configuration
73 #define CONFIG_FFUART 1
75 /* allow to overwrite serial and ethaddr */
76 #define CONFIG_ENV_OVERWRITE
78 #define CONFIG_BAUDRATE 38400
81 # define CONFIG_COMMANDS CFG_CMD_AUTOSCRIPT \
95 & ~(CFG_CMD_JFFS2 | CFG_CMD_FLASH | CFG_CMD_IMLS)
98 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL| \
106 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
107 #include <cmd_confdefs.h>
109 #define CONFIG_BOOTDELAY 3
110 #define CONFIG_BOOTCOMMAND "bootm 80000"
111 #define CONFIG_BOOTARGS "root=/dev/mtdblock1 rootfstype=jffs2 console=ttyS0,38400"
112 #define CONFIG_BOOT_RETRY_TIME -1
113 #define CONFIG_BOOT_RETRY_MIN 60
114 #define CONFIG_RESET_TO_RETRY
115 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
116 #define CONFIG_AUTOBOOT_DELAY_STR " "
117 #define CONFIG_AUTOBOOT_STOP_STR "system"
119 #define CONFIG_ETHADDR ff:ff:ff:ff:ff:ff
120 #define CONFIG_NETMASK 255.255.255.255
121 #define CONFIG_IPADDR 0.0.0.0
122 #define CONFIG_SERVERIP 0.0.0.0
123 #define CONFIG_CMDLINE_TAG 1
124 #define CONFIG_SETUP_MEMORY_TAGS 1
125 #define CONFIG_CMDLINE_EDITING
126 #define CONFIG_TIMESTAMP
127 #define CONFIG_USE_MAC_FROM_ENV
129 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
130 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
131 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
135 * Miscellaneous configurable options
137 #define CFG_HUSH_PARSER 1
138 #define CFG_PROMPT_HUSH_PS2 "> "
140 #define CFG_LONGHELP /* undef to save memory */
141 #ifdef CFG_HUSH_PARSER
142 #define CFG_PROMPT "$ " /* Monitor Command Prompt */
144 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
146 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
147 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
148 #define CFG_MAXARGS 16 /* max number of command args */
149 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
150 #define CFG_DEVICE_NULLDEV 1
152 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
153 #define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
155 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
157 #define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */
159 /* Monahans Core Frequency */
160 #define CFG_MONAHANS_RUN_MODE_OSC_RATIO 31 /* valid values: 8, 16, 24, 31 */
161 #define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 2 /* valid values: 1, 2 */
163 /* valid baudrates */
164 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
166 /* #define CFG_MMC_BASE 0xF0000000 */
171 * The stack sizes are set up in start.S using the settings below
173 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
174 #ifdef CONFIG_USE_IRQ
175 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
176 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
180 * Physical Memory Map
182 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
183 #define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
184 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
186 #define CFG_DRAM_BASE PHYS_SDRAM_1
187 #define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
190 #define CFG_LOAD_ADDR (PHYS_SDRAM_1 + 0x100000) /* default load address */
192 #define CFG_SKIP_DRAM_SCRUB
197 /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
198 #define CONFIG_NEW_NAND_CODE
199 #define CFG_NAND0_BASE 0x0
200 #undef CFG_NAND1_BASE
202 #define CONFIG_MTD_NAND_ECC_JFFS2 1
204 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
205 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
207 /* nand timeout values */
208 #define CFG_NAND_PROG_ERASE_TO 9000
209 #define CFG_NAND_OTHER_TO 2000
210 #define CFG_NAND_SENDCMD_RETRY 3
211 #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
213 /* NAND Timing Parameters (in ns) */
214 #define NAND_TIMING_tCH 10
215 #define NAND_TIMING_tCS 0
216 #define NAND_TIMING_tWH 20
217 #define NAND_TIMING_tWP 40
219 #define NAND_TIMING_tRH 20
220 #define NAND_TIMING_tRP 40
222 #define NAND_TIMING_tR 11123
223 #define NAND_TIMING_tWHR 100
224 #define NAND_TIMING_tAR 10
228 #define CFG_DFC_DEBUG1 /* useful */
229 #define CFG_DFC_DEBUG2 /* noisy */
230 #define CFG_DFC_DEBUG3 /* extremly noisy */
232 #undef CFG_DFC_DEBUG1 /* useful */
233 #undef CFG_DFC_DEBUG2 /* noisy */
234 #undef CFG_DFC_DEBUG3 /* extremly noisy */
237 #define CONFIG_MTD_DEBUG 0
238 #define CONFIG_MTD_DEBUG_VERBOSE 0
240 #define ADDR_COLUMN 1
242 #define ADDR_COLUMN_PAGE 3
244 #define NAND_ChipID_UNKNOWN 0x00
245 #define NAND_MAX_FLOORS 1
246 #define NAND_MAX_CHIPS 1
248 #define CFG_NO_FLASH 1
250 #define CFG_ENV_IS_IN_NAND 1
251 #define CFG_ENV_OFFSET 0x60000
252 #undef CFG_ENV_OFFSET_REDUND
253 #define CFG_ENV_SIZE 0x20000
255 #define CONFIG_JFFS2_NAND 1
256 #define CONFIG_JFFS2_NAND_DEV "nand0" /* nand device jffs2 lives on */
257 #define CONFIG_JFFS2_NAND_OFF 0x80000 /* start of jffs2 partition */
258 #define CONFIG_JFFS2_NAND_SIZE 64*1024*1024 /* size of jffs2 partition */
261 /* mtdparts command line support */
262 #define CONFIG_JFFS2_CMDLINE
263 #define MTDIDS_DEFAULT "nand0=triton320-nand"
264 #define MTDPARTS_DEFAULT "mtdparts=triton320-nand:128k(sbootl),256k(u-boot),128k(env),2m(linux_kernel),83456k(userfs),32m(wince);"
266 #endif /* __CONFIG_H */