2 * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
5 * Configuration settings for the HALE TT-01 board.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 /* High Level Configuration Options */
17 #define CONFIG_DISPLAY_CPUINFO
18 #define CONFIG_DISPLAY_BOARDINFO
20 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
21 #define CONFIG_SETUP_MEMORY_TAGS
22 #define CONFIG_INITRD_TAG
24 #define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
25 #define CONFIG_SYS_TEXT_BASE 0xA0000000
29 * Physical Memory Map:
30 * CS settings are defined by i.MX31:
31 * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
32 * - CS0 and CS1 are 128MB each, at A0000000 and A8000000
33 * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
35 * HALE set-up of the bluetechnix board for now is:
36 * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
37 * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
38 * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
39 * the flash chip is a mirrorbit S29WS256N !
40 * - the PSRAM is hooked to CS5 (0xB6000000)
41 * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
42 * - 64Mbit = 8MByte (will go away in the production set-up)
43 * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
44 * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
45 * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
47 * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
48 * is not used right now. We should be able to reduce the SOM to NAND flash
49 * only and boot from there.
51 #define CONFIG_NR_DRAM_BANKS 1
52 #define PHYS_SDRAM_1 CSD0_BASE
53 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
55 #define CONFIG_BOARD_EARLY_INIT_F
56 #define CONFIG_BOARD_LATE_INIT
58 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
59 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
60 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
61 #define CONFIG_SYS_GBL_DATA_OFFSET \
62 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
63 #define CONFIG_SYS_INIT_SP_ADDR \
64 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
66 /* default load address, 1MB up the road */
67 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
69 /* Size of malloc() pool, make sure possible frame buffer fits */
70 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
72 /* memtest works on all but the last 1MB (u-boot) and malloc area */
73 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
74 #define CONFIG_SYS_MEMTEST_END \
75 (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
77 /* CFI FLASH driver setup */
78 #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
79 #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
80 #define CONFIG_FLASH_SPANSION_S29WS_N
82 * TODO: Bluetechnix (the supplier of the SOM) did define these values
83 * in their original version of u-boot (1.2 or so). This should be
86 * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
87 * #define CONFIG_SYS_FLASH_PROTECTION
89 #define CONFIG_SYS_FLASH_BASE CS0_BASE
90 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
91 #define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
94 * FLASH and environment organization, only the Spansion chip is supported:
95 * - it has 254 * 128kB + 8 * 32kB blocks
96 * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
97 * and 2 sectors with 128k as environment =
98 * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
99 * - this could be less, but this is only for developer versions of the board
100 * and no-one is going to use the NOR flash anyway.
102 * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
103 * way to large, but it avoids ENV overwrite (when updating u-boot) in case
104 * size breaks the next boundary (as it has with 128k).
106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
107 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
109 #define CONFIG_ENV_IS_IN_FLASH
110 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
111 #define CONFIG_ENV_SIZE (128 * 1024)
113 /* Address and size of Redundant Environment Sector */
114 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
115 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
117 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
119 /* Hardware drivers */
122 * on TT-01 UART1 pins are used by Audio, so we use UART2
123 * TT-01 implements a hardware that turns off components depending on
124 * the power level. In PL=1 the RS232 transceiver is usually off,
125 * make sure that the transceiver is enabled during PL=1 for testing!
127 #define CONFIG_MXC_UART
128 #define CONFIG_MXC_UART_BASE UART2_BASE
130 #define CONFIG_MXC_SPI
131 #define CONFIG_MXC_GPIO
133 /* MC13783 connected to CSPI3 and SS0 */
135 #define CONFIG_POWER_SPI
136 #define CONFIG_POWER_FSL
138 #define CONFIG_FSL_PMIC_BUS 2
139 #define CONFIG_FSL_PMIC_CS 0
140 #define CONFIG_FSL_PMIC_CLK 1000000
141 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
142 #define CONFIG_FSL_PMIC_BITLEN 32
144 #define CONFIG_RTC_MC13XXX
146 /* allow to overwrite serial and ethaddr */
147 #define CONFIG_ENV_OVERWRITE
148 /* console is UART2 on TT-01 */
149 #define CONFIG_CONS_INDEX 1
150 #define CONFIG_BAUDRATE 115200
152 /* ethernet setup for the onboard smc9118 */
154 #define CONFIG_SMC911X
155 /* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
156 #define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
157 #define CONFIG_SMC911X_16_BIT
161 #define CONFIG_GENERIC_MMC
162 #define CONFIG_MXC_MMC
163 #define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR
167 #define CONFIG_VIDEO_MX3
168 #define CONFIG_CFB_CONSOLE
169 #define CONFIG_VIDEO_LOGO
170 /* splash image won't work with NAND boot, use preboot script */
171 #define CONFIG_VIDEO_SW_CURSOR
172 #define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
173 #define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
175 /* allow stdin, stdout and stderr variables to redirect output */
176 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
177 #define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */
178 #define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */
179 #define CONFIG_PREBOOT
181 /* allow decompressing max. 4MB */
182 #define CONFIG_VIDEO_BMP_GZIP
183 /* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */
184 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
189 #define CONFIG_CMD_DATE
190 #define CONFIG_CMD_PING
191 #define CONFIG_CMD_DHCP
192 #define CONFIG_CMD_NAND
194 * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
195 * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
196 * a software locking scheme.
198 #define CONFIG_CMD_BMP
200 #define CONFIG_BOOTDELAY 3
203 * currently a default setting for booting via script is implemented
204 * set user to login name and serverip to tftp host, define your
205 * boot behaviour in bootscript.loginname
207 * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
209 * This set-up is for the L5F30947T04 by Epson, which is
210 * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
211 * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
213 #define CONFIG_EXTRA_ENV_SETTINGS \
214 "videomode=epson\0" \
215 "epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
216 "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
217 "bootcmd=dhcp bootscript.${user}; source\0"
219 #define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
220 #define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
222 /* Miscellaneous configurable options */
223 #define CONFIG_SYS_HUSH_PARSER
225 #define CONFIG_SYS_LONGHELP /* undef to save memory */
226 #define CONFIG_SYS_PROMPT "TT01> "
227 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
228 /* Print Buffer Size */
229 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
230 sizeof(CONFIG_SYS_PROMPT)+16)
231 /* max number of command args */
232 #define CONFIG_SYS_MAXARGS 16
233 /* Boot Argument Buffer Size */
234 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
236 #define CONFIG_CMDLINE_EDITING
238 /* MMC boot support */
239 #define CONFIG_CMD_MMC
240 #define CONFIG_DOS_PARTITION
241 #define CONFIG_EFI_PARTITION
242 #define CONFIG_CMD_EXT2
243 #define CONFIG_CMD_FAT
245 #define CONFIG_NAND_MXC
246 #define CONFIG_SYS_MAX_NAND_DEVICE 1
249 * actually this is nothing someone wants to configure!
250 * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
251 * is not used by the driver.
253 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
254 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
255 #define CONFIG_MXC_NAND_HWECC
257 /* the current u-boot driver does not use the nand flash setup! */
258 #define CONFIG_SYS_NAND_LARGEPAGE
261 * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
262 * the current u-boot mxc_nand.c tries to auto-detect, but this only
263 * reads the boot settings during reset (which might be wrong)
266 #endif /* __CONFIG_H */