4 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
9 * SPDX-License-Identifier: GPL-2.0
19 #include <asm/sizes.h>
20 #include <asm/arch/omap.h>
23 * Ka-Ro TX48 board - SoC configuration
25 #define CONFIG_AM33XX_GPIO
26 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
28 #ifndef CONFIG_SPL_BUILD
29 #define CONFIG_SKIP_LOWLEVEL_INIT
30 #define CONFIG_SHOW_ACTIVITY
31 #define CONFIG_DISPLAY_CPUINFO
32 #define CONFIG_DISPLAY_BOARDINFO
33 #define CONFIG_BOARD_LATE_INIT
35 /* LCD Logo and Splash screen support */
38 #define CONFIG_SPLASH_SCREEN
39 #define CONFIG_SPLASH_SCREEN_ALIGN
40 #define CONFIG_VIDEO_DA8XX
41 #define DAVINCI_LCD_CNTL_BASE 0x4830e000
42 #define CONFIG_LCD_LOGO
43 #define LCD_BPP LCD_COLOR24
44 #define CONFIG_CMD_BMP
45 #define CONFIG_VIDEO_BMP_RLE8
46 #endif /* CONFIG_LCD */
47 #endif /* CONFIG_SPL_BUILD */
50 #define V_OSCK 24000000 /* Clock output from T2 */
54 * Memory configuration options
56 #define CONFIG_SYS_SDRAM_DDR3
57 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */
58 #define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
59 #define CONFIG_MAX_RAM_BANK_SIZE SZ_1G
61 #define CONFIG_STACKSIZE SZ_64K
62 #define CONFIG_SYS_MALLOC_LEN SZ_4M
64 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + SZ_64M)
65 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_8M)
67 #define CONFIG_SYS_CACHELINE_SIZE 64
70 * U-Boot general configurations
72 #define CONFIG_SYS_LONGHELP
73 #define CONFIG_SYS_PROMPT "TX48 U-Boot > "
74 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
75 #define CONFIG_SYS_PBSIZE \
76 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
77 /* Print buffer size */
78 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
79 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
80 /* Boot argument buffer size */
81 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
82 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
83 #define CONFIG_CMDLINE_EDITING /* Command history etc */
85 #define CONFIG_SYS_64BIT_VSPRINTF
86 #define CONFIG_SYS_NO_FLASH
89 * Flattened Device Tree (FDT) support
91 #ifdef CONFIG_OF_LIBFDT /* set via cmdline parameter thru boards.cfg */
92 #define CONFIG_FDT_FIXUP_PARTITIONS
93 #define CONFIG_OF_EMBED
94 #define CONFIG_OF_BOARD_SETUP
95 #define CONFIG_DEFAULT_DEVICE_TREE tx48
96 #define CONFIG_ARCH_DEVICE_TREE am33xx
97 #define CONFIG_MACH_TYPE (-1)
98 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
100 #ifndef MACH_TYPE_TIAM335EVM
101 #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
103 #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
109 #define xstr(s) str(s)
111 #define __pfx(x, s) (x##s)
112 #define _pfx(x, s) __pfx(x, s)
114 #define CONFIG_CMDLINE_TAG
115 #define CONFIG_SETUP_MEMORY_TAGS
116 #define CONFIG_BOOTDELAY 3
117 #define CONFIG_ZERO_BOOTDELAY_CHECK
118 #define CONFIG_SYS_AUTOLOAD "no"
119 #define CONFIG_BOOTFILE "uImage"
120 #define CONFIG_BOOTARGS "console=ttyO0,115200 ro debug panic=1"
121 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
122 #define CONFIG_LOADADDR 83000000
123 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
124 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
125 #define CONFIG_HW_WATCHDOG
130 #ifdef CONFIG_OF_LIBFDT
131 #define TX48_BOOTM_CMD \
132 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0"
133 #define TX48_MTDPARTS_CMD ""
135 #define TX48_BOOTM_CMD \
137 #define TX48_MTDPARTS_CMD " ${mtdparts}"
140 #define CONFIG_EXTRA_ENV_SETTINGS \
142 "baseboard=stk5-v3\0" \
143 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
144 " root=/dev/mmcblk0p2 rootwait\0" \
145 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
146 " root=/dev/mtdblock4 rootfstype=jffs2\0" \
147 "nfsroot=/tftpboot/rootfs\0" \
148 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
149 " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
150 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
151 " fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
152 "bootcmd_nand=set autostart no;run bootargs_nand;" \
153 " nboot linux;run bootm_cmd\0" \
154 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
157 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
159 " video=${video_mode} ${append_bootargs}\0" \
160 "cpu_clk=" xstr(CONFIG_SYS_MPU_CLK) "\0" \
161 "fdtaddr=81000000\0" \
162 "mtdids=" MTDIDS_DEFAULT "\0" \
163 "mtdparts=" MTDPARTS_DEFAULT "\0" \
164 "otg_mode=device\0" \
165 "touchpanel=tsc2007\0" \
166 "video_mode=da8xx-fb:640x480MR-24@60\0"
168 #define MTD_NAME "omap2-nand.0"
169 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
174 #include <config_cmd_default.h>
175 #define CONFIG_CMD_CACHE
176 #define CONFIG_CMD_MMC
177 #define CONFIG_CMD_NAND
178 #define CONFIG_CMD_MTDPARTS
179 #define CONFIG_CMD_BOOTCE
180 #define CONFIG_CMD_TIME
181 #define CONFIG_CMD_MEMTEST
186 #define CONFIG_SYS_NS16550
187 #define CONFIG_SYS_NS16550_SERIAL
188 #define CONFIG_SYS_NS16550_MEM32
189 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
190 #define CONFIG_SYS_NS16550_CLK 48000000
191 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
192 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
193 #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
195 #define CONFIG_SYS_NS16550_COM3 0x481aa000 /* UART2 */
196 #define CONFIG_SYS_NS16550_COM4 0x481aa000 /* UART3 */
197 #define CONFIG_SYS_NS16550_COM5 0x481aa000 /* UART4 */
198 #define CONFIG_CONS_INDEX 1 /* one based! */
199 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
201 #define CONFIG_SYS_CONSOLE_INFO_QUIET
206 #ifdef CONFIG_CMD_NET
207 #define CONFIG_DRIVER_TI_CPSW
208 #define CONFIG_NET_MULTI
209 #define CONFIG_PHY_GIGE
210 #define CONFIG_PHY_SMSC
211 #define CONFIG_PHYLIB
213 #define CONFIG_CMD_MII
214 #define CONFIG_CMD_DHCP
215 #define CONFIG_CMD_PING
216 /* Add for working with "strict" DHCP server */
217 #define CONFIG_BOOTP_SUBNETMASK
218 #define CONFIG_BOOTP_GATEWAY
219 #define CONFIG_BOOTP_DNS
220 #define CONFIG_BOOTP_DNS2
226 #ifdef CONFIG_CMD_NAND
227 #define CONFIG_MTD_DEVICE
228 #define CONFIG_ENV_IS_IN_NAND
229 #define CONFIG_NAND_OMAP_GPMC
230 #define GPMC_NAND_ECC_LP_x8_LAYOUT
231 #define GPMC_NAND_HW_ECC_LAYOUT_KERNEL GPMC_NAND_HW_ECC_LAYOUT
232 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
233 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
234 #define CONFIG_SYS_NAND_OOBSIZE 64
235 #define CONFIG_SYS_NAND_ECCSIZE 512
236 #define CONFIG_SYS_NAND_ECCBYTES 14
237 #define CONFIG_CMD_NAND_TRIMFFS
238 #define CONFIG_SYS_NAND_MAX_CHIPS 1
239 #define CONFIG_SYS_NAND_MAXBAD 20 /* Max. number of bad blocks guaranteed by manufacturer */
240 #define CONFIG_SYS_MAX_NAND_DEVICE 1
241 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
242 #define CONFIG_SYS_NAND_USE_FLASH_BBT
243 #ifdef CONFIG_ENV_IS_IN_NAND
244 #define CONFIG_ENV_OVERWRITE
245 #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
246 #define CONFIG_ENV_SIZE SZ_128K
247 #define CONFIG_ENV_RANGE 0x60000
248 #endif /* CONFIG_ENV_IS_IN_NAND */
249 #define CONFIG_SYS_NAND_BASE 0x08000000 /* must be defined but value is irrelevant */
250 #define NAND_BASE CONFIG_SYS_NAND_BASE
251 #endif /* CONFIG_CMD_NAND */
256 #ifdef CONFIG_CMD_MMC
257 #ifndef CONFIG_ENV_IS_IN_NAND
258 #define CONFIG_ENV_IS_IN_MMC
261 #define CONFIG_GENERIC_MMC
262 #define CONFIG_OMAP_HSMMC
263 #define CONFIG_OMAP_MMC_DEV_1
265 #define CONFIG_DOS_PARTITION
266 #define CONFIG_CMD_FAT
267 #define CONFIG_CMD_EXT2
270 * Environments on MMC
272 #ifdef CONFIG_ENV_IS_IN_MMC
273 #define CONFIG_SYS_MMC_ENV_DEV 0
274 #define CONFIG_ENV_OVERWRITE
275 /* Associated with the MMC layout defined in mmcops.c */
276 #define CONFIG_ENV_OFFSET SZ_1K
277 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
278 #define CONFIG_DYNAMIC_MMC_DEVNO
279 #endif /* CONFIG_ENV_IS_IN_MMC */
280 #endif /* CONFIG_CMD_MMC */
282 #ifdef CONFIG_ENV_OFFSET_REDUND
283 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
284 "128k(u-boot-spl)," \
286 xstr(CONFIG_ENV_RANGE) \
288 xstr(CONFIG_ENV_RANGE) \
289 "(env2),4m(linux),16m(rootfs),256k(dtb),107904k(userfs),512k@0x7f80000(bbt)ro"
291 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
292 "128k(u-boot-spl)," \
294 xstr(CONFIG_ENV_RANGE) \
295 "(env),4m(linux),16m(rootfs),256k(dtb),108288k(userfs),512k@0x7f80000(bbt)ro"
298 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
299 #define SRAM0_SIZE SZ_64K
300 #define OCMC_SRAM_BASE 0x40300000
301 #define CONFIG_SPL_STACK (OCMC_SRAM_BASE + 0xb800)
302 #define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + SZ_32K)
304 /* Platform/Board specific defs */
305 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
306 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
308 /* Defines for SPL */
310 #define CONFIG_SPL_FRAMEWORK
311 #define CONFIG_SPL_BOARD_INIT
312 #define CONFIG_SPL_MAX_SIZE (46 * SZ_1K)
313 #define CONFIG_SPL_GPIO_SUPPORT
314 #ifdef CONFIG_NAND_OMAP_GPMC
315 #define CONFIG_SPL_NAND_SUPPORT
316 #define CONFIG_SPL_NAND_DRIVERS
317 #define CONFIG_SPL_NAND_BASE
318 #define CONFIG_SPL_NAND_ECC
319 #define CONFIG_SPL_NAND_AM33XX_BCH
320 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
321 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
322 CONFIG_SYS_NAND_PAGE_SIZE)
323 #define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K
324 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
325 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
326 10, 11, 12, 13, 14, 15, 16, 17, \
327 18, 19, 20, 21, 22, 23, 24, 25, \
328 26, 27, 28, 29, 30, 31, 32, 33, \
329 34, 35, 36, 37, 38, 39, 40, 41, \
330 42, 43, 44, 45, 46, 47, 48, 49, \
331 50, 51, 52, 53, 54, 55, 56, 57, }
334 #define CONFIG_SPL_BSS_START_ADDR PHYS_SDRAM_1
335 #define CONFIG_SPL_BSS_MAX_SIZE SZ_512K
337 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
339 #define CONFIG_SPL_LIBCOMMON_SUPPORT
340 #define CONFIG_SPL_LIBGENERIC_SUPPORT
341 #define CONFIG_SPL_SERIAL_SUPPORT
342 #define CONFIG_SPL_YMODEM_SUPPORT
343 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
346 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
347 * 64 bytes before this address should be set aside for u-boot.img's
348 * header. That is 0x800FFFC0--0x80100000 should not be used for any
351 #define CONFIG_SYS_SPL_MALLOC_START (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
352 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M
354 #endif /* __CONFIG_H */