4 * Copyright (C) 2012-2014 Lothar Waßmann <LW@KARO-electronics.de>
7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
9 * SPDX-License-Identifier: GPL-2.0
16 #define CONFIG_AM33XX /* must be set before including omap.h */
17 #define CONFIG_SYS_L2CACHE_OFF
19 #include <linux/kconfig.h>
20 #include <linux/sizes.h>
21 #include <asm/arch/omap.h>
24 * Ka-Ro TX48 board - SoC configuration
27 #define CONFIG_AM33XX_GPIO
28 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
30 #ifndef CONFIG_SPL_BUILD
31 #define CONFIG_SKIP_LOWLEVEL_INIT
32 #define CONFIG_SHOW_ACTIVITY
33 #define CONFIG_DISPLAY_CPUINFO
34 #define CONFIG_DISPLAY_BOARDINFO
35 #define CONFIG_BOARD_LATE_INIT
36 #define CONFIG_SYS_GENERIC_BOARD
38 /* LCD Logo and Splash screen support */
40 #define CONFIG_VIDEO_DA8XX
41 #define CONFIG_SPLASH_SCREEN
42 #define CONFIG_SPLASH_SCREEN_ALIGN
43 #define CONFIG_AM335X_LCD
44 #define DAVINCI_LCD_CNTL_BASE 0x4830e000
45 #define CONFIG_LCD_LOGO
46 #define LCD_BPP LCD_COLOR32
47 #define CONFIG_CMD_BMP
48 #define CONFIG_VIDEO_BMP_RLE8
49 #endif /* CONFIG_LCD */
50 #endif /* CONFIG_SPL_BUILD */
53 #define V_OSCK 24000000 /* Clock output from T2 */
57 * Memory configuration options
59 #define CONFIG_SYS_SDRAM_DDR3
60 #define CONFIG_NR_DRAM_BANKS 0x1 /* '1' would be converted to 'y' by define2mk.sed */
61 #define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
62 #define CONFIG_MAX_RAM_BANK_SIZE SZ_1G
64 #define CONFIG_STACKSIZE SZ_64K
65 #define CONFIG_SYS_MALLOC_LEN SZ_4M
67 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + SZ_64M)
68 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_8M)
70 #define CONFIG_SYS_CACHELINE_SIZE 64
73 * U-Boot general configurations
75 #define CONFIG_SYS_LONGHELP
76 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
77 #define CONFIG_SYS_PBSIZE \
78 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
79 /* Print buffer size */
80 #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
81 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
82 /* Boot argument buffer size */
83 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
84 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
85 #define CONFIG_CMDLINE_EDITING /* Command history etc */
87 #define CONFIG_SYS_64BIT_VSPRINTF
90 * Flattened Device Tree (FDT) support
96 #define xstr(s) str(s)
98 #define __pfx(x, s) (x##s)
99 #define _pfx(x, s) __pfx(x, s)
101 #define CONFIG_CMDLINE_TAG
102 #define CONFIG_SETUP_MEMORY_TAGS
103 #define CONFIG_BOOTDELAY 3
104 #define CONFIG_ZERO_BOOTDELAY_CHECK
105 #define CONFIG_SYS_AUTOLOAD "no"
106 #define CONFIG_BOOTFILE "uImage"
107 #define CONFIG_BOOTARGS "init=/linuxrc console=ttyO0,115200 ro debug panic=1"
108 #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
109 #define CONFIG_LOADADDR 83000000
110 #define CONFIG_FDTADDR 81000000
111 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
112 #define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR)
113 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
116 * Extra Environment Settings
118 #define CONFIG_SYS_CPU_CLK_STR xstr(CONFIG_SYS_MPU_CLK)
120 #define CONFIG_EXTRA_ENV_SETTINGS \
122 "baseboard=stk5-v3\0" \
123 "bootargs_jffs2=run default_bootargs" \
124 ";setenv bootargs ${bootargs}" \
125 " root=/dev/mtdblock4 rootfstype=jffs2\0" \
126 "bootargs_mmc=run default_bootargs;setenv bootargs ${bootargs}" \
127 " root=/dev/mmcblk0p2 rootwait\0" \
128 "bootargs_nfs=run default_bootargs;setenv bootargs ${bootargs}" \
129 " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
131 "bootargs_ubifs=run default_bootargs" \
132 ";setenv bootargs ${bootargs}" \
133 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
134 "bootcmd_jffs2=setenv autostart no;run bootargs_jffs2" \
136 "bootcmd_mmc=setenv autostart no;run bootargs_mmc" \
137 ";fatload mmc 0 ${loadaddr} uImage\0" \
138 "bootcmd_nand=setenv autostart no;run bootargs_ubifs" \
140 "bootcmd_net=setenv autoload y" \
141 ";setenv autostart n;run bootargs_nfs" \
143 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
145 "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0" \
146 "default_bootargs=setenv bootargs " CONFIG_BOOTARGS \
147 " ${append_bootargs}\0" \
148 "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
149 "fdtsave=fdt resize;nand erase.part dtb" \
150 ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
151 "mtdids=" MTDIDS_DEFAULT "\0" \
152 "mtdparts=" MTDPARTS_DEFAULT "\0" \
153 "nfsroot=/tftpboot/rootfs\0" \
154 "otg_mode=device\0" \
155 "touchpanel=tsc2007\0" \
158 #define MTD_NAME "omap2-nand.0"
159 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
164 #define CONFIG_SYS_NS16550
165 #define CONFIG_SYS_NS16550_SERIAL
166 #define CONFIG_SYS_NS16550_MEM32
167 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
168 #define CONFIG_SYS_NS16550_CLK 48000000
169 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
170 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
171 #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
173 #define CONFIG_SYS_NS16550_COM3 0x481aa000 /* UART2 */
174 #define CONFIG_SYS_NS16550_COM4 0x481aa000 /* UART3 */
175 #define CONFIG_SYS_NS16550_COM5 0x481aa000 /* UART4 */
176 #define CONFIG_CONS_INDEX 1 /* one based! */
177 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
178 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
179 #define CONFIG_SYS_CONSOLE_INFO_QUIET
184 #ifdef CONFIG_CMD_NET
185 #define CONFIG_DRIVER_TI_CPSW
186 #define CONFIG_PHY_GIGE
193 #define CONFIG_NAND_OMAP_GPMC
194 #ifndef CONFIG_SPL_BUILD
195 #define CONFIG_SYS_GPMC_PREFETCH_ENABLE
197 #define GPMC_NAND_ECC_LP_x8_LAYOUT
198 #define GPMC_NAND_HW_ECC_LAYOUT_KERNEL GPMC_NAND_HW_ECC_LAYOUT
199 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
200 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
201 #define CONFIG_SYS_NAND_OOBSIZE 64
202 #define CONFIG_SYS_NAND_ECCSIZE 512
203 #define CONFIG_SYS_NAND_ECCBYTES 14
204 #define CONFIG_SYS_NAND_MAX_CHIPS 0x1
205 #define CONFIG_SYS_NAND_MAXBAD 20 /* Max. number of bad blocks guaranteed by manufacturer */
206 #define CONFIG_SYS_MAX_NAND_DEVICE 0x1
207 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
208 #ifdef CONFIG_ENV_IS_IN_NAND
209 #define CONFIG_ENV_OVERWRITE
210 #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
211 #define CONFIG_ENV_SIZE SZ_128K
212 #define CONFIG_ENV_RANGE 0x60000
213 #endif /* CONFIG_ENV_IS_IN_NAND */
214 #define CONFIG_SYS_NAND_BASE 0x00100000
215 #define CONFIG_SYS_NAND_SIZE SZ_128M
216 #define NAND_BASE CONFIG_SYS_NAND_BASE
217 #endif /* CONFIG_CMD_NAND */
222 #ifdef CONFIG_CMD_MMC
223 #define CONFIG_CMD_FAT
224 #define CONFIG_FAT_WRITE
225 #define CONFIG_CMD_EXT2
228 * Environments on MMC
230 #ifdef CONFIG_ENV_IS_IN_MMC
231 #define CONFIG_SYS_MMC_ENV_DEV 0
232 #define CONFIG_ENV_OVERWRITE
233 /* Associated with the MMC layout defined in mmcops.c */
234 #define CONFIG_ENV_OFFSET SZ_1K
235 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
236 #define CONFIG_DYNAMIC_MMC_DEVNO
237 #endif /* CONFIG_ENV_IS_IN_MMC */
238 #endif /* CONFIG_CMD_MMC */
240 #ifdef CONFIG_ENV_IS_NOWHERE
241 #define CONFIG_ENV_SIZE SZ_4K
244 #ifdef CONFIG_ENV_OFFSET_REDUND
245 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
246 "128k(u-boot-spl)," \
248 xstr(CONFIG_ENV_RANGE) \
250 xstr(CONFIG_ENV_RANGE) \
251 "(env2),6m(linux),32m(rootfs),89216k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
253 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
254 "128k(u-boot-spl)," \
256 xstr(CONFIG_ENV_RANGE) \
257 "(env),6m(linux),32m(rootfs),89600k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
260 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
261 #define SRAM0_SIZE SZ_64K
262 #define OCMC_SRAM_BASE 0x40300000
263 #define CONFIG_SPL_STACK (OCMC_SRAM_BASE + 0xb800)
264 #define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + SZ_32K)
266 /* Platform/Board specific defs */
267 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
268 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
270 /* Defines for SPL */
271 #define CONFIG_SPL_FRAMEWORK
272 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
273 #define CONFIG_SPL_GPIO_SUPPORT
274 #ifdef CONFIG_NAND_OMAP_GPMC
275 #define CONFIG_SPL_NAND_SUPPORT
276 #define CONFIG_SPL_NAND_DRIVERS
277 #define CONFIG_SPL_NAND_BASE
278 #define CONFIG_SPL_NAND_ECC
279 #define CONFIG_SPL_NAND_AM33XX_BCH
280 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
281 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
282 CONFIG_SYS_NAND_PAGE_SIZE)
283 #define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K
284 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
285 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
286 10, 11, 12, 13, 14, 15, 16, 17, \
287 18, 19, 20, 21, 22, 23, 24, 25, \
288 26, 27, 28, 29, 30, 31, 32, 33, \
289 34, 35, 36, 37, 38, 39, 40, 41, \
290 42, 43, 44, 45, 46, 47, 48, 49, \
291 50, 51, 52, 53, 54, 55, 56, 57, }
294 #define CONFIG_SPL_BSS_START_ADDR PHYS_SDRAM_1
295 #define CONFIG_SPL_BSS_MAX_SIZE SZ_512K
297 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
299 #define CONFIG_SPL_LIBCOMMON_SUPPORT
300 #define CONFIG_SPL_LIBGENERIC_SUPPORT
301 #define CONFIG_SPL_SERIAL_SUPPORT
302 #define CONFIG_SPL_YMODEM_SUPPORT
303 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
306 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
307 * 64 bytes before this address should be set aside for u-boot.img's
308 * header. That is 0x800FFFC0--0x80100000 should not be used for any
311 #define CONFIG_SYS_SPL_MALLOC_START (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
312 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M
314 #endif /* __CONFIG_H */