2 * Copyright (C) 2012 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #define CONFIG_MX51 /* must be set before including imx-regs.h */
13 #include <asm/sizes.h>
14 #include <asm/arch/imx-regs.h>
17 * Ka-Ro TX51 board - SoC configuration
19 #define CONFIG_SYS_MX5_IOMUX_V3
20 #define CONFIG_MXC_GPIO /* GPIO control */
21 #define CONFIG_SYS_MX5_HCLK 24000000
22 #define CONFIG_SYS_DDR_CLKSEL 0
23 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
24 #define CONFIG_SHOW_ACTIVITY
25 #define CONFIG_DISPLAY_BOARDINFO
26 #define CONFIG_BOARD_LATE_INIT
27 #define CONFIG_BOARD_EARLY_INIT_F
29 #if CONFIG_SYS_CPU_CLK == 600
30 #define TX51_MOD_PREFIX "6"
31 #elif CONFIG_SYS_CPU_CLK == 800
32 #define TX51_MOD_PREFIX "8"
33 #define CONFIG_MX51_PLL_ERRATA
35 #error Invalid CPU clock
38 /* LCD Logo and Splash screen support */
41 #define CONFIG_SPLASH_SCREEN
42 #define CONFIG_SPLASH_SCREEN_ALIGN
43 #define CONFIG_VIDEO_IPUV3
44 #define CONFIG_IPUV3_CLK 200000000
45 #define CONFIG_LCD_LOGO
46 #define LCD_BPP LCD_COLOR24
47 #define CONFIG_CMD_BMP
48 #define CONFIG_VIDEO_BMP_RLE8
49 #endif /* CONFIG_LCD */
52 * Memory configurations
54 #ifndef CONFIG_SYS_SDRAM_CLK
55 #define CONFIG_SYS_SDRAM_CLK 166
57 #define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */
58 #define PHYS_SDRAM_1_SIZE SZ_128M
59 #if CONFIG_NR_DRAM_BANKS > 1
60 #define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */
61 #define PHYS_SDRAM_2_SIZE SZ_128M
63 #define TX51_MOD_SUFFIX "0"
65 #define CONFIG_STACKSIZE SZ_128K
66 #define CONFIG_SYS_MALLOC_LEN SZ_8M
67 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
68 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
69 #if CONFIG_SYS_SDRAM_CLK == 200
70 #define CONFIG_SYS_CLKTL_CBCDR 0x59e35180
71 #define TX51_MOD_SUFFIX "1"
72 #elif CONFIG_SYS_SDRAM_CLK == 166
73 #define CONFIG_SYS_CLKTL_CBCDR 0x01e35180
74 #ifndef TX51_MOD_SUFFIX
75 #define TX51_MOD_SUFFIX "2"
78 #error Invalid SDRAM clock
82 * U-Boot general configurations
84 #define CONFIG_SYS_LONGHELP
85 #define CONFIG_SYS_PROMPT "TX51 U-Boot > "
86 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
87 #define CONFIG_SYS_PBSIZE \
88 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
89 /* Print buffer size */
90 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
91 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
92 /* Boot argument buffer size */
93 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
94 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
95 #define CONFIG_CMDLINE_EDITING /* Command history etc */
97 #define CONFIG_SYS_64BIT_VSPRINTF
98 #define CONFIG_SYS_NO_FLASH
101 * Flattened Device Tree (FDT) support
103 #define CONFIG_OF_LIBFDT
104 #define CONFIG_OF_BOARD_SETUP
105 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
110 #define xstr(s) str(s)
112 #define __pfx(x, s) (x##s)
113 #define _pfx(x, s) __pfx(x, s)
115 #define CONFIG_CMDLINE_TAG
116 #define CONFIG_SETUP_MEMORY_TAGS
117 #define CONFIG_BOOTDELAY 3
118 #define CONFIG_ZERO_BOOTDELAY_CHECK
119 #define CONFIG_SYS_AUTOLOAD "no"
120 #define CONFIG_BOOTFILE "uImage"
121 #define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
122 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
123 #define CONFIG_LOADADDR 94000000
124 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
125 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
126 #define CONFIG_HW_WATCHDOG
131 #define CONFIG_EXTRA_ENV_SETTINGS \
133 "baseboard=stk5-v3\0" \
134 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
135 " root=/dev/mmcblk0p3 rootwait\0" \
136 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
137 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
138 "nfsroot=/tftpboot/rootfs\0" \
139 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
140 " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
141 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
142 "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
143 "bootcmd_nand=set autostart no;run bootargs_nand;" \
144 "nboot linux;run bootm_cmd\0" \
145 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
147 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
148 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
149 " ${append_bootargs}\0" \
150 "cpu_clk=" xstr(CONFIG_SYS_CPU_CLK) "\0" \
151 "fdtaddr=91000000\0" \
152 "fdtsave=nand erase.part dtb;nand write ${fdtaddr} dtb ${fdtsize}\0" \
153 "mtdids=" MTDIDS_DEFAULT "\0" \
154 "mtdparts=" MTDPARTS_DEFAULT "\0" \
155 "otg_mode=device\0" \
156 "touchpanel=tsc2007\0" \
159 #define MTD_NAME "mxc_nand"
160 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
161 #define CONFIG_FDT_FIXUP_PARTITIONS
166 #include <config_cmd_default.h>
167 #define CONFIG_CMD_CACHE
168 #define CONFIG_CMD_MMC
169 #define CONFIG_CMD_NAND
170 #define CONFIG_CMD_MTDPARTS
171 #define CONFIG_CMD_BOOTCE
172 #define CONFIG_CMD_TIME
173 #define CONFIG_CMD_MEMTEST
178 #define CONFIG_MXC_UART
179 #define CONFIG_MXC_UART_BASE UART1_BASE
180 #define CONFIG_MXC_GPIO
181 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
182 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
183 #define CONFIG_SYS_CONSOLE_INFO_QUIET
188 #define CONFIG_FEC_MXC
189 #ifdef CONFIG_FEC_MXC
190 #define IMX_FEC_BASE FEC_BASE_ADDR
191 #define CONFIG_FEC_MXC_PHYADDR 0x1f
192 #define CONFIG_PHYLIB
193 #define CONFIG_PHY_SMSC
195 #define CONFIG_FEC_XCV_TYPE MII100
196 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
197 #define CONFIG_CMD_MII
198 #define CONFIG_CMD_DHCP
199 #define CONFIG_CMD_PING
200 /* Add for working with "strict" DHCP server */
201 #define CONFIG_BOOTP_SUBNETMASK
202 #define CONFIG_BOOTP_GATEWAY
203 #define CONFIG_BOOTP_DNS
209 #ifdef CONFIG_CMD_NAND
210 #define CONFIG_MTD_DEVICE
211 #define CONFIG_ENV_IS_IN_NAND
212 #define CONFIG_NAND_MXC
213 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
214 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
215 #define CONFIG_MXC_NAND_HWECC
216 #define CONFIG_CMD_NAND_TRIMFFS
217 #define CONFIG_SYS_MAX_FLASH_SECT 1024
218 #define CONFIG_SYS_MAX_FLASH_BANKS 1
219 #define CONFIG_SYS_NAND_MAX_CHIPS 1
220 #define CONFIG_SYS_MAX_NAND_DEVICE 1
221 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
222 #define CONFIG_SYS_NAND_USE_FLASH_BBT
223 #ifdef CONFIG_ENV_IS_IN_NAND
224 #define CONFIG_ENV_OVERWRITE
225 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
226 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
227 #define CONFIG_ENV_RANGE 0x60000
229 #ifndef CONFIG_SYS_NO_FLASH
230 #define CONFIG_CMD_FLASH
231 #define CONFIG_SYS_NAND_BASE 0xa0000000
234 #define CONFIG_SYS_NAND_BASE 0x00000000
235 #define CONFIG_CMD_ROMUPDATE
237 #endif /* CONFIG_CMD_NAND */
242 #ifdef CONFIG_CMD_MMC
243 #ifndef CONFIG_ENV_IS_IN_NAND
244 #define CONFIG_ENV_IS_IN_MMC
247 #define CONFIG_GENERIC_MMC
248 #define CONFIG_FSL_ESDHC
249 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
251 #define CONFIG_DOS_PARTITION
252 #define CONFIG_CMD_FAT
253 #define CONFIG_CMD_EXT2
256 * Environments on MMC
258 #ifdef CONFIG_ENV_IS_IN_MMC
259 #define CONFIG_SYS_MMC_ENV_DEV 0
260 #define CONFIG_ENV_OVERWRITE
261 /* Associated with the MMC layout defined in mmcops.c */
262 #define CONFIG_ENV_OFFSET SZ_1K
263 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
264 #define CONFIG_DYNAMIC_MMC_DEVNO
265 #endif /* CONFIG_ENV_IS_IN_MMC */
266 #endif /* CONFIG_CMD_MMC */
268 #ifdef CONFIG_ENV_OFFSET_REDUND
269 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
271 xstr(CONFIG_ENV_RANGE) \
273 xstr(CONFIG_ENV_RANGE) \
274 "(env2),4m(linux),16m(rootfs),256k(dtb),?(userfs),512k@0x7f80000(bbt)ro"
276 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
278 xstr(CONFIG_ENV_RANGE) \
279 "(env),4m(linux),16m(rootfs),256k(dtb),?(userfs),512k@0x7f80000(bbt)ro"
282 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
283 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
284 GENERATED_GBL_DATA_SIZE)
286 #ifdef CONFIG_CMD_IIM
287 #define CONFIG_FSL_IIM
290 #endif /* __CONFIG_H */