2 * Copyright (C) 2012-2014 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #define CONFIG_MX53 /* must be set before including imx-regs.h */
13 #include <asm/sizes.h>
14 #include <asm/arch/imx-regs.h>
17 * Ka-Ro TX53 board - SoC configuration
19 #define CONFIG_TX53 /* TX53 SoM */
20 #define CONFIG_SYS_MX5_IOMUX_V3
21 #define CONFIG_MXC_GPIO /* GPIO control */
22 #define CONFIG_SYS_MX5_HCLK 24000000
23 #define CONFIG_SYS_DDR_CLKSEL 0
24 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
25 #define CONFIG_SHOW_ACTIVITY
26 #define CONFIG_DISPLAY_BOARDINFO
27 #define CONFIG_BOARD_LATE_INIT
28 #define CONFIG_BOARD_EARLY_INIT_F
30 /* LCD Logo and Splash screen support */
33 #define CONFIG_SPLASH_SCREEN
34 #define CONFIG_SPLASH_SCREEN_ALIGN
35 #define CONFIG_VIDEO_IPUV3
36 #define CONFIG_IPUV3_CLK 200000000
37 #define CONFIG_LCD_LOGO
38 #define LCD_BPP LCD_COLOR24
39 #define CONFIG_CMD_BMP
40 #define CONFIG_VIDEO_BMP_RLE8
41 #endif /* CONFIG_LCD */
44 * Memory configuration options
46 #ifndef CONFIG_SYS_SDRAM_SIZE
47 #define CONFIG_SYS_SDRAM_SIZE (SZ_512M * CONFIG_NR_DRAM_BANKS)
50 #define PHYS_SDRAM_1 0x70000000 /* Base address of bank 1 */
51 #define PHYS_SDRAM_1_SIZE (CONFIG_SYS_SDRAM_SIZE / CONFIG_NR_DRAM_BANKS)
52 #if CONFIG_NR_DRAM_BANKS > 1
53 #define PHYS_SDRAM_2 0xb0000000 /* Base address of bank 2 */
54 #define PHYS_SDRAM_2_SIZE PHYS_SDRAM_1_SIZE
56 #define CONFIG_STACKSIZE SZ_128K
57 #define CONFIG_SYS_MALLOC_LEN SZ_8M
58 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
59 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
60 #define CONFIG_SYS_SDRAM_CLK 400
63 * U-Boot general configurations
65 #define CONFIG_SYS_LONGHELP
66 #define CONFIG_SYS_PROMPT "TX53 U-Boot > "
67 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
68 #define CONFIG_SYS_PBSIZE \
69 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
70 /* Print buffer size */
71 #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
72 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
73 /* Boot argument buffer size */
74 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
75 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
76 #define CONFIG_CMDLINE_EDITING /* Command history etc */
78 #define CONFIG_SYS_64BIT_VSPRINTF
79 #define CONFIG_SYS_NO_FLASH
82 * Flattened Device Tree (FDT) support
84 #define CONFIG_OF_LIBFDT
85 #define CONFIG_OF_BOARD_SETUP
86 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
91 #define xstr(s) str(s)
93 #define __pfx(x, s) (x##s)
94 #define _pfx(x, s) __pfx(x, s)
96 #define CONFIG_CMDLINE_TAG
97 #define CONFIG_SETUP_MEMORY_TAGS
98 #define CONFIG_BOOTDELAY 3
99 #define CONFIG_ZERO_BOOTDELAY_CHECK
100 #define CONFIG_SYS_AUTOLOAD "no"
101 #define CONFIG_BOOTFILE "uImage"
102 #define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
103 #define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
104 #define CONFIG_LOADADDR 78000000
105 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
106 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
107 #define CONFIG_HW_WATCHDOG
108 #ifndef CONFIG_SYS_LVDS_IF
109 #define DEFAULT_VIDEO_MODE "VGA"
111 #define DEFAULT_VIDEO_MODE "HSD100PXN1"
115 * Extra Environment Settings
117 #define CONFIG_EXTRA_ENV_SETTINGS \
119 "baseboard=stk5-v3\0" \
120 "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \
121 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
122 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
123 " root=/dev/mmcblk0p2 rootwait\0" \
124 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
125 " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \
127 "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \
128 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
129 "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \
131 "bootcmd_mmc=set autostart no;run bootargs_mmc" \
132 ";fatload mmc 0 ${loadaddr} uImage\0" \
133 "bootcmd_nand=set autostart no;run bootargs_ubifs" \
135 "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \
137 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
140 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
141 " ${append_bootargs}\0" \
142 "fdtaddr=71000000\0" \
143 "fdtsave=fdt resize;nand erase.part dtb" \
144 ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
145 "mtdids=" MTDIDS_DEFAULT "\0" \
146 "mtdparts=" MTDPARTS_DEFAULT "\0" \
147 "nfsroot=/tftpboot/rootfs\0" \
148 "otg_mode=device\0" \
149 "touchpanel=tsc2007\0" \
150 "video_mode=" DEFAULT_VIDEO_MODE "\0"
152 #define MTD_NAME "mxc_nand"
153 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
154 #define CONFIG_FDT_FIXUP_PARTITIONS
159 #include <config_cmd_default.h>
160 #define CONFIG_CMD_CACHE
161 #define CONFIG_CMD_MMC
162 #define CONFIG_CMD_NAND
163 #define CONFIG_CMD_MTDPARTS
164 #define CONFIG_CMD_BOOTCE
165 #define CONFIG_CMD_TIME
166 #define CONFIG_CMD_I2C
167 #define CONFIG_CMD_MEMTEST
172 #define CONFIG_MXC_UART
173 #define CONFIG_MXC_UART_BASE UART1_BASE
174 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
175 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
176 #define CONFIG_SYS_CONSOLE_INFO_QUIET
181 #define CONFIG_MXC_GPIO
186 #define CONFIG_FEC_MXC
187 #ifdef CONFIG_FEC_MXC
188 #define IMX_FEC_BASE FEC_BASE_ADDR
189 #define CONFIG_FEC_MXC_PHYADDR 0
190 #define CONFIG_PHYLIB
191 #define CONFIG_PHY_SMSC
193 #define CONFIG_FEC_XCV_TYPE MII100
194 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
195 #define CONFIG_CMD_MII
196 #define CONFIG_CMD_DHCP
197 #define CONFIG_CMD_PING
198 /* Add for working with "strict" DHCP server */
199 #define CONFIG_BOOTP_SUBNETMASK
200 #define CONFIG_BOOTP_GATEWAY
201 #define CONFIG_BOOTP_DNS
207 #ifdef CONFIG_CMD_I2C
208 #define CONFIG_HARD_I2C
209 #define CONFIG_I2C_MXC
210 #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
211 #define CONFIG_SYS_I2C_MX6_PORT1
212 #define CONFIG_SYS_I2C_SPEED 400000
213 #define CONFIG_SYS_I2C_SLAVE 0x34
219 #ifdef CONFIG_CMD_NAND
220 #define CONFIG_MTD_DEVICE
221 #define CONFIG_ENV_IS_IN_NAND
222 #define CONFIG_NAND_MXC
223 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
224 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
225 #define CONFIG_MXC_NAND_HWECC
226 #define CONFIG_CMD_NAND_TRIMFFS
227 #define CONFIG_SYS_NAND_MAX_CHIPS 1
228 #define CONFIG_SYS_MAX_NAND_DEVICE 1
229 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
230 #define CONFIG_SYS_NAND_USE_FLASH_BBT
231 #ifdef CONFIG_ENV_IS_IN_NAND
232 #define CONFIG_ENV_OVERWRITE
233 #define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
234 #define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
235 #define CONFIG_ENV_RANGE 0x60000
237 #define CONFIG_SYS_NAND_BASE 0x00000000
238 #define CONFIG_CMD_ROMUPDATE
239 #endif /* CONFIG_CMD_NAND */
244 #ifdef CONFIG_CMD_MMC
245 #ifndef CONFIG_ENV_IS_IN_NAND
246 #define CONFIG_ENV_IS_IN_MMC
249 #define CONFIG_GENERIC_MMC
250 #define CONFIG_FSL_ESDHC
251 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
253 #define CONFIG_DOS_PARTITION
254 #define CONFIG_CMD_FAT
255 #define CONFIG_FAT_WRITE
256 #define CONFIG_CMD_EXT2
259 * Environments on MMC
261 #ifdef CONFIG_ENV_IS_IN_MMC
262 #define CONFIG_SYS_MMC_ENV_DEV 0
263 #define CONFIG_ENV_OVERWRITE
264 /* Associated with the MMC layout defined in mmcops.c */
265 #define CONFIG_ENV_OFFSET SZ_1K
266 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
267 #define CONFIG_DYNAMIC_MMC_DEVNO
268 #endif /* CONFIG_ENV_IS_IN_MMC */
269 #endif /* CONFIG_CMD_MMC */
271 #ifdef CONFIG_ENV_OFFSET_REDUND
272 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
274 xstr(CONFIG_ENV_RANGE) \
276 xstr(CONFIG_ENV_RANGE) \
277 "(env2),6m(linux),32m(rootfs),89344k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
279 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
281 xstr(CONFIG_ENV_RANGE) \
282 "(env),6m(linux),32m(rootfs),89728k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
285 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
286 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
287 GENERATED_GBL_DATA_SIZE)
289 #ifdef CONFIG_CMD_IIM
290 #define CONFIG_FSL_IIM
293 #endif /* __CONFIG_H */