2 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
5 * See file CREDITS for list of people who contributed to this project.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * High Level Configuration Options
29 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
30 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
31 #define CONFIG_V38B 1 /* ...on V38B board */
32 #define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
34 #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
35 #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
37 #undef CONFIG_HW_WATCHDOG /* don't use watchdog */
39 #define CONFIG_NETCONSOLE 1
41 #define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
43 #define CFG_XLB_PIPELINING 1 /* gives better performance */
45 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
46 #define BOOTFLAG_WARM 0x02 /* Software reboot */
48 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
49 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
50 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
54 * Serial console configuration
56 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
57 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
58 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
63 #define SDRAM_DDR 1 /* is DDR */
64 /* Settings for XLB = 132 MHz */
65 #define SDRAM_MODE 0x018D0000
66 #define SDRAM_EMODE 0x40090000
67 #define SDRAM_CONTROL 0x704f0f00
68 #define SDRAM_CONFIG1 0x73722930
69 #define SDRAM_CONFIG2 0x47770000
70 #define SDRAM_TAPDELAY 0x10000000
80 #define CONFIG_MAC_PARTITION 1
81 #define CONFIG_DOS_PARTITION 1
86 #define CONFIG_USB_OHCI
87 #define CONFIG_USB_STORAGE
88 #define CONFIG_USB_CLOCK 0x0001BBBB
89 #define CONFIG_USB_CONFIG 0x00001000
94 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
109 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
111 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
112 #include <cmd_confdefs.h>
115 * Boot low with 16 MB Flash
117 #define CFG_LOWBOOT 1
118 #define CFG_LOWBOOT16 1
123 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
125 #define CONFIG_PREBOOT "echo;" \
126 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
129 #undef CONFIG_BOOTARGS
131 #define CONFIG_EXTRA_ENV_SETTINGS \
132 "bootcmd=run net_nfs\0" \
134 "baudrate=115200\0" \
135 "preboot=echo;echo Type \"run flash_nfs\" to mount root " \
136 "filesystem over NFS; echo\0" \
138 "ramargs=setenv bootargs root=/dev/ram rw\0" \
139 "addip=setenv bootargs $(bootargs) " \
140 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
141 "$(netmask):$(hostname):$(netdev):off panic=1\0" \
142 "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
143 "flash_self=run ramargs addip;bootm $(kernel_addr) " \
144 "$(ramdisk_addr)\0" \
145 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
146 "nfsargs=setenv bootargs root=/dev/nfs rw " \
147 "nfsroot=$(serverip):$(rootpath)\0" \
149 "ethact=FEC ETHERNET\0" \
150 "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
151 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
152 "cp.b 200000 ff000000 $(filesize);" \
153 "prot on ff000000 ff03ffff\0" \
154 "load=tftp 200000 $(u-boot)\0" \
155 "netmask=255.255.0.0\0" \
156 "ipaddr=192.168.160.18\0" \
157 "serverip=192.168.1.1\0" \
158 "ethaddr=00:e0:ee:00:05:2e\0" \
159 "bootfile=/tftpboot/v38b/uImage\0" \
160 "u-boot=/tftpboot/v38b/u-boot.bin\0" \
163 #define CONFIG_BOOTCOMMAND "run net_nfs"
165 #if defined(CONFIG_MPC5200)
167 * IPB Bus clocking configuration.
169 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
175 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
176 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
177 #define CFG_I2C_SPEED 100000 /* 100 kHz */
178 #define CFG_I2C_SLAVE 0x7F
181 * EEPROM configuration
183 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
184 #define CFG_I2C_EEPROM_ADDR_LEN 1
185 #define CFG_EEPROM_PAGE_WRITE_BITS 3
186 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
191 #define CFG_I2C_RTC_ADDR 0x51
194 * Flash configuration - use CFI driver
196 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
197 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
198 #define CFG_FLASH_CFI_AMD_RESET 1
199 #define CFG_FLASH_BASE 0xFF000000
200 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
201 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
202 #define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */
203 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
204 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
207 * Environment settings
209 #define CFG_ENV_IS_IN_FLASH 1
210 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
211 #define CFG_ENV_SIZE 0x10000
212 #define CFG_ENV_SECT_SIZE 0x10000
213 #define CONFIG_ENV_OVERWRITE 1
218 #define CFG_MBAR 0xF0000000
219 #define CFG_SDRAM_BASE 0x00000000
220 #define CFG_DEFAULT_MBAR 0x80000000
222 /* Use SRAM until RAM will be available */
223 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
224 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
226 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
227 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
228 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
230 #define CFG_MONITOR_BASE TEXT_BASE
231 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
232 # define CFG_RAMBOOT 1
235 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
236 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
237 #define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
240 * Ethernet configuration
242 #define CONFIG_MPC5xxx_FEC 1
243 #define CONFIG_PHY_ADDR 0x00
249 #define CFG_GPS_PORT_CONFIG 0x90001404
252 * Miscellaneous configurable options
254 #define CFG_LONGHELP /* undef to save memory */
255 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
256 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
257 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
259 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
261 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
262 #define CFG_MAXARGS 16 /* max number of command args */
263 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
265 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
266 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
268 #define CFG_LOAD_ADDR 0x100000 /* default load address */
270 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
273 * Various low-level settings
275 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
276 #define CFG_HID0_FINAL HID0_ICE
278 #define CFG_BOOTCS_START CFG_FLASH_BASE
279 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
280 #define CFG_BOOTCS_CFG 0x00047801
281 #define CFG_CS0_START CFG_FLASH_BASE
282 #define CFG_CS0_SIZE CFG_FLASH_SIZE
284 #define CFG_CS_BURST 0x00000000
285 #define CFG_CS_DEADCYCLE 0x33333333
287 #define CFG_RESET_ADDRESS 0xff000000
290 * IDE/ATA (supports IDE harddisk)
292 #undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
293 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
294 #undef CONFIG_IDE_LED /* LED for ide not supported */
296 #define CONFIG_IDE_RESET /* reset for ide supported */
297 #define CONFIG_IDE_PREINIT
299 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
300 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
302 #define CFG_ATA_IDE0_OFFSET 0x0000
304 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
306 #define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
308 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */
310 #define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
312 #define CFG_ATA_STRIDE 4 /* Interval between registers */
317 #define CONFIG_STATUS_LED /* Status LED enabled */
318 #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
320 #define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
322 typedef unsigned int led_id_t;
324 #define __led_toggle(_msk) \
326 *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
329 #define __led_set(_msk, _st) \
332 *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
334 *((volatile long *) (CFG_LED_BASE)) |= (_msk); \
337 #define __led_init(_msk, st) \
339 *((volatile long *) (CFG_LED_BASE)) |= 0x34; \
341 #endif /* __ASSEMBLY__ */
343 #endif /* __CONFIG_H */