2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * Configuration settings for the MX51-3Stack Freescale board.
8 * SPDX-License-Identifier: GPL-2.0+
15 #define CONFIG_SYS_TEXT_BASE 0x97800000
17 #include <asm/arch/imx-regs.h>
19 #define CONFIG_DISPLAY_CPUINFO
20 #define CONFIG_DISPLAY_BOARDINFO
22 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23 #define CONFIG_SETUP_MEMORY_TAGS
24 #define CONFIG_INITRD_TAG
25 #define CONFIG_BOARD_LATE_INIT
27 #ifndef MACH_TYPE_TTC_VISION2
28 #define MACH_TYPE_TTC_VISION2 2775
30 #define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
33 * Size of malloc() pool
35 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
40 #define CONFIG_MXC_UART
41 #define CONFIG_MXC_UART_BASE UART3_BASE
42 #define CONFIG_MXC_GPIO
43 #define CONFIG_MXC_SPI
44 #define CONFIG_HW_WATCHDOG
52 #define CONFIG_SPI_FLASH_STMICRO
55 * Use gpio 4 pin 25 as chip select for SPI flash
56 * This corresponds to gpio 121
58 #define CONFIG_SF_DEFAULT_CS 1
59 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
60 #define CONFIG_SF_DEFAULT_SPEED 25000000
62 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
63 #define CONFIG_ENV_SPI_BUS 0
64 #define CONFIG_ENV_SPI_MAX_HZ 25000000
65 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
67 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
68 #define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
69 #define CONFIG_ENV_SIZE (4 * 1024)
71 #define CONFIG_FSL_ENV_IN_SF
72 #define CONFIG_ENV_IS_IN_SPI_FLASH
76 #define CONFIG_POWER_SPI
77 #define CONFIG_POWER_FSL
78 #define CONFIG_FSL_PMIC_BUS 0
79 #define CONFIG_FSL_PMIC_CS 0
80 #define CONFIG_FSL_PMIC_CLK 2500000
81 #define CONFIG_FSL_PMIC_MODE SPI_MODE_0
82 #define CONFIG_FSL_PMIC_BITLEN 32
83 #define CONFIG_RTC_MC13XXX
88 #define CONFIG_FSL_ESDHC
89 #ifdef CONFIG_FSL_ESDHC
90 #define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
91 #define CONFIG_SYS_FSL_ESDHC_NUM 1
95 #define CONFIG_CMD_MMC
96 #define CONFIG_GENERIC_MMC
97 #define CONFIG_CMD_FAT
98 #define CONFIG_DOS_PARTITION
101 #define CONFIG_CMD_DATE
106 #define CONFIG_HAS_ETH1
109 #define CONFIG_FEC_MXC
110 #define IMX_FEC_BASE FEC_BASE_ADDR
111 #define CONFIG_FEC_MXC_PHYADDR 0x1F
113 #define CONFIG_CMD_PING
114 #define CONFIG_CMD_MII
116 /* allow to overwrite serial and ethaddr */
117 #define CONFIG_ENV_OVERWRITE
118 #define CONFIG_CONS_INDEX 3
119 #define CONFIG_BAUDRATE 115200
121 /***********************************************************
123 ***********************************************************/
125 #define CONFIG_CMD_SPI
127 #define CONFIG_BOOTDELAY 3
129 #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
131 #define CONFIG_EXTRA_ENV_SETTINGS \
133 "loadaddr=0x90800000\0"
136 * Miscellaneous configurable options
138 #define CONFIG_SYS_LONGHELP
139 #define CONFIG_SYS_PROMPT "Vision II U-boot > "
140 #define CONFIG_AUTO_COMPLETE
141 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
143 /* Print Buffer Size */
144 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
145 sizeof(CONFIG_SYS_PROMPT) + 16)
146 #define CONFIG_SYS_MAXARGS 64 /* max number of command args */
147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
149 #define CONFIG_SYS_MEMTEST_START 0x90000000
150 #define CONFIG_SYS_MEMTEST_END 0x10000
152 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
154 #define CONFIG_CMDLINE_EDITING
155 #define CONFIG_SYS_HUSH_PARSER
158 * Physical Memory Map
160 #define CONFIG_NR_DRAM_BANKS 2
161 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
162 #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
163 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
164 #define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
165 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
166 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
167 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
169 #define CONFIG_SYS_INIT_SP_OFFSET \
170 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
171 #define CONFIG_SYS_INIT_SP_ADDR \
172 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
174 #define CONFIG_BOARD_EARLY_INIT_F
176 /* 166 MHz DDR RAM */
177 #define CONFIG_SYS_DDR_CLKSEL 0
178 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100
179 #define CONFIG_SYS_MAIN_PWR_ON
181 #define CONFIG_SYS_NO_FLASH
184 * Framebuffer and LCD
186 #define CONFIG_PREBOOT
188 #define CONFIG_VIDEO_IPUV3
189 #define CONFIG_CFB_CONSOLE
190 #define CONFIG_VGA_AS_SINGLE_DEVICE
191 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
192 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
193 #define CONFIG_VIDEO_BMP_RLE8
194 #define CONFIG_SPLASH_SCREEN
195 #define CONFIG_CMD_BMP
196 #define CONFIG_BMP_16BPP
197 #define CONFIG_IPUV3_CLK 133000000
199 #endif /* __CONFIG_H */