5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
9 * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/types.h>
18 #include <linux/list.h>
23 #define IDMA_CHAN_INVALID 0xFF
24 #define HIGH_RESOLUTION_WIDTH 1024
27 * Enumeration of Synchronous (Memory-less) panel types
34 /* IPU Pixel format definitions */
35 #define fourcc(a, b, c, d)\
36 (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
39 * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
40 * the same used by V4L2 API.
43 #define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
44 #define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
45 #define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
46 #define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
48 #define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
49 #define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
50 #define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
51 #define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
52 #define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
53 #define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
54 #define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */
55 #define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */
56 #define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */
57 #define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */
58 #define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */
59 #define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */
61 /* YUV Interleaved Formats */
62 #define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */
63 #define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */
64 #define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */
65 #define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */
67 /* two planes -- one Y, one Cb + Cr interleaved */
68 #define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
70 #define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */
71 #define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */
72 #define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */
73 #define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */
74 #define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */
75 #define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */
76 #define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
77 #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
80 * IPU Driver channels definitions.
81 * Note these are different from IDMA channels
84 #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
85 ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
86 #define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
87 #define IPU_CHAN_ID(ch) (ch >> 24)
88 #define IPU_CHAN_ALT(ch) (ch & 0x02000000)
89 #define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
90 #define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
91 #define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
92 #define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
97 * Enumeration of IPU logical channels. An IPU logical channel is defined as a
98 * combination of an input (memory to IPU), output (IPU to memory), and/or
99 * secondary input IDMA channels and in some cases an Image Converter task.
100 * Some channels consist of only an input or output.
105 MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
106 MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
107 MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
108 MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
110 MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
111 MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
112 MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
113 MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
115 DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
116 DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
121 * Enumeration of types of buffers for a logical channel.
124 IPU_OUTPUT_BUFFER = 0, /* Buffer for output from IPU */
125 IPU_ALPHA_IN_BUFFER = 1, /* Buffer for input to IPU */
126 IPU_GRAPH_IN_BUFFER = 2, /* Buffer for input to IPU */
127 IPU_VIDEO_IN_BUFFER = 3, /* Buffer for input to IPU */
128 IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
129 IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
134 * Enumeration of version of IPU V3 .
137 IPUV3_HW_REV_IPUV3DEX = 2, /* IPUv3D, IPUv3E IPUv3EX */
138 IPUV3_HW_REV_IPUV3M = 3, /* IPUv3M */
139 IPUV3_HW_REV_IPUV3H = 4, /* IPUv3H */
143 #define IPU_PANEL_SERIAL 1
144 #define IPU_PANEL_PARALLEL 2
155 DMFC_HIGH_RESOLUTION_DC,
156 DMFC_HIGH_RESOLUTION_DP,
157 DMFC_HIGH_RESOLUTION_ONLY_DP,
162 * Union of initialization parameters for a logical channel.
167 unsigned char interlaced;
174 unsigned char interlaced;
175 uint32_t in_pixel_fmt;
176 uint32_t out_pixel_fmt;
177 unsigned char alpha_chan_en;
184 unsigned char interlaced;
185 uint32_t in_pixel_fmt;
186 uint32_t out_pixel_fmt;
187 unsigned char alpha_chan_en;
189 } ipu_channel_params_t;
192 * Enumeration of IPU interrupts.
195 IPU_IRQ_DP_SF_END = 448 + 3,
196 IPU_IRQ_DC_FC_1 = 448 + 9,
200 * Bitfield of Display Interface signal polarities.
203 unsigned datamask_en:1;
205 unsigned interlaced:1;
206 unsigned odd_field_first:1;
207 unsigned clksel_en:1;
208 unsigned clkidle_en:1;
209 unsigned data_pol:1; /* true = inverted */
210 unsigned clk_pol:1; /* true = rising edge */
211 unsigned enable_pol:1;
212 unsigned Hsync_pol:1; /* true = active high */
213 unsigned Vsync_pol:1;
214 } ipu_di_signal_cfg_t;
226 } ipu_di_clk_parent_t;
229 int ipuv3_fb_init(struct fb_videomode *mode, int di,
230 unsigned int interface_pix_fmt,
231 ipu_di_clk_parent_t di_clk_parent,
232 unsigned long di_clk_val, int bpp);
233 void ipuv3_fb_shutdown(void);
235 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
236 void ipu_uninit_channel(ipu_channel_t channel);
238 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
240 uint16_t width, uint16_t height,
242 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
243 uint32_t u_offset, uint32_t v_offset);
245 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
246 uint32_t bufNum, dma_addr_t phyaddr);
248 int32_t ipu_is_channel_busy(ipu_channel_t channel);
249 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
251 int32_t ipu_enable_channel(ipu_channel_t channel);
252 int32_t ipu_disable_channel(ipu_channel_t channel);
254 int32_t ipu_init_sync_panel(int disp,
256 uint16_t width, uint16_t height,
258 uint16_t h_start_width, uint16_t h_sync_width,
259 uint16_t h_end_width, uint16_t v_start_width,
260 uint16_t v_sync_width, uint16_t v_end_width,
261 uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
263 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
265 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
268 uint32_t bytes_per_pixel(uint32_t fmt);
270 int clk_enable(struct clk *clk);
271 void clk_disable(struct clk *clk);
272 u32 clk_get_rate(struct clk *clk);
273 int clk_set_rate(struct clk *clk, unsigned long rate);
274 long clk_round_rate(struct clk *clk, unsigned long rate);
275 int clk_set_parent(struct clk *clk, struct clk *parent);
276 int clk_get_usecount(struct clk *clk);
277 struct clk *clk_get_parent(struct clk *clk);
279 void ipu_dump_registers(void);
280 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val);
282 void ipu_dmfc_init(int dmfc_type, int first);
283 void ipu_init_dc_mappings(void);
284 void ipu_dmfc_set_wait4eot(int dma_chan, int width);
285 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
286 void ipu_dc_uninit(int dc_chan);
287 void ipu_dp_dc_enable(ipu_channel_t channel);
288 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
289 uint32_t out_pixel_fmt);
290 void ipu_dp_uninit(ipu_channel_t channel);
291 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
292 ipu_color_space_t format_to_colorspace(uint32_t fmt);