2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 #ifndef __KVM_ARM_VGIC_H
17 #define __KVM_ARM_VGIC_H
19 #include <linux/kernel.h>
20 #include <linux/kvm.h>
21 #include <linux/irqreturn.h>
22 #include <linux/spinlock.h>
23 #include <linux/types.h>
24 #include <kvm/iodev.h>
26 #define VGIC_V3_MAX_CPUS 255
27 #define VGIC_V2_MAX_CPUS 8
28 #define VGIC_NR_IRQS_LEGACY 256
29 #define VGIC_NR_SGIS 16
30 #define VGIC_NR_PPIS 16
31 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
32 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
33 #define VGIC_MAX_SPI 1019
34 #define VGIC_MAX_RESERVED 1023
35 #define VGIC_MIN_LPI 8192
38 VGIC_V2, /* Good ol' GICv2 */
39 VGIC_V3, /* New fancy GICv3 */
42 /* same for all guests, as depending only on the _host's_ GIC model */
44 /* type of the host GIC */
47 /* Physical address of vgic virtual cpu interface */
48 phys_addr_t vcpu_base;
50 /* virtual control interface mapping */
51 void __iomem *vctrl_base;
53 /* Number of implemented list registers */
56 /* Maintenance IRQ number */
57 unsigned int maint_irq;
59 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
62 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
63 bool can_emulate_gicv2;
66 extern struct vgic_global kvm_vgic_global_state;
68 #define VGIC_V2_MAX_LRS (1 << 6)
69 #define VGIC_V3_MAX_LRS 16
70 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
72 enum vgic_irq_config {
78 spinlock_t irq_lock; /* Protects the content of the struct */
79 struct list_head ap_list;
81 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
82 * SPIs and LPIs: The VCPU whose ap_list
86 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should
87 * be sent to, as a result of the
88 * targets reg (v2) or the
92 u32 intid; /* Guest visible INTID */
94 bool line_level; /* Level only */
95 bool soft_pending; /* Level only */
96 bool active; /* not used for LPIs */
98 bool hw; /* Tied to HW IRQ */
99 struct kref refcount; /* Used for LPIs */
100 u32 hwintid; /* HW INTID number */
102 u8 targets; /* GICv2 target VCPUs mask */
103 u32 mpidr; /* GICv3 target VCPU */
105 u8 source; /* GICv2 SGIs only */
107 enum vgic_irq_config config; /* Level or edge */
110 struct vgic_register_region;
112 struct vgic_io_device {
114 struct kvm_vcpu *redist_vcpu;
115 const struct vgic_register_region *regions;
117 struct kvm_io_device dev;
125 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
130 /* TODO: Consider moving to global state */
131 /* Virtual control interface mapping */
132 void __iomem *vctrl_base;
134 /* base addresses in guest physical address space: */
135 gpa_t vgic_dist_base; /* distributor */
137 /* either a GICv2 CPU interface */
139 /* or a number of GICv3 redistributor regions */
140 gpa_t vgic_redist_base;
143 /* distributor enabled */
146 struct vgic_irq *spis;
148 struct vgic_io_device dist_iodev;
151 * Contains the attributes and gpa of the LPI configuration table.
152 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
153 * one address across all redistributors.
154 * GICv3 spec: 6.1.2 "LPI Configuration tables"
159 struct vgic_v2_cpu_if {
162 u32 vgic_misr; /* Saved only */
163 u64 vgic_eisr; /* Saved only */
164 u64 vgic_elrsr; /* Saved only */
166 u32 vgic_lr[VGIC_V2_MAX_LRS];
169 struct vgic_v3_cpu_if {
170 #ifdef CONFIG_KVM_ARM_VGIC_V3
173 u32 vgic_sre; /* Restored only, change ignored */
174 u32 vgic_misr; /* Saved only */
175 u32 vgic_eisr; /* Saved only */
176 u32 vgic_elrsr; /* Saved only */
179 u64 vgic_lr[VGIC_V3_MAX_LRS];
184 /* CPU vif control registers for world switch */
186 struct vgic_v2_cpu_if vgic_v2;
187 struct vgic_v3_cpu_if vgic_v3;
190 unsigned int used_lrs;
191 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
193 spinlock_t ap_list_lock; /* Protects the ap_list */
196 * List of IRQs that this VCPU should consider because they are either
197 * Active or Pending (hence the name; AP list), or because they recently
198 * were one of the two and need to be migrated off this list to another
201 struct list_head ap_list_head;
206 * Members below are used with GICv3 emulation only and represent
207 * parts of the redistributor.
209 struct vgic_io_device rd_iodev;
210 struct vgic_io_device sgi_iodev;
212 /* Contains the attributes and gpa of the LPI pending tables. */
218 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
219 void kvm_vgic_early_init(struct kvm *kvm);
220 int kvm_vgic_create(struct kvm *kvm, u32 type);
221 void kvm_vgic_destroy(struct kvm *kvm);
222 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
223 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
224 int kvm_vgic_map_resources(struct kvm *kvm);
225 int kvm_vgic_hyp_init(void);
227 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
229 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
231 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
232 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
233 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
235 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
237 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
238 #define vgic_initialized(k) ((k)->arch.vgic.initialized)
239 #define vgic_ready(k) ((k)->arch.vgic.ready)
240 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
241 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
243 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
244 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
245 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
247 #ifdef CONFIG_KVM_ARM_VGIC_V3
248 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
250 static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
256 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
258 * The host's GIC naturally limits the maximum amount of VCPUs a guest
261 static inline int kvm_vgic_get_max_vcpus(void)
263 return kvm_vgic_global_state.max_gic_vcpus;
266 #endif /* __KVM_ARM_VGIC_H */