1 #ifndef __INCLUDE_ATMEL_SSC_H
2 #define __INCLUDE_ATMEL_SSC_H
4 #include <linux/platform_device.h>
5 #include <linux/list.h>
8 struct atmel_ssc_platform_data {
13 struct list_head list;
15 struct platform_device *pdev;
16 struct atmel_ssc_platform_data *pdata;
22 struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
23 void ssc_free(struct ssc_device *ssc);
25 /* SSC register offsets */
27 /* SSC Control Register */
28 #define SSC_CR 0x00000000
29 #define SSC_CR_RXDIS_SIZE 1
30 #define SSC_CR_RXDIS_OFFSET 1
31 #define SSC_CR_RXEN_SIZE 1
32 #define SSC_CR_RXEN_OFFSET 0
33 #define SSC_CR_SWRST_SIZE 1
34 #define SSC_CR_SWRST_OFFSET 15
35 #define SSC_CR_TXDIS_SIZE 1
36 #define SSC_CR_TXDIS_OFFSET 9
37 #define SSC_CR_TXEN_SIZE 1
38 #define SSC_CR_TXEN_OFFSET 8
40 /* SSC Clock Mode Register */
41 #define SSC_CMR 0x00000004
42 #define SSC_CMR_DIV_SIZE 12
43 #define SSC_CMR_DIV_OFFSET 0
45 /* SSC Receive Clock Mode Register */
46 #define SSC_RCMR 0x00000010
47 #define SSC_RCMR_CKG_SIZE 2
48 #define SSC_RCMR_CKG_OFFSET 6
49 #define SSC_RCMR_CKI_SIZE 1
50 #define SSC_RCMR_CKI_OFFSET 5
51 #define SSC_RCMR_CKO_SIZE 3
52 #define SSC_RCMR_CKO_OFFSET 2
53 #define SSC_RCMR_CKS_SIZE 2
54 #define SSC_RCMR_CKS_OFFSET 0
55 #define SSC_RCMR_PERIOD_SIZE 8
56 #define SSC_RCMR_PERIOD_OFFSET 24
57 #define SSC_RCMR_START_SIZE 4
58 #define SSC_RCMR_START_OFFSET 8
59 #define SSC_RCMR_STOP_SIZE 1
60 #define SSC_RCMR_STOP_OFFSET 12
61 #define SSC_RCMR_STTDLY_SIZE 8
62 #define SSC_RCMR_STTDLY_OFFSET 16
64 /* SSC Receive Frame Mode Register */
65 #define SSC_RFMR 0x00000014
66 #define SSC_RFMR_DATLEN_SIZE 5
67 #define SSC_RFMR_DATLEN_OFFSET 0
68 #define SSC_RFMR_DATNB_SIZE 4
69 #define SSC_RFMR_DATNB_OFFSET 8
70 #define SSC_RFMR_FSEDGE_SIZE 1
71 #define SSC_RFMR_FSEDGE_OFFSET 24
72 #define SSC_RFMR_FSLEN_SIZE 4
73 #define SSC_RFMR_FSLEN_OFFSET 16
74 #define SSC_RFMR_FSOS_SIZE 4
75 #define SSC_RFMR_FSOS_OFFSET 20
76 #define SSC_RFMR_LOOP_SIZE 1
77 #define SSC_RFMR_LOOP_OFFSET 5
78 #define SSC_RFMR_MSBF_SIZE 1
79 #define SSC_RFMR_MSBF_OFFSET 7
81 /* SSC Transmit Clock Mode Register */
82 #define SSC_TCMR 0x00000018
83 #define SSC_TCMR_CKG_SIZE 2
84 #define SSC_TCMR_CKG_OFFSET 6
85 #define SSC_TCMR_CKI_SIZE 1
86 #define SSC_TCMR_CKI_OFFSET 5
87 #define SSC_TCMR_CKO_SIZE 3
88 #define SSC_TCMR_CKO_OFFSET 2
89 #define SSC_TCMR_CKS_SIZE 2
90 #define SSC_TCMR_CKS_OFFSET 0
91 #define SSC_TCMR_PERIOD_SIZE 8
92 #define SSC_TCMR_PERIOD_OFFSET 24
93 #define SSC_TCMR_START_SIZE 4
94 #define SSC_TCMR_START_OFFSET 8
95 #define SSC_TCMR_STTDLY_SIZE 8
96 #define SSC_TCMR_STTDLY_OFFSET 16
98 /* SSC Transmit Frame Mode Register */
99 #define SSC_TFMR 0x0000001c
100 #define SSC_TFMR_DATDEF_SIZE 1
101 #define SSC_TFMR_DATDEF_OFFSET 5
102 #define SSC_TFMR_DATLEN_SIZE 5
103 #define SSC_TFMR_DATLEN_OFFSET 0
104 #define SSC_TFMR_DATNB_SIZE 4
105 #define SSC_TFMR_DATNB_OFFSET 8
106 #define SSC_TFMR_FSDEN_SIZE 1
107 #define SSC_TFMR_FSDEN_OFFSET 23
108 #define SSC_TFMR_FSEDGE_SIZE 1
109 #define SSC_TFMR_FSEDGE_OFFSET 24
110 #define SSC_TFMR_FSLEN_SIZE 4
111 #define SSC_TFMR_FSLEN_OFFSET 16
112 #define SSC_TFMR_FSOS_SIZE 3
113 #define SSC_TFMR_FSOS_OFFSET 20
114 #define SSC_TFMR_MSBF_SIZE 1
115 #define SSC_TFMR_MSBF_OFFSET 7
117 /* SSC Receive Hold Register */
118 #define SSC_RHR 0x00000020
119 #define SSC_RHR_RDAT_SIZE 32
120 #define SSC_RHR_RDAT_OFFSET 0
122 /* SSC Transmit Hold Register */
123 #define SSC_THR 0x00000024
124 #define SSC_THR_TDAT_SIZE 32
125 #define SSC_THR_TDAT_OFFSET 0
127 /* SSC Receive Sync. Holding Register */
128 #define SSC_RSHR 0x00000030
129 #define SSC_RSHR_RSDAT_SIZE 16
130 #define SSC_RSHR_RSDAT_OFFSET 0
132 /* SSC Transmit Sync. Holding Register */
133 #define SSC_TSHR 0x00000034
134 #define SSC_TSHR_TSDAT_SIZE 16
135 #define SSC_TSHR_RSDAT_OFFSET 0
137 /* SSC Receive Compare 0 Register */
138 #define SSC_RC0R 0x00000038
139 #define SSC_RC0R_CP0_SIZE 16
140 #define SSC_RC0R_CP0_OFFSET 0
142 /* SSC Receive Compare 1 Register */
143 #define SSC_RC1R 0x0000003c
144 #define SSC_RC1R_CP1_SIZE 16
145 #define SSC_RC1R_CP1_OFFSET 0
147 /* SSC Status Register */
148 #define SSC_SR 0x00000040
149 #define SSC_SR_CP0_SIZE 1
150 #define SSC_SR_CP0_OFFSET 8
151 #define SSC_SR_CP1_SIZE 1
152 #define SSC_SR_CP1_OFFSET 9
153 #define SSC_SR_ENDRX_SIZE 1
154 #define SSC_SR_ENDRX_OFFSET 6
155 #define SSC_SR_ENDTX_SIZE 1
156 #define SSC_SR_ENDTX_OFFSET 2
157 #define SSC_SR_OVRUN_SIZE 1
158 #define SSC_SR_OVRUN_OFFSET 5
159 #define SSC_SR_RXBUFF_SIZE 1
160 #define SSC_SR_RXBUFF_OFFSET 7
161 #define SSC_SR_RXEN_SIZE 1
162 #define SSC_SR_RXEN_OFFSET 17
163 #define SSC_SR_RXRDY_SIZE 1
164 #define SSC_SR_RXRDY_OFFSET 4
165 #define SSC_SR_RXSYN_SIZE 1
166 #define SSC_SR_RXSYN_OFFSET 11
167 #define SSC_SR_TXBUFE_SIZE 1
168 #define SSC_SR_TXBUFE_OFFSET 3
169 #define SSC_SR_TXEMPTY_SIZE 1
170 #define SSC_SR_TXEMPTY_OFFSET 1
171 #define SSC_SR_TXEN_SIZE 1
172 #define SSC_SR_TXEN_OFFSET 16
173 #define SSC_SR_TXRDY_SIZE 1
174 #define SSC_SR_TXRDY_OFFSET 0
175 #define SSC_SR_TXSYN_SIZE 1
176 #define SSC_SR_TXSYN_OFFSET 10
178 /* SSC Interrupt Enable Register */
179 #define SSC_IER 0x00000044
180 #define SSC_IER_CP0_SIZE 1
181 #define SSC_IER_CP0_OFFSET 8
182 #define SSC_IER_CP1_SIZE 1
183 #define SSC_IER_CP1_OFFSET 9
184 #define SSC_IER_ENDRX_SIZE 1
185 #define SSC_IER_ENDRX_OFFSET 6
186 #define SSC_IER_ENDTX_SIZE 1
187 #define SSC_IER_ENDTX_OFFSET 2
188 #define SSC_IER_OVRUN_SIZE 1
189 #define SSC_IER_OVRUN_OFFSET 5
190 #define SSC_IER_RXBUFF_SIZE 1
191 #define SSC_IER_RXBUFF_OFFSET 7
192 #define SSC_IER_RXRDY_SIZE 1
193 #define SSC_IER_RXRDY_OFFSET 4
194 #define SSC_IER_RXSYN_SIZE 1
195 #define SSC_IER_RXSYN_OFFSET 11
196 #define SSC_IER_TXBUFE_SIZE 1
197 #define SSC_IER_TXBUFE_OFFSET 3
198 #define SSC_IER_TXEMPTY_SIZE 1
199 #define SSC_IER_TXEMPTY_OFFSET 1
200 #define SSC_IER_TXRDY_SIZE 1
201 #define SSC_IER_TXRDY_OFFSET 0
202 #define SSC_IER_TXSYN_SIZE 1
203 #define SSC_IER_TXSYN_OFFSET 10
205 /* SSC Interrupt Disable Register */
206 #define SSC_IDR 0x00000048
207 #define SSC_IDR_CP0_SIZE 1
208 #define SSC_IDR_CP0_OFFSET 8
209 #define SSC_IDR_CP1_SIZE 1
210 #define SSC_IDR_CP1_OFFSET 9
211 #define SSC_IDR_ENDRX_SIZE 1
212 #define SSC_IDR_ENDRX_OFFSET 6
213 #define SSC_IDR_ENDTX_SIZE 1
214 #define SSC_IDR_ENDTX_OFFSET 2
215 #define SSC_IDR_OVRUN_SIZE 1
216 #define SSC_IDR_OVRUN_OFFSET 5
217 #define SSC_IDR_RXBUFF_SIZE 1
218 #define SSC_IDR_RXBUFF_OFFSET 7
219 #define SSC_IDR_RXRDY_SIZE 1
220 #define SSC_IDR_RXRDY_OFFSET 4
221 #define SSC_IDR_RXSYN_SIZE 1
222 #define SSC_IDR_RXSYN_OFFSET 11
223 #define SSC_IDR_TXBUFE_SIZE 1
224 #define SSC_IDR_TXBUFE_OFFSET 3
225 #define SSC_IDR_TXEMPTY_SIZE 1
226 #define SSC_IDR_TXEMPTY_OFFSET 1
227 #define SSC_IDR_TXRDY_SIZE 1
228 #define SSC_IDR_TXRDY_OFFSET 0
229 #define SSC_IDR_TXSYN_SIZE 1
230 #define SSC_IDR_TXSYN_OFFSET 10
232 /* SSC Interrupt Mask Register */
233 #define SSC_IMR 0x0000004c
234 #define SSC_IMR_CP0_SIZE 1
235 #define SSC_IMR_CP0_OFFSET 8
236 #define SSC_IMR_CP1_SIZE 1
237 #define SSC_IMR_CP1_OFFSET 9
238 #define SSC_IMR_ENDRX_SIZE 1
239 #define SSC_IMR_ENDRX_OFFSET 6
240 #define SSC_IMR_ENDTX_SIZE 1
241 #define SSC_IMR_ENDTX_OFFSET 2
242 #define SSC_IMR_OVRUN_SIZE 1
243 #define SSC_IMR_OVRUN_OFFSET 5
244 #define SSC_IMR_RXBUFF_SIZE 1
245 #define SSC_IMR_RXBUFF_OFFSET 7
246 #define SSC_IMR_RXRDY_SIZE 1
247 #define SSC_IMR_RXRDY_OFFSET 4
248 #define SSC_IMR_RXSYN_SIZE 1
249 #define SSC_IMR_RXSYN_OFFSET 11
250 #define SSC_IMR_TXBUFE_SIZE 1
251 #define SSC_IMR_TXBUFE_OFFSET 3
252 #define SSC_IMR_TXEMPTY_SIZE 1
253 #define SSC_IMR_TXEMPTY_OFFSET 1
254 #define SSC_IMR_TXRDY_SIZE 1
255 #define SSC_IMR_TXRDY_OFFSET 0
256 #define SSC_IMR_TXSYN_SIZE 1
257 #define SSC_IMR_TXSYN_OFFSET 10
259 /* SSC PDC Receive Pointer Register */
260 #define SSC_PDC_RPR 0x00000100
262 /* SSC PDC Receive Counter Register */
263 #define SSC_PDC_RCR 0x00000104
265 /* SSC PDC Transmit Pointer Register */
266 #define SSC_PDC_TPR 0x00000108
268 /* SSC PDC Receive Next Pointer Register */
269 #define SSC_PDC_RNPR 0x00000110
271 /* SSC PDC Receive Next Counter Register */
272 #define SSC_PDC_RNCR 0x00000114
274 /* SSC PDC Transmit Counter Register */
275 #define SSC_PDC_TCR 0x0000010c
277 /* SSC PDC Transmit Next Pointer Register */
278 #define SSC_PDC_TNPR 0x00000118
280 /* SSC PDC Transmit Next Counter Register */
281 #define SSC_PDC_TNCR 0x0000011c
283 /* SSC PDC Transfer Control Register */
284 #define SSC_PDC_PTCR 0x00000120
285 #define SSC_PDC_PTCR_RXTDIS_SIZE 1
286 #define SSC_PDC_PTCR_RXTDIS_OFFSET 1
287 #define SSC_PDC_PTCR_RXTEN_SIZE 1
288 #define SSC_PDC_PTCR_RXTEN_OFFSET 0
289 #define SSC_PDC_PTCR_TXTDIS_SIZE 1
290 #define SSC_PDC_PTCR_TXTDIS_OFFSET 9
291 #define SSC_PDC_PTCR_TXTEN_SIZE 1
292 #define SSC_PDC_PTCR_TXTEN_OFFSET 8
294 /* SSC PDC Transfer Status Register */
295 #define SSC_PDC_PTSR 0x00000124
296 #define SSC_PDC_PTSR_RXTEN_SIZE 1
297 #define SSC_PDC_PTSR_RXTEN_OFFSET 0
298 #define SSC_PDC_PTSR_TXTEN_SIZE 1
299 #define SSC_PDC_PTSR_TXTEN_OFFSET 8
301 /* Bit manipulation macros */
302 #define SSC_BIT(name) \
303 (1 << SSC_##name##_OFFSET)
304 #define SSC_BF(name, value) \
305 (((value) & ((1 << SSC_##name##_SIZE) - 1)) \
306 << SSC_##name##_OFFSET)
307 #define SSC_BFEXT(name, value) \
308 (((value) >> SSC_##name##_OFFSET) \
309 & ((1 << SSC_##name##_SIZE) - 1))
310 #define SSC_BFINS(name, value, old) \
311 (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \
312 << SSC_##name##_OFFSET)) | SSC_BF(name, value))
314 /* Register access macros */
315 #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg)
316 #define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg)
318 #endif /* __INCLUDE_ATMEL_SSC_H */