2 * linux/include/linux/clk-provider.h
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __LINUX_CLK_PROVIDER_H
12 #define __LINUX_CLK_PROVIDER_H
17 #ifdef CONFIG_COMMON_CLK
20 * flags used across common struct clk. these flags should only affect the
21 * top-level framework. custom flags for dealing with hardware specifics
22 * belong in struct clk_foo
24 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
25 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
27 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
28 #define CLK_IS_ROOT BIT(4) /* Deprecated: Don't use */
29 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
30 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
31 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
32 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
33 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
34 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
45 * @rate: Requested clock rate. This field will be adjusted by
46 * clock drivers according to hardware capabilities.
47 * @min_rate: Minimum rate imposed by clk users.
48 * @max_rate: Maximum rate imposed by clk users.
49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
50 * requested constraints.
51 * @best_parent_hw: The most appropriate parent clock that fulfills the
52 * requested constraints.
55 struct clk_rate_request {
57 unsigned long min_rate;
58 unsigned long max_rate;
59 unsigned long best_parent_rate;
60 struct clk_hw *best_parent_hw;
64 * struct clk_ops - Callback operations for hardware clocks; these are to
65 * be provided by the clock implementation, and will be called by drivers
66 * through the clk_* api.
68 * @prepare: Prepare the clock for enabling. This must not return until
69 * the clock is fully prepared, and it's safe to call clk_enable.
70 * This callback is intended to allow clock implementations to
71 * do any initialisation that may sleep. Called with
74 * @unprepare: Release the clock from its prepared state. This will typically
75 * undo any work done in the @prepare callback. Called with
78 * @is_prepared: Queries the hardware to determine if the clock is prepared.
79 * This function is allowed to sleep. Optional, if this op is not
80 * set then the prepare count will be used.
82 * @unprepare_unused: Unprepare the clock atomically. Only called from
83 * clk_disable_unused for prepare clocks with special needs.
84 * Called with prepare mutex held. This function may sleep.
86 * @enable: Enable the clock atomically. This must not return until the
87 * clock is generating a valid clock signal, usable by consumer
88 * devices. Called with enable_lock held. This function must not
91 * @disable: Disable the clock atomically. Called with enable_lock held.
92 * This function must not sleep.
94 * @is_enabled: Queries the hardware to determine if the clock is enabled.
95 * This function must not sleep. Optional, if this op is not
96 * set then the enable count will be used.
98 * @disable_unused: Disable the clock atomically. Only called from
99 * clk_disable_unused for gate clocks with special needs.
100 * Called with enable_lock held. This function must not
103 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
104 * parent rate is an input parameter. It is up to the caller to
105 * ensure that the prepare_mutex is held across this call.
106 * Returns the calculated rate. Optional, but recommended - if
107 * this op is not set then clock rate will be initialized to 0.
109 * @round_rate: Given a target rate as input, returns the closest rate actually
110 * supported by the clock. The parent rate is an input/output
113 * @determine_rate: Given a target rate as input, returns the closest rate
114 * actually supported by the clock, and optionally the parent clock
115 * that should be used to provide the clock rate.
117 * @set_parent: Change the input source of this clock; for clocks with multiple
118 * possible parents specify a new parent by passing in the index
119 * as a u8 corresponding to the parent in either the .parent_names
120 * or .parents arrays. This function in affect translates an
121 * array index into the value programmed into the hardware.
122 * Returns 0 on success, -EERROR otherwise.
124 * @get_parent: Queries the hardware to determine the parent of a clock. The
125 * return value is a u8 which specifies the index corresponding to
126 * the parent clock. This index can be applied to either the
127 * .parent_names or .parents arrays. In short, this function
128 * translates the parent value read from hardware into an array
129 * index. Currently only called when the clock is initialized by
130 * __clk_init. This callback is mandatory for clocks with
131 * multiple parents. It is optional (and unnecessary) for clocks
132 * with 0 or 1 parents.
134 * @set_rate: Change the rate of this clock. The requested rate is specified
135 * by the second argument, which should typically be the return
136 * of .round_rate call. The third argument gives the parent rate
137 * which is likely helpful for most .set_rate implementation.
138 * Returns 0 on success, -EERROR otherwise.
140 * @set_rate_and_parent: Change the rate and the parent of this clock. The
141 * requested rate is specified by the second argument, which
142 * should typically be the return of .round_rate call. The
143 * third argument gives the parent rate which is likely helpful
144 * for most .set_rate_and_parent implementation. The fourth
145 * argument gives the parent index. This callback is optional (and
146 * unnecessary) for clocks with 0 or 1 parents as well as
147 * for clocks that can tolerate switching the rate and the parent
148 * separately via calls to .set_parent and .set_rate.
149 * Returns 0 on success, -EERROR otherwise.
151 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
152 * is expressed in ppb (parts per billion). The parent accuracy is
153 * an input parameter.
154 * Returns the calculated accuracy. Optional - if this op is not
155 * set then clock accuracy will be initialized to parent accuracy
156 * or 0 (perfect clock) if clock has no parent.
158 * @get_phase: Queries the hardware to get the current phase of a clock.
159 * Returned values are 0-359 degrees on success, negative
160 * error codes on failure.
162 * @set_phase: Shift the phase this clock signal in degrees specified
163 * by the second argument. Valid values for degrees are
164 * 0-359. Return 0 on success, otherwise -EERROR.
166 * @init: Perform platform-specific initialization magic.
167 * This is not not used by any of the basic clock types.
168 * Please consider other ways of solving initialization problems
169 * before using this callback, as its use is discouraged.
171 * @debug_init: Set up type-specific debugfs entries for this clock. This
172 * is called once, after the debugfs directory entry for this
173 * clock has been created. The dentry pointer representing that
174 * directory is provided as an argument. Called with
175 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
178 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
179 * implementations to split any work between atomic (enable) and sleepable
180 * (prepare) contexts. If enabling a clock requires code that might sleep,
181 * this must be done in clk_prepare. Clock enable code that will never be
182 * called in a sleepable context may be implemented in clk_enable.
184 * Typically, drivers will call clk_prepare when a clock may be needed later
185 * (eg. when a device is opened), and clk_enable when the clock is actually
186 * required (eg. from an interrupt). Note that clk_prepare MUST have been
187 * called before clk_enable.
190 int (*prepare)(struct clk_hw *hw);
191 void (*unprepare)(struct clk_hw *hw);
192 int (*is_prepared)(struct clk_hw *hw);
193 void (*unprepare_unused)(struct clk_hw *hw);
194 int (*enable)(struct clk_hw *hw);
195 void (*disable)(struct clk_hw *hw);
196 int (*is_enabled)(struct clk_hw *hw);
197 void (*disable_unused)(struct clk_hw *hw);
198 unsigned long (*recalc_rate)(struct clk_hw *hw,
199 unsigned long parent_rate);
200 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
201 unsigned long *parent_rate);
202 int (*determine_rate)(struct clk_hw *hw,
203 struct clk_rate_request *req);
204 int (*set_parent)(struct clk_hw *hw, u8 index);
205 u8 (*get_parent)(struct clk_hw *hw);
206 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
207 unsigned long parent_rate);
208 int (*set_rate_and_parent)(struct clk_hw *hw,
210 unsigned long parent_rate, u8 index);
211 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
212 unsigned long parent_accuracy);
213 int (*get_phase)(struct clk_hw *hw);
214 int (*set_phase)(struct clk_hw *hw, int degrees);
215 void (*init)(struct clk_hw *hw);
216 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
220 * struct clk_init_data - holds init data that's common to all clocks and is
221 * shared between the clock provider and the common clock framework.
224 * @ops: operations this clock supports
225 * @parent_names: array of string names for all possible parents
226 * @num_parents: number of possible parents
227 * @flags: framework-level hints and quirks
229 struct clk_init_data {
231 const struct clk_ops *ops;
232 const char * const *parent_names;
238 * struct clk_hw - handle for traversing from a struct clk to its corresponding
239 * hardware-specific structure. struct clk_hw should be declared within struct
240 * clk_foo and then referenced by the struct clk instance that uses struct
243 * @core: pointer to the struct clk_core instance that points back to this
244 * struct clk_hw instance
246 * @clk: pointer to the per-user struct clk instance that can be used to call
249 * @init: pointer to struct clk_init_data that contains the init data shared
250 * with the common clock framework.
253 struct clk_core *core;
255 const struct clk_init_data *init;
259 * DOC: Basic clock implementations common to many platforms
261 * Each basic clock hardware type is comprised of a structure describing the
262 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
263 * unique flags for that hardware type, a registration function and an
264 * alternative macro for static initialization
268 * struct clk_fixed_rate - fixed-rate clock
269 * @hw: handle between common and hardware-specific interfaces
270 * @fixed_rate: constant frequency of clock
272 struct clk_fixed_rate {
274 unsigned long fixed_rate;
275 unsigned long fixed_accuracy;
279 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
281 extern const struct clk_ops clk_fixed_rate_ops;
282 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
283 const char *parent_name, unsigned long flags,
284 unsigned long fixed_rate);
285 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
286 const char *name, const char *parent_name, unsigned long flags,
287 unsigned long fixed_rate, unsigned long fixed_accuracy);
288 void clk_unregister_fixed_rate(struct clk *clk);
289 void of_fixed_clk_setup(struct device_node *np);
292 * struct clk_gate - gating clock
294 * @hw: handle between common and hardware-specific interfaces
295 * @reg: register controlling gate
296 * @bit_idx: single bit controlling gate
297 * @flags: hardware-specific flags
298 * @lock: register lock
300 * Clock which can gate its output. Implements .enable & .disable
303 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
304 * enable the clock. Setting this flag does the opposite: setting the bit
305 * disable the clock and clearing it enables the clock
306 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
307 * of this register, and mask of gate bits are in higher 16-bit of this
308 * register. While setting the gate bits, higher 16-bit should also be
309 * updated to indicate changing gate bits.
319 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
321 #define CLK_GATE_SET_TO_DISABLE BIT(0)
322 #define CLK_GATE_HIWORD_MASK BIT(1)
324 extern const struct clk_ops clk_gate_ops;
325 struct clk *clk_register_gate(struct device *dev, const char *name,
326 const char *parent_name, unsigned long flags,
327 void __iomem *reg, u8 bit_idx,
328 u8 clk_gate_flags, spinlock_t *lock);
329 void clk_unregister_gate(struct clk *clk);
331 struct clk_div_table {
337 * struct clk_divider - adjustable divider clock
339 * @hw: handle between common and hardware-specific interfaces
340 * @reg: register containing the divider
341 * @shift: shift to the divider bit field
342 * @width: width of the divider bit field
343 * @table: array of value/divider pairs, last entry should have div = 0
344 * @lock: register lock
346 * Clock with an adjustable divider affecting its output frequency. Implements
347 * .recalc_rate, .set_rate and .round_rate
350 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
351 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
352 * the raw value read from the register, with the value of zero considered
353 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
354 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
355 * the hardware register
356 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
357 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
358 * Some hardware implementations gracefully handle this case and allow a
359 * zero divisor by not modifying their input clock
360 * (divide by one / bypass).
361 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
362 * of this register, and mask of divider bits are in higher 16-bit of this
363 * register. While setting the divider bits, higher 16-bit should also be
364 * updated to indicate changing divider bits.
365 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
366 * to the closest integer instead of the up one.
367 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
368 * not be changed by the clock framework.
369 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
370 * except when the value read from the register is zero, the divisor is
371 * 2^width of the field.
379 const struct clk_div_table *table;
383 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
385 #define CLK_DIVIDER_ONE_BASED BIT(0)
386 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
387 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
388 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
389 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
390 #define CLK_DIVIDER_READ_ONLY BIT(5)
391 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
393 extern const struct clk_ops clk_divider_ops;
394 extern const struct clk_ops clk_divider_ro_ops;
396 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
397 unsigned int val, const struct clk_div_table *table,
398 unsigned long flags);
399 long divider_round_rate(struct clk_hw *hw, unsigned long rate,
400 unsigned long *prate, const struct clk_div_table *table,
401 u8 width, unsigned long flags);
402 int divider_get_val(unsigned long rate, unsigned long parent_rate,
403 const struct clk_div_table *table, u8 width,
404 unsigned long flags);
406 struct clk *clk_register_divider(struct device *dev, const char *name,
407 const char *parent_name, unsigned long flags,
408 void __iomem *reg, u8 shift, u8 width,
409 u8 clk_divider_flags, spinlock_t *lock);
410 struct clk *clk_register_divider_table(struct device *dev, const char *name,
411 const char *parent_name, unsigned long flags,
412 void __iomem *reg, u8 shift, u8 width,
413 u8 clk_divider_flags, const struct clk_div_table *table,
415 void clk_unregister_divider(struct clk *clk);
418 * struct clk_mux - multiplexer clock
420 * @hw: handle between common and hardware-specific interfaces
421 * @reg: register controlling multiplexer
422 * @shift: shift to multiplexer bit field
423 * @width: width of mutliplexer bit field
424 * @flags: hardware-specific flags
425 * @lock: register lock
427 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
431 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
432 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
433 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
434 * register, and mask of mux bits are in higher 16-bit of this register.
435 * While setting the mux bits, higher 16-bit should also be updated to
436 * indicate changing mux bits.
437 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
450 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
452 #define CLK_MUX_INDEX_ONE BIT(0)
453 #define CLK_MUX_INDEX_BIT BIT(1)
454 #define CLK_MUX_HIWORD_MASK BIT(2)
455 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
456 #define CLK_MUX_ROUND_CLOSEST BIT(4)
458 extern const struct clk_ops clk_mux_ops;
459 extern const struct clk_ops clk_mux_ro_ops;
461 struct clk *clk_register_mux(struct device *dev, const char *name,
462 const char * const *parent_names, u8 num_parents,
464 void __iomem *reg, u8 shift, u8 width,
465 u8 clk_mux_flags, spinlock_t *lock);
467 struct clk *clk_register_mux_table(struct device *dev, const char *name,
468 const char * const *parent_names, u8 num_parents,
470 void __iomem *reg, u8 shift, u32 mask,
471 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
473 void clk_unregister_mux(struct clk *clk);
475 void of_fixed_factor_clk_setup(struct device_node *node);
478 * struct clk_fixed_factor - fixed multiplier and divider clock
480 * @hw: handle between common and hardware-specific interfaces
484 * Clock with a fixed multiplier and divider. The output frequency is the
485 * parent clock rate divided by div and multiplied by mult.
486 * Implements .recalc_rate, .set_rate and .round_rate
489 struct clk_fixed_factor {
495 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
497 extern const struct clk_ops clk_fixed_factor_ops;
498 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
499 const char *parent_name, unsigned long flags,
500 unsigned int mult, unsigned int div);
501 void clk_unregister_fixed_factor(struct clk *clk);
504 * struct clk_fractional_divider - adjustable fractional divider clock
506 * @hw: handle between common and hardware-specific interfaces
507 * @reg: register containing the divider
508 * @mshift: shift to the numerator bit field
509 * @mwidth: width of the numerator bit field
510 * @nshift: shift to the denominator bit field
511 * @nwidth: width of the denominator bit field
512 * @lock: register lock
514 * Clock with adjustable fractional divider affecting its output frequency.
516 struct clk_fractional_divider {
529 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
531 extern const struct clk_ops clk_fractional_divider_ops;
532 struct clk *clk_register_fractional_divider(struct device *dev,
533 const char *name, const char *parent_name, unsigned long flags,
534 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
535 u8 clk_divider_flags, spinlock_t *lock);
538 * struct clk_multiplier - adjustable multiplier clock
540 * @hw: handle between common and hardware-specific interfaces
541 * @reg: register containing the multiplier
542 * @shift: shift to the multiplier bit field
543 * @width: width of the multiplier bit field
544 * @lock: register lock
546 * Clock with an adjustable multiplier affecting its output frequency.
547 * Implements .recalc_rate, .set_rate and .round_rate
550 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
551 * from the register, with 0 being a valid value effectively
552 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
553 * set, then a null multiplier will be considered as a bypass,
554 * leaving the parent rate unmodified.
555 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
556 * rounded to the closest integer instead of the down one.
558 struct clk_multiplier {
567 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
569 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
570 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
572 extern const struct clk_ops clk_multiplier_ops;
575 * struct clk_composite - aggregate clock of mux, divider and gate clocks
577 * @hw: handle between common and hardware-specific interfaces
578 * @mux_hw: handle between composite and hardware-specific mux clock
579 * @rate_hw: handle between composite and hardware-specific rate clock
580 * @gate_hw: handle between composite and hardware-specific gate clock
581 * @mux_ops: clock ops for mux
582 * @rate_ops: clock ops for rate
583 * @gate_ops: clock ops for gate
585 struct clk_composite {
589 struct clk_hw *mux_hw;
590 struct clk_hw *rate_hw;
591 struct clk_hw *gate_hw;
593 const struct clk_ops *mux_ops;
594 const struct clk_ops *rate_ops;
595 const struct clk_ops *gate_ops;
598 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
600 struct clk *clk_register_composite(struct device *dev, const char *name,
601 const char * const *parent_names, int num_parents,
602 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
603 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
604 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
605 unsigned long flags);
608 * struct clk_gpio_gate - gpio gated clock
610 * @hw: handle between common and hardware-specific interfaces
611 * @gpiod: gpio descriptor
613 * Clock with a gpio control for enabling and disabling the parent clock.
614 * Implements .enable, .disable and .is_enabled
619 struct gpio_desc *gpiod;
622 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
624 extern const struct clk_ops clk_gpio_gate_ops;
625 struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
626 const char *parent_name, unsigned gpio, bool active_low,
627 unsigned long flags);
630 * struct clk_gpio_mux - gpio controlled clock multiplexer
632 * @hw: see struct clk_gpio
633 * @gpiod: gpio descriptor to select the parent of this clock multiplexer
635 * Clock with a gpio control for selecting the parent clock.
636 * Implements .get_parent, .set_parent and .determine_rate
639 extern const struct clk_ops clk_gpio_mux_ops;
640 struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
641 const char * const *parent_names, u8 num_parents, unsigned gpio,
642 bool active_low, unsigned long flags);
645 * clk_register - allocate a new clock, register it and return an opaque cookie
646 * @dev: device that is registering this clock
647 * @hw: link to hardware-specific clock data
649 * clk_register is the primary interface for populating the clock tree with new
650 * clock nodes. It returns a pointer to the newly allocated struct clk which
651 * cannot be dereferenced by driver code but may be used in conjuction with the
652 * rest of the clock API. In the event of an error clk_register will return an
653 * error code; drivers must test for an error code after calling clk_register.
655 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
656 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
658 void clk_unregister(struct clk *clk);
659 void devm_clk_unregister(struct device *dev, struct clk *clk);
661 /* helper functions */
662 const char *__clk_get_name(const struct clk *clk);
663 const char *clk_hw_get_name(const struct clk_hw *hw);
664 struct clk_hw *__clk_get_hw(struct clk *clk);
665 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
666 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
667 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
669 unsigned int __clk_get_enable_count(struct clk *clk);
670 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
671 unsigned long __clk_get_flags(struct clk *clk);
672 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
673 bool clk_hw_is_prepared(const struct clk_hw *hw);
674 bool clk_hw_is_enabled(const struct clk_hw *hw);
675 bool __clk_is_enabled(struct clk *clk);
676 struct clk *__clk_lookup(const char *name);
677 int __clk_mux_determine_rate(struct clk_hw *hw,
678 struct clk_rate_request *req);
679 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
680 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
681 struct clk_rate_request *req);
682 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
683 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
684 unsigned long max_rate);
686 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
689 dst->core = src->core;
693 * FIXME clock api without lock protection
695 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
699 typedef void (*of_clk_init_cb_t)(struct device_node *);
701 struct clk_onecell_data {
703 unsigned int clk_num;
706 extern struct of_device_id __clk_of_table;
708 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
711 int of_clk_add_provider(struct device_node *np,
712 struct clk *(*clk_src_get)(struct of_phandle_args *args,
715 void of_clk_del_provider(struct device_node *np);
716 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
718 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
719 unsigned int of_clk_get_parent_count(struct device_node *np);
720 int of_clk_parent_fill(struct device_node *np, const char **parents,
722 const char *of_clk_get_parent_name(struct device_node *np, int index);
724 void of_clk_init(const struct of_device_id *matches);
726 #else /* !CONFIG_OF */
728 static inline int of_clk_add_provider(struct device_node *np,
729 struct clk *(*clk_src_get)(struct of_phandle_args *args,
735 static inline void of_clk_del_provider(struct device_node *np) {}
736 static inline struct clk *of_clk_src_simple_get(
737 struct of_phandle_args *clkspec, void *data)
739 return ERR_PTR(-ENOENT);
741 static inline struct clk *of_clk_src_onecell_get(
742 struct of_phandle_args *clkspec, void *data)
744 return ERR_PTR(-ENOENT);
746 static inline int of_clk_get_parent_count(struct device_node *np)
750 static inline int of_clk_parent_fill(struct device_node *np,
751 const char **parents, unsigned int size)
755 static inline const char *of_clk_get_parent_name(struct device_node *np,
760 static inline void of_clk_init(const struct of_device_id *matches) {}
761 #endif /* CONFIG_OF */
764 * wrap access to peripherals in accessor routines
765 * for improved portability across platforms
768 #if IS_ENABLED(CONFIG_PPC)
770 static inline u32 clk_readl(u32 __iomem *reg)
772 return ioread32be(reg);
775 static inline void clk_writel(u32 val, u32 __iomem *reg)
777 iowrite32be(val, reg);
780 #else /* platform dependent I/O accessors */
782 static inline u32 clk_readl(u32 __iomem *reg)
787 static inline void clk_writel(u32 val, u32 __iomem *reg)
792 #endif /* platform dependent I/O accessors */
794 #ifdef CONFIG_DEBUG_FS
795 struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
796 void *data, const struct file_operations *fops);
799 #endif /* CONFIG_COMMON_CLK */
800 #endif /* CLK_PROVIDER_H */