2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
21 #ifndef LINUX_DMAENGINE_H
22 #define LINUX_DMAENGINE_H
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/uio.h>
27 #include <linux/bug.h>
28 #include <linux/scatterlist.h>
29 #include <linux/bitmap.h>
30 #include <linux/types.h>
34 * typedef dma_cookie_t - an opaque DMA cookie
36 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
38 typedef s32 dma_cookie_t;
39 #define DMA_MIN_COOKIE 1
40 #define DMA_MAX_COOKIE INT_MAX
42 static inline int dma_submit_error(dma_cookie_t cookie)
44 return cookie < 0 ? cookie : 0;
48 * enum dma_status - DMA transaction status
49 * @DMA_COMPLETE: transaction completed
50 * @DMA_IN_PROGRESS: transaction not yet processed
51 * @DMA_PAUSED: transaction is paused
52 * @DMA_ERROR: transaction failed
62 * enum dma_transaction_type - DMA transaction types/indexes
64 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
65 * automatically set as dma devices are registered.
67 enum dma_transaction_type {
80 /* last transaction type for creation of the capabilities mask */
85 * enum dma_transfer_direction - dma transfer mode and direction indicator
86 * @DMA_MEM_TO_MEM: Async/Memcpy mode
87 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
88 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
89 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
91 enum dma_transfer_direction {
100 * Interleaved Transfer Request
101 * ----------------------------
102 * A chunk is collection of contiguous bytes to be transfered.
103 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
104 * ICGs may or maynot change between chunks.
105 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
106 * that when repeated an integral number of times, specifies the transfer.
107 * A transfer template is specification of a Frame, the number of times
108 * it is to be repeated and other per-transfer attributes.
110 * Practically, a client driver would have ready a template for each
111 * type of transfer it is going to need during its lifetime and
112 * set only 'src_start' and 'dst_start' before submitting the requests.
115 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
116 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
123 * struct data_chunk - Element of scatter-gather list that makes a frame.
124 * @size: Number of bytes to read from source.
125 * size_dst := fn(op, size_src), so doesn't mean much for destination.
126 * @icg: Number of bytes to jump after last src/dst address of this
127 * chunk and before first src/dst address for next chunk.
128 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
129 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
137 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
139 * @src_start: Bus address of source for the first chunk.
140 * @dst_start: Bus address of destination for the first chunk.
141 * @dir: Specifies the type of Source and Destination.
142 * @src_inc: If the source address increments after reading from it.
143 * @dst_inc: If the destination address increments after writing to it.
144 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
145 * Otherwise, source is read contiguously (icg ignored).
146 * Ignored if src_inc is false.
147 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
148 * Otherwise, destination is filled contiguously (icg ignored).
149 * Ignored if dst_inc is false.
150 * @numf: Number of frames in this template.
151 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
152 * @sgl: Array of {chunk,icg} pairs that make up a frame.
154 struct dma_interleaved_template {
155 dma_addr_t src_start;
156 dma_addr_t dst_start;
157 enum dma_transfer_direction dir;
164 struct data_chunk sgl[0];
168 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
169 * control completion, and communicate status.
170 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
172 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
173 * acknowledges receipt, i.e. has has a chance to establish any dependency
175 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
176 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
177 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
178 * sources that were the result of a previous operation, in the case of a PQ
179 * operation it continues the calculation with new sources
180 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
181 * on the result of this operation
183 enum dma_ctrl_flags {
184 DMA_PREP_INTERRUPT = (1 << 0),
185 DMA_CTRL_ACK = (1 << 1),
186 DMA_PREP_PQ_DISABLE_P = (1 << 2),
187 DMA_PREP_PQ_DISABLE_Q = (1 << 3),
188 DMA_PREP_CONTINUE = (1 << 4),
189 DMA_PREP_FENCE = (1 << 5),
193 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
194 * on a running channel.
195 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
196 * @DMA_PAUSE: pause ongoing transfers
197 * @DMA_RESUME: resume paused transfer
198 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
199 * that need to runtime reconfigure the slave channels (as opposed to passing
200 * configuration data in statically from the platform). An additional
201 * argument of struct dma_slave_config must be passed in with this
203 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
204 * into external start mode.
211 FSLDMA_EXTERNAL_START,
215 * enum sum_check_bits - bit position of pq_check_flags
217 enum sum_check_bits {
223 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
224 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
225 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
227 enum sum_check_flags {
228 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
229 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
234 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
235 * See linux/cpumask.h
237 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
240 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
241 * @memcpy_count: transaction counter
242 * @bytes_transferred: byte counter
245 struct dma_chan_percpu {
247 unsigned long memcpy_count;
248 unsigned long bytes_transferred;
252 * struct dma_chan - devices supply DMA channels, clients use them
253 * @device: ptr to the dma device who supplies this channel, always !%NULL
254 * @cookie: last cookie value returned to client
255 * @completed_cookie: last completed cookie for this channel
256 * @chan_id: channel ID for sysfs
257 * @dev: class device for sysfs
258 * @device_node: used to add this to the device chan list
259 * @local: per-cpu pointer to a struct dma_chan_percpu
260 * @client_count: how many clients are using this channel
261 * @table_count: number of appearances in the mem-to-mem allocation table
262 * @private: private data for certain client-channel associations
265 struct dma_device *device;
267 dma_cookie_t completed_cookie;
271 struct dma_chan_dev *dev;
273 struct list_head device_node;
274 struct dma_chan_percpu __percpu *local;
281 * struct dma_chan_dev - relate sysfs device node to backing channel device
282 * @chan: driver channel device
283 * @device: sysfs device
284 * @dev_id: parent dma_device dev_id
285 * @idr_ref: reference count to gate release of dma_device dev_id
287 struct dma_chan_dev {
288 struct dma_chan *chan;
289 struct device device;
295 * enum dma_slave_buswidth - defines bus with of the DMA slave
296 * device, source or target buses
298 enum dma_slave_buswidth {
299 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
300 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
301 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
302 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
303 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
307 * struct dma_slave_config - dma slave channel runtime config
308 * @direction: whether the data shall go in or out on this slave
309 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
311 * @src_addr: this is the physical address where DMA slave data
312 * should be read (RX), if the source is memory this argument is
314 * @dst_addr: this is the physical address where DMA slave data
315 * should be written (TX), if the source is memory this argument
317 * @src_addr_width: this is the width in bytes of the source (RX)
318 * register where DMA data shall be read. If the source
319 * is memory this may be ignored depending on architecture.
320 * Legal values: 1, 2, 4, 8.
321 * @dst_addr_width: same as src_addr_width but for destination
322 * target (TX) mutatis mutandis.
323 * @src_maxburst: the maximum number of words (note: words, as in
324 * units of the src_addr_width member, not bytes) that can be sent
325 * in one burst to the device. Typically something like half the
326 * FIFO depth on I/O peripherals so you don't overflow it. This
327 * may or may not be applicable on memory sources.
328 * @dst_maxburst: same as src_maxburst but for destination target
330 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
331 * with 'true' if peripheral should be flow controller. Direction will be
332 * selected at Runtime.
333 * @slave_id: Slave requester id. Only valid for slave channels. The dma
334 * slave peripheral will have unique id as dma requester which need to be
335 * pass as slave config.
337 * This struct is passed in as configuration data to a DMA engine
338 * in order to set up a certain channel for DMA transport at runtime.
339 * The DMA device/engine has to provide support for an additional
340 * command in the channel config interface, DMA_SLAVE_CONFIG
341 * and this struct will then be passed in as an argument to the
342 * DMA engine device_control() function.
344 * The rationale for adding configuration information to this struct is as
345 * follows: if it is likely that more than one DMA slave controllers in
346 * the world will support the configuration option, then make it generic.
347 * If not: if it is fixed so that it be sent in static from the platform
348 * data, then prefer to do that.
350 struct dma_slave_config {
351 enum dma_transfer_direction direction;
354 enum dma_slave_buswidth src_addr_width;
355 enum dma_slave_buswidth dst_addr_width;
359 unsigned int slave_id;
363 * enum dma_residue_granularity - Granularity of the reported transfer residue
364 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
365 * DMA channel is only able to tell whether a descriptor has been completed or
366 * not, which means residue reporting is not supported by this channel. The
367 * residue field of the dma_tx_state field will always be 0.
368 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
369 * completed segment of the transfer (For cyclic transfers this is after each
370 * period). This is typically implemented by having the hardware generate an
371 * interrupt after each transferred segment and then the drivers updates the
372 * outstanding residue by the size of the segment. Another possibility is if
373 * the hardware supports scatter-gather and the segment descriptor has a field
374 * which gets set after the segment has been completed. The driver then counts
375 * the number of segments without the flag set to compute the residue.
376 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
377 * burst. This is typically only supported if the hardware has a progress
378 * register of some sort (E.g. a register with the current read/write address
379 * or a register with the amount of bursts/beats/bytes that have been
380 * transferred or still need to be transferred).
382 enum dma_residue_granularity {
383 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
384 DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
385 DMA_RESIDUE_GRANULARITY_BURST = 2,
388 /* struct dma_slave_caps - expose capabilities of a slave channel only
390 * @src_addr_widths: bit mask of src addr widths the channel supports
391 * @dstn_addr_widths: bit mask of dstn addr widths the channel supports
392 * @directions: bit mask of slave direction the channel supported
393 * since the enum dma_transfer_direction is not defined as bits for each
394 * type of direction, the dma controller should fill (1 << <TYPE>) and same
395 * should be checked by controller as well
396 * @cmd_pause: true, if pause and thereby resume is supported
397 * @cmd_terminate: true, if terminate cmd is supported
398 * @residue_granularity: granularity of the reported transfer residue
400 struct dma_slave_caps {
402 u32 dstn_addr_widths;
406 enum dma_residue_granularity residue_granularity;
409 static inline const char *dma_chan_name(struct dma_chan *chan)
411 return dev_name(&chan->dev->device);
414 void dma_chan_cleanup(struct kref *kref);
417 * typedef dma_filter_fn - callback filter for dma_request_channel
418 * @chan: channel to be reviewed
419 * @filter_param: opaque parameter passed through dma_request_channel
421 * When this optional parameter is specified in a call to dma_request_channel a
422 * suitable channel is passed to this routine for further dispositioning before
423 * being returned. Where 'suitable' indicates a non-busy channel that
424 * satisfies the given capability mask. It returns 'true' to indicate that the
425 * channel is suitable.
427 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
429 typedef void (*dma_async_tx_callback)(void *dma_async_param);
431 struct dmaengine_unmap_data {
442 * struct dma_async_tx_descriptor - async transaction descriptor
443 * ---dma generic offload fields---
444 * @cookie: tracking cookie for this transaction, set to -EBUSY if
445 * this tx is sitting on a dependency list
446 * @flags: flags to augment operation preparation, control completion, and
448 * @phys: physical address of the descriptor
449 * @chan: target channel for this operation
450 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
451 * @callback: routine to call after this operation is complete
452 * @callback_param: general parameter to pass to the callback routine
453 * ---async_tx api specific fields---
454 * @next: at completion submit this descriptor
455 * @parent: pointer to the next level up in the dependency chain
456 * @lock: protect the parent and next pointers
458 struct dma_async_tx_descriptor {
460 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
462 struct dma_chan *chan;
463 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
464 dma_async_tx_callback callback;
465 void *callback_param;
466 struct dmaengine_unmap_data *unmap;
467 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
468 struct dma_async_tx_descriptor *next;
469 struct dma_async_tx_descriptor *parent;
474 #ifdef CONFIG_DMA_ENGINE
475 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
476 struct dmaengine_unmap_data *unmap)
478 kref_get(&unmap->kref);
482 struct dmaengine_unmap_data *
483 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
484 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
486 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
487 struct dmaengine_unmap_data *unmap)
490 static inline struct dmaengine_unmap_data *
491 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
495 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
500 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
503 dmaengine_unmap_put(tx->unmap);
508 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
509 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
512 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
515 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
519 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
522 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
525 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
529 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
535 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
537 spin_lock_bh(&txd->lock);
539 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
541 spin_unlock_bh(&txd->lock);
543 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
548 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
552 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
556 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
560 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
567 * struct dma_tx_state - filled in to report the status of
569 * @last: last completed DMA cookie
570 * @used: last issued DMA cookie (i.e. the one in progress)
571 * @residue: the remaining number of bytes left to transmit
572 * on the selected transfer for states DMA_IN_PROGRESS and
573 * DMA_PAUSED if this is implemented in the driver, else 0
575 struct dma_tx_state {
582 * struct dma_device - info on the entity supplying DMA services
583 * @chancnt: how many DMA channels are supported
584 * @privatecnt: how many DMA channels are requested by dma_request_channel
585 * @channels: the list of struct dma_chan
586 * @global_node: list_head for global dma_device_list
587 * @cap_mask: one or more dma_capability flags
588 * @max_xor: maximum number of xor sources, 0 if no capability
589 * @max_pq: maximum number of PQ sources and PQ-continue capability
590 * @copy_align: alignment shift for memcpy operations
591 * @xor_align: alignment shift for xor operations
592 * @pq_align: alignment shift for pq operations
593 * @fill_align: alignment shift for memset operations
594 * @dev_id: unique device ID
595 * @dev: struct device reference for dma mapping api
596 * @device_alloc_chan_resources: allocate resources and return the
597 * number of allocated descriptors
598 * @device_free_chan_resources: release DMA channel's resources
599 * @device_prep_dma_memcpy: prepares a memcpy operation
600 * @device_prep_dma_xor: prepares a xor operation
601 * @device_prep_dma_xor_val: prepares a xor validation operation
602 * @device_prep_dma_pq: prepares a pq operation
603 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
604 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
605 * @device_prep_slave_sg: prepares a slave dma operation
606 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
607 * The function takes a buffer of size buf_len. The callback function will
608 * be called after period_len bytes have been transferred.
609 * @device_prep_interleaved_dma: Transfer expression in a generic way.
610 * @device_control: manipulate all pending operations on a channel, returns
612 * @device_tx_status: poll for transaction completion, the optional
613 * txstate parameter can be supplied with a pointer to get a
614 * struct with auxiliary transfer status information, otherwise the call
615 * will just return a simple status code
616 * @device_issue_pending: push pending transactions to hardware
617 * @device_slave_caps: return the slave channel capabilities
621 unsigned int chancnt;
622 unsigned int privatecnt;
623 struct list_head channels;
624 struct list_head global_node;
625 dma_cap_mask_t cap_mask;
626 unsigned short max_xor;
627 unsigned short max_pq;
632 #define DMA_HAS_PQ_CONTINUE (1 << 15)
637 int (*device_alloc_chan_resources)(struct dma_chan *chan);
638 void (*device_free_chan_resources)(struct dma_chan *chan);
640 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
641 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
642 size_t len, unsigned long flags);
643 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
644 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
645 unsigned int src_cnt, size_t len, unsigned long flags);
646 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
647 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
648 size_t len, enum sum_check_flags *result, unsigned long flags);
649 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
650 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
651 unsigned int src_cnt, const unsigned char *scf,
652 size_t len, unsigned long flags);
653 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
654 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
655 unsigned int src_cnt, const unsigned char *scf, size_t len,
656 enum sum_check_flags *pqres, unsigned long flags);
657 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
658 struct dma_chan *chan, unsigned long flags);
659 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
660 struct dma_chan *chan,
661 struct scatterlist *dst_sg, unsigned int dst_nents,
662 struct scatterlist *src_sg, unsigned int src_nents,
663 unsigned long flags);
665 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
666 struct dma_chan *chan, struct scatterlist *sgl,
667 unsigned int sg_len, enum dma_transfer_direction direction,
668 unsigned long flags, void *context);
669 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
670 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
671 size_t period_len, enum dma_transfer_direction direction,
672 unsigned long flags, void *context);
673 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
674 struct dma_chan *chan, struct dma_interleaved_template *xt,
675 unsigned long flags);
676 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
679 enum dma_status (*device_tx_status)(struct dma_chan *chan,
681 struct dma_tx_state *txstate);
682 void (*device_issue_pending)(struct dma_chan *chan);
683 int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
686 static inline int dmaengine_device_control(struct dma_chan *chan,
687 enum dma_ctrl_cmd cmd,
690 if (chan->device->device_control)
691 return chan->device->device_control(chan, cmd, arg);
696 static inline int dmaengine_slave_config(struct dma_chan *chan,
697 struct dma_slave_config *config)
699 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
700 (unsigned long)config);
703 static inline bool is_slave_direction(enum dma_transfer_direction direction)
705 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
708 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
709 struct dma_chan *chan, dma_addr_t buf, size_t len,
710 enum dma_transfer_direction dir, unsigned long flags)
712 struct scatterlist sg;
713 sg_init_table(&sg, 1);
714 sg_dma_address(&sg) = buf;
715 sg_dma_len(&sg) = len;
717 return chan->device->device_prep_slave_sg(chan, &sg, 1,
721 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
722 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
723 enum dma_transfer_direction dir, unsigned long flags)
725 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
729 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
731 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
732 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
733 enum dma_transfer_direction dir, unsigned long flags,
734 struct rio_dma_ext *rio_ext)
736 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
737 dir, flags, rio_ext);
741 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
742 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
743 size_t period_len, enum dma_transfer_direction dir,
746 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
747 period_len, dir, flags, NULL);
750 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
751 struct dma_chan *chan, struct dma_interleaved_template *xt,
754 return chan->device->device_prep_interleaved_dma(chan, xt, flags);
757 static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
762 /* check if the channel supports slave transactions */
763 if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
766 if (chan->device->device_slave_caps)
767 return chan->device->device_slave_caps(chan, caps);
772 static inline int dmaengine_terminate_all(struct dma_chan *chan)
774 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
777 static inline int dmaengine_pause(struct dma_chan *chan)
779 return dmaengine_device_control(chan, DMA_PAUSE, 0);
782 static inline int dmaengine_resume(struct dma_chan *chan)
784 return dmaengine_device_control(chan, DMA_RESUME, 0);
787 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
788 dma_cookie_t cookie, struct dma_tx_state *state)
790 return chan->device->device_tx_status(chan, cookie, state);
793 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
795 return desc->tx_submit(desc);
798 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
804 mask = (1 << align) - 1;
805 if (mask & (off1 | off2 | len))
810 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
811 size_t off2, size_t len)
813 return dmaengine_check_align(dev->copy_align, off1, off2, len);
816 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
817 size_t off2, size_t len)
819 return dmaengine_check_align(dev->xor_align, off1, off2, len);
822 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
823 size_t off2, size_t len)
825 return dmaengine_check_align(dev->pq_align, off1, off2, len);
828 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
829 size_t off2, size_t len)
831 return dmaengine_check_align(dev->fill_align, off1, off2, len);
835 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
839 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
842 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
844 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
847 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
849 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
851 return (flags & mask) == mask;
854 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
856 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
859 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
861 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
864 /* dma_maxpq - reduce maxpq in the face of continued operations
865 * @dma - dma device with PQ capability
866 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
868 * When an engine does not support native continuation we need 3 extra
869 * source slots to reuse P and Q with the following coefficients:
870 * 1/ {00} * P : remove P from Q', but use it as a source for P'
871 * 2/ {01} * Q : use Q to continue Q' calculation
872 * 3/ {00} * Q : subtract Q from P' to cancel (2)
874 * In the case where P is disabled we only need 1 extra source:
875 * 1/ {01} * Q : use Q to continue Q' calculation
877 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
879 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
880 return dma_dev_to_maxpq(dma);
881 else if (dmaf_p_disabled_continue(flags))
882 return dma_dev_to_maxpq(dma) - 1;
883 else if (dmaf_continue(flags))
884 return dma_dev_to_maxpq(dma) - 3;
888 /* --- public DMA engine API --- */
890 #ifdef CONFIG_DMA_ENGINE
891 void dmaengine_get(void);
892 void dmaengine_put(void);
894 static inline void dmaengine_get(void)
897 static inline void dmaengine_put(void)
902 #ifdef CONFIG_NET_DMA
903 #define net_dmaengine_get() dmaengine_get()
904 #define net_dmaengine_put() dmaengine_put()
906 static inline void net_dmaengine_get(void)
909 static inline void net_dmaengine_put(void)
914 #ifdef CONFIG_ASYNC_TX_DMA
915 #define async_dmaengine_get() dmaengine_get()
916 #define async_dmaengine_put() dmaengine_put()
917 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
918 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
920 #define async_dma_find_channel(type) dma_find_channel(type)
921 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
923 static inline void async_dmaengine_get(void)
926 static inline void async_dmaengine_put(void)
929 static inline struct dma_chan *
930 async_dma_find_channel(enum dma_transaction_type type)
934 #endif /* CONFIG_ASYNC_TX_DMA */
936 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
937 void *dest, void *src, size_t len);
938 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
939 struct page *page, unsigned int offset, void *kdata, size_t len);
940 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
941 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
942 unsigned int src_off, size_t len);
943 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
944 struct dma_chan *chan);
946 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
948 tx->flags |= DMA_CTRL_ACK;
951 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
953 tx->flags &= ~DMA_CTRL_ACK;
956 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
958 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
961 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
963 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
965 set_bit(tx_type, dstp->bits);
968 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
970 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
972 clear_bit(tx_type, dstp->bits);
975 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
976 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
978 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
981 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
983 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
985 return test_bit(tx_type, srcp->bits);
988 #define for_each_dma_cap_mask(cap, mask) \
989 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
992 * dma_async_issue_pending - flush pending transactions to HW
993 * @chan: target DMA channel
995 * This allows drivers to push copies to HW in batches,
996 * reducing MMIO writes where possible.
998 static inline void dma_async_issue_pending(struct dma_chan *chan)
1000 chan->device->device_issue_pending(chan);
1004 * dma_async_is_tx_complete - poll for transaction completion
1005 * @chan: DMA channel
1006 * @cookie: transaction identifier to check status of
1007 * @last: returns last completed cookie, can be NULL
1008 * @used: returns last issued cookie, can be NULL
1010 * If @last and @used are passed in, upon return they reflect the driver
1011 * internal state and can be used with dma_async_is_complete() to check
1012 * the status of multiple cookies without re-checking hardware state.
1014 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1015 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1017 struct dma_tx_state state;
1018 enum dma_status status;
1020 status = chan->device->device_tx_status(chan, cookie, &state);
1029 * dma_async_is_complete - test a cookie against chan state
1030 * @cookie: transaction identifier to test status of
1031 * @last_complete: last know completed transaction
1032 * @last_used: last cookie value handed out
1034 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1035 * the test logic is separated for lightweight testing of multiple cookies
1037 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1038 dma_cookie_t last_complete, dma_cookie_t last_used)
1040 if (last_complete <= last_used) {
1041 if ((cookie <= last_complete) || (cookie > last_used))
1042 return DMA_COMPLETE;
1044 if ((cookie <= last_complete) && (cookie > last_used))
1045 return DMA_COMPLETE;
1047 return DMA_IN_PROGRESS;
1051 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1056 st->residue = residue;
1060 #ifdef CONFIG_DMA_ENGINE
1061 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1062 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1063 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1064 void dma_issue_pending_all(void);
1065 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1066 dma_filter_fn fn, void *fn_param);
1067 struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
1069 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1070 void dma_release_channel(struct dma_chan *chan);
1072 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1076 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1078 return DMA_COMPLETE;
1080 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1082 return DMA_COMPLETE;
1084 static inline void dma_issue_pending_all(void)
1087 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1088 dma_filter_fn fn, void *fn_param)
1092 static inline struct dma_chan *dma_request_slave_channel_reason(
1093 struct device *dev, const char *name)
1095 return ERR_PTR(-ENODEV);
1097 static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1102 static inline void dma_release_channel(struct dma_chan *chan)
1107 /* --- DMA device --- */
1109 int dma_async_device_register(struct dma_device *device);
1110 void dma_async_device_unregister(struct dma_device *device);
1111 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1112 struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
1113 struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
1114 struct dma_chan *net_dma_find_channel(void);
1115 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1116 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1117 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1119 static inline struct dma_chan
1120 *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
1121 dma_filter_fn fn, void *fn_param,
1122 struct device *dev, char *name)
1124 struct dma_chan *chan;
1126 chan = dma_request_slave_channel(dev, name);
1130 return __dma_request_channel(mask, fn, fn_param);
1133 /* --- Helper iov-locking functions --- */
1135 struct dma_page_list {
1136 char __user *base_address;
1138 struct page **pages;
1141 struct dma_pinned_list {
1143 struct dma_page_list page_list[0];
1146 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
1147 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
1149 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
1150 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
1151 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
1152 struct dma_pinned_list *pinned_list, struct page *page,
1153 unsigned int offset, size_t len);
1155 #endif /* DMAENGINE_H */