4 * Author: Dave Jiang <djiang@mvista.com>
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_
15 #include <linux/atomic.h>
16 #include <linux/kobject.h>
17 #include <linux/completion.h>
18 #include <linux/workqueue.h>
22 #define EDAC_OPSTATE_INVAL -1
23 #define EDAC_OPSTATE_POLL 0
24 #define EDAC_OPSTATE_NMI 1
25 #define EDAC_OPSTATE_INT 2
27 extern int edac_op_state;
28 extern int edac_err_assert;
29 extern atomic_t edac_handlers;
30 extern struct bus_type edac_subsys;
32 extern int edac_handler_set(void);
33 extern void edac_atomic_assert_error(void);
34 extern struct bus_type *edac_get_sysfs_subsys(void);
35 extern void edac_put_sysfs_subsys(void);
37 static inline void opstate_init(void)
39 switch (edac_op_state) {
40 case EDAC_OPSTATE_POLL:
41 case EDAC_OPSTATE_NMI:
44 edac_op_state = EDAC_OPSTATE_POLL;
49 #define EDAC_MC_LABEL_LEN 31
50 #define MC_PROC_NAME_MAX_LEN 7
53 * enum dev_type - describe the type of memory DRAM chips used at the stick
54 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
55 * @DEV_X1: 1 bit for data
56 * @DEV_X2: 2 bits for data
57 * @DEV_X4: 4 bits for data
58 * @DEV_X8: 8 bits for data
59 * @DEV_X16: 16 bits for data
60 * @DEV_X32: 32 bits for data
61 * @DEV_X64: 64 bits for data
63 * Typical values are x4 and x8.
72 DEV_X32, /* Do these parts exist? */
73 DEV_X64 /* Do these parts exist? */
76 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
77 #define DEV_FLAG_X1 BIT(DEV_X1)
78 #define DEV_FLAG_X2 BIT(DEV_X2)
79 #define DEV_FLAG_X4 BIT(DEV_X4)
80 #define DEV_FLAG_X8 BIT(DEV_X8)
81 #define DEV_FLAG_X16 BIT(DEV_X16)
82 #define DEV_FLAG_X32 BIT(DEV_X32)
83 #define DEV_FLAG_X64 BIT(DEV_X64)
86 * enum hw_event_mc_err_type - type of the detected error
88 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
89 * corrected error was detected
90 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
91 * can't be corrected by ECC, but it is not
92 * fatal (maybe it is on an unused memory area,
93 * or the memory controller could recover from
94 * it for example, by re-trying the operation).
95 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
98 enum hw_event_mc_err_type {
99 HW_EVENT_ERR_CORRECTED,
100 HW_EVENT_ERR_UNCORRECTED,
105 * enum mem_type - memory types. For a more detailed reference, please see
106 * http://en.wikipedia.org/wiki/DRAM
108 * @MEM_EMPTY Empty csrow
109 * @MEM_RESERVED: Reserved csrow type
110 * @MEM_UNKNOWN: Unknown csrow type
111 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
112 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
113 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
114 * @MEM_SDR: SDR - Single data rate SDRAM
115 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
116 * They use 3 pins for chip select: Pins 0 and 2 are
117 * for rank 0; pins 1 and 3 are for rank 1, if the memory
119 * @MEM_RDR: Registered SDR SDRAM
120 * @MEM_DDR: Double data rate SDRAM
121 * http://en.wikipedia.org/wiki/DDR_SDRAM
122 * @MEM_RDDR: Registered Double data rate SDRAM
123 * This is a variant of the DDR memories.
124 * A registered memory has a buffer inside it, hiding
125 * part of the memory details to the memory controller.
126 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
127 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
128 * Those memories are labed as "PC2-" instead of "PC" to
129 * differenciate from DDR.
130 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
132 * Those memories are accessed per DIMM slot, and not by
133 * a chip select signal.
134 * @MEM_RDDR2: Registered DDR2 RAM
135 * This is a variant of the DDR2 memories.
136 * @MEM_XDR: Rambus XDR
137 * It is an evolution of the original RAMBUS memories,
138 * created to compete with DDR2. Weren't used on any
139 * x86 arch, but cell_edac PPC memory controller uses it.
140 * @MEM_DDR3: DDR3 RAM
141 * @MEM_RDDR3: Registered DDR3 RAM
142 * This is a variant of the DDR3 memories.
164 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
165 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
166 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
167 #define MEM_FLAG_FPM BIT(MEM_FPM)
168 #define MEM_FLAG_EDO BIT(MEM_EDO)
169 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
170 #define MEM_FLAG_SDR BIT(MEM_SDR)
171 #define MEM_FLAG_RDR BIT(MEM_RDR)
172 #define MEM_FLAG_DDR BIT(MEM_DDR)
173 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
174 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
175 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
176 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
177 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
178 #define MEM_FLAG_XDR BIT(MEM_XDR)
179 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
180 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
183 * enum edac-type - Error Detection and Correction capabilities and mode
184 * @EDAC_UNKNOWN: Unknown if ECC is available
185 * @EDAC_NONE: Doesn't support ECC
186 * @EDAC_RESERVED: Reserved ECC type
187 * @EDAC_PARITY: Detects parity errors
188 * @EDAC_EC: Error Checking - no correction
189 * @EDAC_SECDED: Single bit error correction, Double detection
190 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
191 * @EDAC_S4ECD4ED: Chipkill x4 devices
192 * @EDAC_S8ECD8ED: Chipkill x8 devices
193 * @EDAC_S16ECD16ED: Chipkill x16 devices
208 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
209 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
210 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
211 #define EDAC_FLAG_EC BIT(EDAC_EC)
212 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
213 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
214 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
215 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
216 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
219 * enum scrub_type - scrubbing capabilities
220 * @SCRUB_UNKNOWN Unknown if scrubber is available
221 * @SCRUB_NONE: No scrubber
222 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
223 * @SCRUB_SW_SRC: Software scrub only errors
224 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
225 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
226 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
227 * @SCRUB_HW_SRC: Hardware scrub only errors
228 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
229 * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
244 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
245 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
246 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
247 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
248 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
249 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
250 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
251 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
253 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
255 /* EDAC internal operation states */
256 #define OP_ALLOC 0x100
257 #define OP_RUNNING_POLL 0x201
258 #define OP_RUNNING_INTERRUPT 0x202
259 #define OP_RUNNING_POLL_INTR 0x203
260 #define OP_OFFLINE 0x300
263 * Concepts used at the EDAC subsystem
265 * There are several things to be aware of that aren't at all obvious:
267 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
269 * These are some of the many terms that are thrown about that don't always
270 * mean what people think they mean (Inconceivable!). In the interest of
271 * creating a common ground for discussion, terms and their definitions
272 * will be established.
274 * Memory devices: The individual DRAM chips on a memory stick. These
275 * devices commonly output 4 and 8 bits each (x4, x8).
276 * Grouping several of these in parallel provides the
277 * number of bits that the memory controller expects:
278 * typically 72 bits, in order to provide 64 bits +
279 * 8 bits of ECC data.
281 * Memory Stick: A printed circuit board that aggregates multiple
282 * memory devices in parallel. In general, this is the
283 * Field Replaceable Unit (FRU) which gets replaced, in
284 * the case of excessive errors. Most often it is also
285 * called DIMM (Dual Inline Memory Module).
287 * Memory Socket: A physical connector on the motherboard that accepts
288 * a single memory stick. Also called as "slot" on several
291 * Channel: A memory controller channel, responsible to communicate
292 * with a group of DIMMs. Each channel has its own
293 * independent control (command) and data bus, and can
294 * be used independently or grouped with other channels.
296 * Branch: It is typically the highest hierarchy on a
297 * Fully-Buffered DIMM memory controller.
298 * Typically, it contains two channels.
299 * Two channels at the same branch can be used in single
300 * mode or in lockstep mode.
301 * When lockstep is enabled, the cacheline is doubled,
302 * but it generally brings some performance penalty.
303 * Also, it is generally not possible to point to just one
304 * memory stick when an error occurs, as the error
305 * correction code is calculated using two DIMMs instead
306 * of one. Due to that, it is capable of correcting more
307 * errors than on single mode.
309 * Single-channel: The data accessed by the memory controller is contained
310 * into one dimm only. E. g. if the data is 64 bits-wide,
311 * the data flows to the CPU using one 64 bits parallel
313 * Typically used with SDR, DDR, DDR2 and DDR3 memories.
314 * FB-DIMM and RAMBUS use a different concept for channel,
315 * so this concept doesn't apply there.
317 * Double-channel: The data size accessed by the memory controller is
318 * interlaced into two dimms, accessed at the same time.
319 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
320 * the data flows to the CPU using a 128 bits parallel
323 * Chip-select row: This is the name of the DRAM signal used to select the
324 * DRAM ranks to be accessed. Common chip-select rows for
325 * single channel are 64 bits, for dual channel 128 bits.
326 * It may not be visible by the memory controller, as some
327 * DIMM types have a memory buffer that can hide direct
328 * access to it from the Memory Controller.
330 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
331 * Motherboards commonly drive two chip-select pins to
332 * a memory stick. A single-ranked stick, will occupy
333 * only one of those rows. The other will be unused.
335 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
336 * access different sets of memory devices. The two
337 * rows cannot be accessed concurrently.
339 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
340 * A double-sided stick has two chip-select rows which
341 * access different sets of memory devices. The two
342 * rows cannot be accessed concurrently. "Double-sided"
343 * is irrespective of the memory devices being mounted
344 * on both sides of the memory stick.
346 * Socket set: All of the memory sticks that are required for
347 * a single memory access or all of the memory sticks
348 * spanned by a chip-select row. A single socket set
349 * has two chip-select rows and if double-sided sticks
350 * are used these will occupy those chip-select rows.
352 * Bank: This term is avoided because it is unclear when
353 * needing to distinguish between chip-select rows and
363 * STRUCTURE ORGANIZATION AND CHOICES
367 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
371 * enum edac_mc_layer - memory controller hierarchy layer
373 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
374 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
375 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
376 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
378 * This enum is used by the drivers to tell edac_mc_sysfs what name should
379 * be used when describing a memory stick location.
381 enum edac_mc_layer_type {
382 EDAC_MC_LAYER_BRANCH,
383 EDAC_MC_LAYER_CHANNEL,
385 EDAC_MC_LAYER_CHIP_SELECT,
389 * struct edac_mc_layer - describes the memory controller hierarchy
391 * @size: number of components per layer. For example,
392 * if the channel layer has two channels, size = 2
393 * @is_virt_csrow: This layer is part of the "csrow" when old API
394 * compatibility mode is enabled. Otherwise, it is
397 struct edac_mc_layer {
398 enum edac_mc_layer_type type;
404 * Maximum number of layers used by the memory controller to uniquely
405 * identify a single memory stick.
406 * NOTE: Changing this constant requires not only to change the constant
407 * below, but also to change the existing code at the core, as there are
408 * some code there that are optimized for 3 layers.
410 #define EDAC_MAX_LAYERS 3
413 * EDAC_DIMM_PTR - Macro responsible to find a pointer inside a pointer array
414 * for the element given by [layer0,layer1,layer2] position
416 * @layers: a struct edac_mc_layer array, describing how many elements
417 * were allocated for each layer
418 * @var: name of the var where we want to get the pointer
420 * @n_layers: Number of layers at the @layers array
421 * @layer0: layer0 position
422 * @layer1: layer1 position. Unused if n_layers < 2
423 * @layer2: layer2 position. Unused if n_layers < 3
425 * For 1 layer, this macro returns &var[layer0]
426 * For 2 layers, this macro is similar to allocate a bi-dimensional array
427 * and to return "&var[layer0][layer1]"
428 * For 3 layers, this macro is similar to allocate a tri-dimensional array
429 * and to return "&var[layer0][layer1][layer2]"
431 * A loop could be used here to make it more generic, but, as we only have
432 * 3 layers, this is a little faster.
433 * By design, layers can never be 0 or more than 3. If that ever happens,
434 * a NULL is returned, causing an OOPS during the memory allocation routine,
435 * with would point to the developer that he's doing something wrong.
437 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
439 if ((nlayers) == 1) \
440 __p = &var[layer0]; \
441 else if ((nlayers) == 2) \
442 __p = &var[(layer1) + ((layers[1]).size * (layer0))]; \
443 else if ((nlayers) == 3) \
444 __p = &var[(layer2) + ((layers[2]).size * ((layer1) + \
445 ((layers[1]).size * (layer0))))]; \
452 /* FIXME: add the proper per-location error counts */
454 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
456 /* Memory location data */
457 unsigned location[EDAC_MAX_LAYERS];
459 struct mem_ctl_info *mci; /* the parent */
461 u32 grain; /* granularity of reported error in bytes */
462 enum dev_type dtype; /* memory device type */
463 enum mem_type mtype; /* memory dimm type */
464 enum edac_type edac_mode; /* EDAC mode for this dimm */
466 u32 nr_pages; /* number of pages on this dimm */
468 unsigned csrow, cschannel; /* Points to the old API data */
472 * struct rank_info - contains the information for one DIMM rank
474 * @chan_idx: channel number where the rank is (typically, 0 or 1)
475 * @ce_count: number of correctable errors for this rank
476 * @csrow: A pointer to the chip select row structure (the parent
477 * structure). The location of the rank is given by
478 * the (csrow->csrow_idx, chan_idx) vector.
479 * @dimm: A pointer to the DIMM structure, where the DIMM label
480 * information is stored.
482 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
483 * This is a bad assumption, but it makes this patch easier. Later
484 * patches in this series will fix this issue.
488 struct csrow_info *csrow;
489 struct dimm_info *dimm;
491 u32 ce_count; /* Correctable Errors for this csrow */
495 /* Used only by edac_mc_find_csrow_by_page() */
496 unsigned long first_page; /* first page number in csrow */
497 unsigned long last_page; /* last page number in csrow */
498 unsigned long page_mask; /* used for interleaving -
499 * 0UL for non intlv */
501 int csrow_idx; /* the chip-select row */
503 u32 ue_count; /* Uncorrectable Errors for this csrow */
504 u32 ce_count; /* Correctable Errors for this csrow */
506 struct mem_ctl_info *mci; /* the parent */
508 struct kobject kobj; /* sysfs kobject for this csrow */
510 /* channel information for this csrow */
512 struct rank_info *channels;
515 struct mcidev_sysfs_group {
516 const char *name; /* group name */
517 const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
520 struct mcidev_sysfs_group_kobj {
521 struct list_head list; /* list for all instances within a mc */
523 struct kobject kobj; /* kobj for the group */
525 const struct mcidev_sysfs_group *grp; /* group description table */
526 struct mem_ctl_info *mci; /* the parent */
529 /* mcidev_sysfs_attribute structure
530 * used for driver sysfs attributes and in mem_ctl_info
531 * sysfs top level entries
533 struct mcidev_sysfs_attribute {
534 /* It should use either attr or grp */
535 struct attribute attr;
536 const struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
538 /* Ops for show/store values at the attribute - not used on group */
539 ssize_t (*show)(struct mem_ctl_info *,char *);
540 ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
543 /* MEMORY controller information structure
545 struct mem_ctl_info {
546 struct list_head link; /* for global list of mem_ctl_info structs */
548 struct module *owner; /* Module owner of this control struct */
550 unsigned long mtype_cap; /* memory types supported by mc */
551 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
552 unsigned long edac_cap; /* configuration capabilities - this is
553 * closely related to edac_ctl_cap. The
554 * difference is that the controller may be
555 * capable of s4ecd4ed which would be listed
556 * in edac_ctl_cap, but if channels aren't
557 * capable of s4ecd4ed then the edac_cap would
558 * not have that capability.
560 unsigned long scrub_cap; /* chipset scrub capabilities */
561 enum scrub_type scrub_mode; /* current scrub mode */
563 /* Translates sdram memory scrub rate given in bytes/sec to the
564 internal representation and configures whatever else needs
567 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
569 /* Get the current sdram memory scrub rate from the internal
570 representation and converts it to the closest matching
571 bandwidth in bytes/sec.
573 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
576 /* pointer to edac checking routine */
577 void (*edac_check) (struct mem_ctl_info * mci);
580 * Remaps memory pages: controller pages to physical pages.
581 * For most MC's, this will be NULL.
583 /* FIXME - why not send the phys page to begin with? */
584 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
587 struct csrow_info *csrows;
588 unsigned nr_csrows, num_cschannel;
590 /* Memory Controller hierarchy */
592 struct edac_mc_layer *layers;
593 bool mem_is_per_rank;
596 * DIMM info. Will eventually remove the entire csrows_info some day
599 struct dimm_info *dimms;
602 * FIXME - what about controllers on other busses? - IDs must be
603 * unique. dev pointer should be sufficiently unique, but
604 * BUS:SLOT.FUNC numbers may not be unique.
607 const char *mod_name;
609 const char *ctl_name;
610 const char *dev_name;
611 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
613 unsigned long start_time; /* mci load start time (in jiffies) */
616 * drivers shouldn't access those fields directly, as the core
617 * already handles that.
619 u32 ce_noinfo_count, ue_noinfo_count;
621 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
623 struct completion complete;
625 /* edac sysfs device control */
626 struct kobject edac_mci_kobj;
628 /* list for all grp instances within a mc */
629 struct list_head grp_kobj_list;
631 /* Additional top controller level attributes, but specified
632 * by the low level driver.
634 * Set by the low level driver to provide attributes at the
636 * An array of structures, NULL terminated
638 * If attributes are desired, then set to array of attributes
639 * If no attributes are desired, leave NULL
641 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
643 /* work struct for this MC */
644 struct delayed_work work;
646 /* the internal state of this controller instance */