4 * Author: Dave Jiang <djiang@mvista.com>
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_
15 #include <linux/atomic.h>
16 #include <linux/device.h>
17 #include <linux/completion.h>
18 #include <linux/workqueue.h>
19 #include <linux/debugfs.h>
23 #define EDAC_OPSTATE_INVAL -1
24 #define EDAC_OPSTATE_POLL 0
25 #define EDAC_OPSTATE_NMI 1
26 #define EDAC_OPSTATE_INT 2
28 extern int edac_op_state;
29 extern int edac_err_assert;
30 extern atomic_t edac_handlers;
32 extern int edac_handler_set(void);
33 extern void edac_atomic_assert_error(void);
34 extern struct bus_type *edac_get_sysfs_subsys(void);
37 EDAC_REPORTING_ENABLED,
38 EDAC_REPORTING_DISABLED,
42 extern int edac_report_status;
44 static inline int get_edac_report_status(void)
46 return edac_report_status;
49 static inline void set_edac_report_status(int new)
51 edac_report_status = new;
54 static inline int get_edac_report_status(void)
56 return EDAC_REPORTING_DISABLED;
59 static inline void set_edac_report_status(int new)
64 static inline void opstate_init(void)
66 switch (edac_op_state) {
67 case EDAC_OPSTATE_POLL:
68 case EDAC_OPSTATE_NMI:
71 edac_op_state = EDAC_OPSTATE_POLL;
76 /* Max length of a DIMM label*/
77 #define EDAC_MC_LABEL_LEN 31
79 /* Maximum size of the location string */
80 #define LOCATION_SIZE 256
82 /* Defines the maximum number of labels that can be reported */
83 #define EDAC_MAX_LABELS 8
85 /* String used to join two or more labels */
86 #define OTHER_LABEL " or "
89 * enum dev_type - describe the type of memory DRAM chips used at the stick
90 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
91 * @DEV_X1: 1 bit for data
92 * @DEV_X2: 2 bits for data
93 * @DEV_X4: 4 bits for data
94 * @DEV_X8: 8 bits for data
95 * @DEV_X16: 16 bits for data
96 * @DEV_X32: 32 bits for data
97 * @DEV_X64: 64 bits for data
99 * Typical values are x4 and x8.
108 DEV_X32, /* Do these parts exist? */
109 DEV_X64 /* Do these parts exist? */
112 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
113 #define DEV_FLAG_X1 BIT(DEV_X1)
114 #define DEV_FLAG_X2 BIT(DEV_X2)
115 #define DEV_FLAG_X4 BIT(DEV_X4)
116 #define DEV_FLAG_X8 BIT(DEV_X8)
117 #define DEV_FLAG_X16 BIT(DEV_X16)
118 #define DEV_FLAG_X32 BIT(DEV_X32)
119 #define DEV_FLAG_X64 BIT(DEV_X64)
122 * enum hw_event_mc_err_type - type of the detected error
124 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
125 * corrected error was detected
126 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
127 * can't be corrected by ECC, but it is not
128 * fatal (maybe it is on an unused memory area,
129 * or the memory controller could recover from
130 * it for example, by re-trying the operation).
131 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
134 enum hw_event_mc_err_type {
135 HW_EVENT_ERR_CORRECTED,
136 HW_EVENT_ERR_UNCORRECTED,
137 HW_EVENT_ERR_DEFERRED,
142 static inline char *mc_event_error_type(const unsigned int err_type)
145 case HW_EVENT_ERR_CORRECTED:
147 case HW_EVENT_ERR_UNCORRECTED:
148 return "Uncorrected";
149 case HW_EVENT_ERR_DEFERRED:
151 case HW_EVENT_ERR_FATAL:
154 case HW_EVENT_ERR_INFO:
160 * enum mem_type - memory types. For a more detailed reference, please see
161 * http://en.wikipedia.org/wiki/DRAM
163 * @MEM_EMPTY Empty csrow
164 * @MEM_RESERVED: Reserved csrow type
165 * @MEM_UNKNOWN: Unknown csrow type
166 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
167 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
168 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
169 * @MEM_SDR: SDR - Single data rate SDRAM
170 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
171 * They use 3 pins for chip select: Pins 0 and 2 are
172 * for rank 0; pins 1 and 3 are for rank 1, if the memory
174 * @MEM_RDR: Registered SDR SDRAM
175 * @MEM_DDR: Double data rate SDRAM
176 * http://en.wikipedia.org/wiki/DDR_SDRAM
177 * @MEM_RDDR: Registered Double data rate SDRAM
178 * This is a variant of the DDR memories.
179 * A registered memory has a buffer inside it, hiding
180 * part of the memory details to the memory controller.
181 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
182 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
183 * Those memories are labed as "PC2-" instead of "PC" to
184 * differenciate from DDR.
185 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
187 * Those memories are accessed per DIMM slot, and not by
188 * a chip select signal.
189 * @MEM_RDDR2: Registered DDR2 RAM
190 * This is a variant of the DDR2 memories.
191 * @MEM_XDR: Rambus XDR
192 * It is an evolution of the original RAMBUS memories,
193 * created to compete with DDR2. Weren't used on any
194 * x86 arch, but cell_edac PPC memory controller uses it.
195 * @MEM_DDR3: DDR3 RAM
196 * @MEM_RDDR3: Registered DDR3 RAM
197 * This is a variant of the DDR3 memories.
198 * @MEM_LRDDR3: Load-Reduced DDR3 memory.
199 * @MEM_DDR4: Unbuffered DDR4 RAM
200 * @MEM_RDDR4: Registered DDR4 RAM
201 * This is a variant of the DDR4 memories.
202 * @MEM_LRDDR4: Load-Reduced DDR4 memory.
228 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
229 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
230 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
231 #define MEM_FLAG_FPM BIT(MEM_FPM)
232 #define MEM_FLAG_EDO BIT(MEM_EDO)
233 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
234 #define MEM_FLAG_SDR BIT(MEM_SDR)
235 #define MEM_FLAG_RDR BIT(MEM_RDR)
236 #define MEM_FLAG_DDR BIT(MEM_DDR)
237 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
238 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
239 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
240 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
241 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
242 #define MEM_FLAG_XDR BIT(MEM_XDR)
243 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
244 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
245 #define MEM_FLAG_DDR4 BIT(MEM_DDR4)
246 #define MEM_FLAG_RDDR4 BIT(MEM_RDDR4)
247 #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4)
250 * enum edac-type - Error Detection and Correction capabilities and mode
251 * @EDAC_UNKNOWN: Unknown if ECC is available
252 * @EDAC_NONE: Doesn't support ECC
253 * @EDAC_RESERVED: Reserved ECC type
254 * @EDAC_PARITY: Detects parity errors
255 * @EDAC_EC: Error Checking - no correction
256 * @EDAC_SECDED: Single bit error correction, Double detection
257 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
258 * @EDAC_S4ECD4ED: Chipkill x4 devices
259 * @EDAC_S8ECD8ED: Chipkill x8 devices
260 * @EDAC_S16ECD16ED: Chipkill x16 devices
275 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
276 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
277 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
278 #define EDAC_FLAG_EC BIT(EDAC_EC)
279 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
280 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
281 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
282 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
283 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
286 * enum scrub_type - scrubbing capabilities
287 * @SCRUB_UNKNOWN Unknown if scrubber is available
288 * @SCRUB_NONE: No scrubber
289 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
290 * @SCRUB_SW_SRC: Software scrub only errors
291 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
292 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
293 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
294 * @SCRUB_HW_SRC: Hardware scrub only errors
295 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
296 * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
311 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
312 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
313 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
314 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
315 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
316 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
317 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
318 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
320 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
322 /* EDAC internal operation states */
323 #define OP_ALLOC 0x100
324 #define OP_RUNNING_POLL 0x201
325 #define OP_RUNNING_INTERRUPT 0x202
326 #define OP_RUNNING_POLL_INTR 0x203
327 #define OP_OFFLINE 0x300
330 * Concepts used at the EDAC subsystem
332 * There are several things to be aware of that aren't at all obvious:
334 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
336 * These are some of the many terms that are thrown about that don't always
337 * mean what people think they mean (Inconceivable!). In the interest of
338 * creating a common ground for discussion, terms and their definitions
339 * will be established.
341 * Memory devices: The individual DRAM chips on a memory stick. These
342 * devices commonly output 4 and 8 bits each (x4, x8).
343 * Grouping several of these in parallel provides the
344 * number of bits that the memory controller expects:
345 * typically 72 bits, in order to provide 64 bits +
346 * 8 bits of ECC data.
348 * Memory Stick: A printed circuit board that aggregates multiple
349 * memory devices in parallel. In general, this is the
350 * Field Replaceable Unit (FRU) which gets replaced, in
351 * the case of excessive errors. Most often it is also
352 * called DIMM (Dual Inline Memory Module).
354 * Memory Socket: A physical connector on the motherboard that accepts
355 * a single memory stick. Also called as "slot" on several
358 * Channel: A memory controller channel, responsible to communicate
359 * with a group of DIMMs. Each channel has its own
360 * independent control (command) and data bus, and can
361 * be used independently or grouped with other channels.
363 * Branch: It is typically the highest hierarchy on a
364 * Fully-Buffered DIMM memory controller.
365 * Typically, it contains two channels.
366 * Two channels at the same branch can be used in single
367 * mode or in lockstep mode.
368 * When lockstep is enabled, the cacheline is doubled,
369 * but it generally brings some performance penalty.
370 * Also, it is generally not possible to point to just one
371 * memory stick when an error occurs, as the error
372 * correction code is calculated using two DIMMs instead
373 * of one. Due to that, it is capable of correcting more
374 * errors than on single mode.
376 * Single-channel: The data accessed by the memory controller is contained
377 * into one dimm only. E. g. if the data is 64 bits-wide,
378 * the data flows to the CPU using one 64 bits parallel
380 * Typically used with SDR, DDR, DDR2 and DDR3 memories.
381 * FB-DIMM and RAMBUS use a different concept for channel,
382 * so this concept doesn't apply there.
384 * Double-channel: The data size accessed by the memory controller is
385 * interlaced into two dimms, accessed at the same time.
386 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
387 * the data flows to the CPU using a 128 bits parallel
390 * Chip-select row: This is the name of the DRAM signal used to select the
391 * DRAM ranks to be accessed. Common chip-select rows for
392 * single channel are 64 bits, for dual channel 128 bits.
393 * It may not be visible by the memory controller, as some
394 * DIMM types have a memory buffer that can hide direct
395 * access to it from the Memory Controller.
397 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
398 * Motherboards commonly drive two chip-select pins to
399 * a memory stick. A single-ranked stick, will occupy
400 * only one of those rows. The other will be unused.
402 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
403 * access different sets of memory devices. The two
404 * rows cannot be accessed concurrently.
406 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
407 * A double-sided stick has two chip-select rows which
408 * access different sets of memory devices. The two
409 * rows cannot be accessed concurrently. "Double-sided"
410 * is irrespective of the memory devices being mounted
411 * on both sides of the memory stick.
413 * Socket set: All of the memory sticks that are required for
414 * a single memory access or all of the memory sticks
415 * spanned by a chip-select row. A single socket set
416 * has two chip-select rows and if double-sided sticks
417 * are used these will occupy those chip-select rows.
419 * Bank: This term is avoided because it is unclear when
420 * needing to distinguish between chip-select rows and
430 * STRUCTURE ORGANIZATION AND CHOICES
434 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
438 * enum edac_mc_layer - memory controller hierarchy layer
440 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
441 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
442 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
443 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
444 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
445 * as a single memory area. This is used when
446 * retrieving errors from a firmware driven driver.
448 * This enum is used by the drivers to tell edac_mc_sysfs what name should
449 * be used when describing a memory stick location.
451 enum edac_mc_layer_type {
452 EDAC_MC_LAYER_BRANCH,
453 EDAC_MC_LAYER_CHANNEL,
455 EDAC_MC_LAYER_CHIP_SELECT,
456 EDAC_MC_LAYER_ALL_MEM,
460 * struct edac_mc_layer - describes the memory controller hierarchy
462 * @size: number of components per layer. For example,
463 * if the channel layer has two channels, size = 2
464 * @is_virt_csrow: This layer is part of the "csrow" when old API
465 * compatibility mode is enabled. Otherwise, it is
468 struct edac_mc_layer {
469 enum edac_mc_layer_type type;
475 * Maximum number of layers used by the memory controller to uniquely
476 * identify a single memory stick.
477 * NOTE: Changing this constant requires not only to change the constant
478 * below, but also to change the existing code at the core, as there are
479 * some code there that are optimized for 3 layers.
481 #define EDAC_MAX_LAYERS 3
484 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array
485 * for the element given by [layer0,layer1,layer2] position
487 * @layers: a struct edac_mc_layer array, describing how many elements
488 * were allocated for each layer
489 * @n_layers: Number of layers at the @layers array
490 * @layer0: layer0 position
491 * @layer1: layer1 position. Unused if n_layers < 2
492 * @layer2: layer2 position. Unused if n_layers < 3
494 * For 1 layer, this macro returns &var[layer0] - &var
495 * For 2 layers, this macro is similar to allocate a bi-dimensional array
496 * and to return "&var[layer0][layer1] - &var"
497 * For 3 layers, this macro is similar to allocate a tri-dimensional array
498 * and to return "&var[layer0][layer1][layer2] - &var"
500 * A loop could be used here to make it more generic, but, as we only have
501 * 3 layers, this is a little faster.
502 * By design, layers can never be 0 or more than 3. If that ever happens,
503 * a NULL is returned, causing an OOPS during the memory allocation routine,
504 * with would point to the developer that he's doing something wrong.
506 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
508 if ((nlayers) == 1) \
510 else if ((nlayers) == 2) \
511 __i = (layer1) + ((layers[1]).size * (layer0)); \
512 else if ((nlayers) == 3) \
513 __i = (layer2) + ((layers[2]).size * ((layer1) + \
514 ((layers[1]).size * (layer0)))); \
521 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
522 * for the element given by [layer0,layer1,layer2] position
524 * @layers: a struct edac_mc_layer array, describing how many elements
525 * were allocated for each layer
526 * @var: name of the var where we want to get the pointer
528 * @n_layers: Number of layers at the @layers array
529 * @layer0: layer0 position
530 * @layer1: layer1 position. Unused if n_layers < 2
531 * @layer2: layer2 position. Unused if n_layers < 3
533 * For 1 layer, this macro returns &var[layer0]
534 * For 2 layers, this macro is similar to allocate a bi-dimensional array
535 * and to return "&var[layer0][layer1]"
536 * For 3 layers, this macro is similar to allocate a tri-dimensional array
537 * and to return "&var[layer0][layer1][layer2]"
539 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
541 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
552 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
554 /* Memory location data */
555 unsigned location[EDAC_MAX_LAYERS];
557 struct mem_ctl_info *mci; /* the parent */
559 u32 grain; /* granularity of reported error in bytes */
560 enum dev_type dtype; /* memory device type */
561 enum mem_type mtype; /* memory dimm type */
562 enum edac_type edac_mode; /* EDAC mode for this dimm */
564 u32 nr_pages; /* number of pages on this dimm */
566 unsigned csrow, cschannel; /* Points to the old API data */
570 * struct rank_info - contains the information for one DIMM rank
572 * @chan_idx: channel number where the rank is (typically, 0 or 1)
573 * @ce_count: number of correctable errors for this rank
574 * @csrow: A pointer to the chip select row structure (the parent
575 * structure). The location of the rank is given by
576 * the (csrow->csrow_idx, chan_idx) vector.
577 * @dimm: A pointer to the DIMM structure, where the DIMM label
578 * information is stored.
580 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
581 * This is a bad assumption, but it makes this patch easier. Later
582 * patches in this series will fix this issue.
586 struct csrow_info *csrow;
587 struct dimm_info *dimm;
589 u32 ce_count; /* Correctable Errors for this csrow */
595 /* Used only by edac_mc_find_csrow_by_page() */
596 unsigned long first_page; /* first page number in csrow */
597 unsigned long last_page; /* last page number in csrow */
598 unsigned long page_mask; /* used for interleaving -
599 * 0UL for non intlv */
601 int csrow_idx; /* the chip-select row */
603 u32 ue_count; /* Uncorrectable Errors for this csrow */
604 u32 ce_count; /* Correctable Errors for this csrow */
606 struct mem_ctl_info *mci; /* the parent */
608 /* channel information for this csrow */
610 struct rank_info **channels;
614 * struct errcount_attribute - used to store the several error counts
616 struct errcount_attribute_data {
618 int pos[EDAC_MAX_LAYERS];
619 int layer0, layer1, layer2;
623 * edac_raw_error_desc - Raw error report structure
624 * @grain: minimum granularity for an error report, in bytes
625 * @error_count: number of errors of the same type
626 * @top_layer: top layer of the error (layer[0])
627 * @mid_layer: middle layer of the error (layer[1])
628 * @low_layer: low layer of the error (layer[2])
629 * @page_frame_number: page where the error happened
630 * @offset_in_page: page offset
631 * @syndrome: syndrome of the error (or 0 if unknown or if
632 * the syndrome is not applicable)
633 * @msg: error message
634 * @location: location of the error
635 * @label: label of the affected DIMM(s)
636 * @other_detail: other driver-specific detail about the error
637 * @enable_per_layer_report: if false, the error affects all layers
638 * (typically, a memory controller error)
640 struct edac_raw_error_desc {
642 * NOTE: everything before grain won't be cleaned by
643 * edac_raw_error_desc_clean()
645 char location[LOCATION_SIZE];
646 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
649 /* the vars below and grain will be cleaned on every new error report */
654 unsigned long page_frame_number;
655 unsigned long offset_in_page;
656 unsigned long syndrome;
658 const char *other_detail;
659 bool enable_per_layer_report;
662 /* MEMORY controller information structure
664 struct mem_ctl_info {
666 struct bus_type *bus;
668 struct list_head link; /* for global list of mem_ctl_info structs */
670 struct module *owner; /* Module owner of this control struct */
672 unsigned long mtype_cap; /* memory types supported by mc */
673 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
674 unsigned long edac_cap; /* configuration capabilities - this is
675 * closely related to edac_ctl_cap. The
676 * difference is that the controller may be
677 * capable of s4ecd4ed which would be listed
678 * in edac_ctl_cap, but if channels aren't
679 * capable of s4ecd4ed then the edac_cap would
680 * not have that capability.
682 unsigned long scrub_cap; /* chipset scrub capabilities */
683 enum scrub_type scrub_mode; /* current scrub mode */
685 /* Translates sdram memory scrub rate given in bytes/sec to the
686 internal representation and configures whatever else needs
689 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
691 /* Get the current sdram memory scrub rate from the internal
692 representation and converts it to the closest matching
693 bandwidth in bytes/sec.
695 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
698 /* pointer to edac checking routine */
699 void (*edac_check) (struct mem_ctl_info * mci);
702 * Remaps memory pages: controller pages to physical pages.
703 * For most MC's, this will be NULL.
705 /* FIXME - why not send the phys page to begin with? */
706 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
709 struct csrow_info **csrows;
710 unsigned nr_csrows, num_cschannel;
713 * Memory Controller hierarchy
715 * There are basically two types of memory controller: the ones that
716 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
717 * All old memory controllers enumerate memories per rank, but most
718 * of the recent drivers enumerate memories per DIMM, instead.
719 * When the memory controller is per rank, csbased is true.
722 struct edac_mc_layer *layers;
726 * DIMM info. Will eventually remove the entire csrows_info some day
729 struct dimm_info **dimms;
732 * FIXME - what about controllers on other busses? - IDs must be
733 * unique. dev pointer should be sufficiently unique, but
734 * BUS:SLOT.FUNC numbers may not be unique.
737 const char *mod_name;
739 const char *ctl_name;
740 const char *dev_name;
742 unsigned long start_time; /* mci load start time (in jiffies) */
745 * drivers shouldn't access those fields directly, as the core
746 * already handles that.
748 u32 ce_noinfo_count, ue_noinfo_count;
750 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
752 struct completion complete;
754 /* Additional top controller level attributes, but specified
755 * by the low level driver.
757 * Set by the low level driver to provide attributes at the
759 * An array of structures, NULL terminated
761 * If attributes are desired, then set to array of attributes
762 * If no attributes are desired, leave NULL
764 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
766 /* work struct for this MC */
767 struct delayed_work work;
770 * Used to report an error - by being at the global struct
771 * makes the memory allocated by the EDAC core
773 struct edac_raw_error_desc error_desc;
775 /* the internal state of this controller instance */
778 struct dentry *debugfs;
779 u8 fake_inject_layer[EDAC_MAX_LAYERS];
781 u16 fake_inject_count;
785 * Maximum number of memory controllers in the coherent fabric.
787 #define EDAC_MAX_MCS 16