1 #ifndef __LINUX_GPIO_DRIVER_H
2 #define __LINUX_GPIO_DRIVER_H
4 #include <linux/device.h>
5 #include <linux/types.h>
6 #include <linux/module.h>
8 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/lockdep.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/kconfig.h>
15 struct of_phandle_args;
23 * enum single_ended_mode - mode for single ended operation
24 * @LINE_MODE_PUSH_PULL: normal mode for a GPIO line, drive actively high/low
25 * @LINE_MODE_OPEN_DRAIN: set line to be open drain
26 * @LINE_MODE_OPEN_SOURCE: set line to be open source
28 enum single_ended_mode {
31 LINE_MODE_OPEN_SOURCE,
35 * struct gpio_chip - abstract a GPIO controller
36 * @label: a functional name for the GPIO device, such as a part
37 * number or the name of the SoC IP-block implementing it.
38 * @gpiodev: the internal state holder, opaque struct
39 * @parent: optional parent device providing the GPIOs
40 * @owner: helps prevent removal of modules exporting active GPIOs
41 * @request: optional hook for chip-specific activation, such as
42 * enabling module power and clock; may sleep
43 * @free: optional hook for chip-specific deactivation, such as
44 * disabling module power and clock; may sleep
45 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
46 * (same as GPIOF_DIR_XXX), or negative error
47 * @direction_input: configures signal "offset" as input, or returns error
48 * @direction_output: configures signal "offset" as output, or returns error
49 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
50 * @set: assigns output value for signal "offset"
51 * @set_multiple: assigns output values for multiple signals defined by "mask"
52 * @set_debounce: optional hook for setting debounce time for specified gpio in
53 * interrupt triggered gpio chips
54 * @set_single_ended: optional hook for setting a line as open drain, open
55 * source, or non-single ended (restore from open drain/source to normal
56 * push-pull mode) this should be implemented if the hardware supports
57 * open drain or open source settings. The GPIOlib will otherwise try
58 * to emulate open drain/source by not actively driving lines high/low
59 * if a consumer request this. The driver may return -ENOTSUPP if e.g.
60 * it supports just open drain but not open source and is called
61 * with LINE_MODE_OPEN_SOURCE as mode argument.
62 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
63 * implementation may not sleep
64 * @dbg_show: optional routine to show contents in debugfs; default code
65 * will be used when this is omitted, but custom code can show extra
66 * state (such as pullup/pulldown configuration).
67 * @base: identifies the first GPIO number handled by this chip;
68 * or, if negative during registration, requests dynamic ID allocation.
69 * DEPRECATION: providing anything non-negative and nailing the base
70 * offset of GPIO chips is deprecated. Please pass -1 as base to
71 * let gpiolib select the chip base in all possible cases. We want to
72 * get rid of the static GPIO number space in the long run.
73 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
74 * handled is (base + ngpio - 1).
75 * @names: if set, must be an array of strings to use as alternative
76 * names for the GPIOs in this chip. Any entry in the array
77 * may be NULL if there is no alias for the GPIO, however the
78 * array must be @ngpio entries long. A name can include a single printk
79 * format specifier for an unsigned int. It is substituted by the actual
81 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
82 * must while accessing GPIO expander chips over I2C or SPI. This
83 * implies that if the chip supports IRQs, these IRQs need to be threaded
84 * as the chip access may sleep when e.g. reading out the IRQ status
86 * @irq_not_threaded: flag must be set if @can_sleep is set but the
87 * IRQs don't need to be threaded
88 * @read_reg: reader function for generic GPIO
89 * @write_reg: writer function for generic GPIO
90 * @pin2mask: some generic GPIO controllers work with the big-endian bits
91 * notation, e.g. in a 8-bits register, GPIO7 is the least significant
92 * bit. This callback assigns the right bit mask.
93 * @reg_dat: data (in) register for generic GPIO
94 * @reg_set: output set register (out=high) for generic GPIO
95 * @reg_clk: output clear register (out=low) for generic GPIO
96 * @reg_dir: direction setting register for generic GPIO
97 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
98 * <register width> * 8
99 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
100 * shadowed and real data registers writes together.
101 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
103 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
105 * @irqchip: GPIO IRQ chip impl, provided by GPIO driver
106 * @irqdomain: Interrupt translation domain; responsible for mapping
107 * between GPIO hwirq number and linux irq number
108 * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
109 * @irq_handler: the irq handler to use (often a predefined irq core function)
110 * for GPIO IRQs, provided by GPIO driver
111 * @irq_default_type: default IRQ triggering type applied during GPIO driver
112 * initialization, provided by GPIO driver
113 * @irq_parent: GPIO IRQ chip parent/bank linux irq number,
114 * provided by GPIO driver
115 * @lock_key: per GPIO IRQ chip lockdep class
117 * A gpio_chip can help platforms abstract various sources of GPIOs so
118 * they can all be accessed through a common programing interface.
119 * Example sources would be SOC controllers, FPGAs, multifunction
120 * chips, dedicated GPIO expanders, and so on.
122 * Each chip controls a number of signals, identified in method calls
123 * by "offset" values in the range 0..(@ngpio - 1). When those signals
124 * are referenced through calls like gpio_get_value(gpio), the offset
125 * is calculated by subtracting @base from the gpio number.
129 struct gpio_device *gpiodev;
130 struct device *parent;
131 struct module *owner;
133 int (*request)(struct gpio_chip *chip,
135 void (*free)(struct gpio_chip *chip,
137 int (*get_direction)(struct gpio_chip *chip,
139 int (*direction_input)(struct gpio_chip *chip,
141 int (*direction_output)(struct gpio_chip *chip,
142 unsigned offset, int value);
143 int (*get)(struct gpio_chip *chip,
145 void (*set)(struct gpio_chip *chip,
146 unsigned offset, int value);
147 void (*set_multiple)(struct gpio_chip *chip,
149 unsigned long *bits);
150 int (*set_debounce)(struct gpio_chip *chip,
153 int (*set_single_ended)(struct gpio_chip *chip,
155 enum single_ended_mode mode);
157 int (*to_irq)(struct gpio_chip *chip,
160 void (*dbg_show)(struct seq_file *s,
161 struct gpio_chip *chip);
164 const char *const *names;
166 bool irq_not_threaded;
168 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
169 unsigned long (*read_reg)(void __iomem *reg);
170 void (*write_reg)(void __iomem *reg, unsigned long data);
171 unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
172 void __iomem *reg_dat;
173 void __iomem *reg_set;
174 void __iomem *reg_clr;
175 void __iomem *reg_dir;
177 spinlock_t bgpio_lock;
178 unsigned long bgpio_data;
179 unsigned long bgpio_dir;
182 #ifdef CONFIG_GPIOLIB_IRQCHIP
184 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
185 * to handle IRQs for most practical cases.
187 struct irq_chip *irqchip;
188 struct irq_domain *irqdomain;
189 unsigned int irq_base;
190 irq_flow_handler_t irq_handler;
191 unsigned int irq_default_type;
193 struct lock_class_key *lock_key;
196 #if defined(CONFIG_OF_GPIO)
198 * If CONFIG_OF is enabled, then all GPIO controllers described in the
199 * device tree automatically may have an OF translation
201 struct device_node *of_node;
203 int (*of_xlate)(struct gpio_chip *gc,
204 const struct of_phandle_args *gpiospec, u32 *flags);
208 extern const char *gpiochip_is_requested(struct gpio_chip *chip,
211 /* add/remove chips */
212 extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
213 static inline int gpiochip_add(struct gpio_chip *chip)
215 return gpiochip_add_data(chip, NULL);
217 extern void gpiochip_remove(struct gpio_chip *chip);
218 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
220 extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);
222 extern struct gpio_chip *gpiochip_find(void *data,
223 int (*match)(struct gpio_chip *chip, void *data));
225 /* lock/unlock as IRQ */
226 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
227 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
228 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
230 /* Line status inquiry for drivers */
231 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
232 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
234 /* get driver data */
235 void *gpiochip_get_data(struct gpio_chip *chip);
237 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
245 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
247 int bgpio_init(struct gpio_chip *gc, struct device *dev,
248 unsigned long sz, void __iomem *dat, void __iomem *set,
249 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
250 unsigned long flags);
252 #define BGPIOF_BIG_ENDIAN BIT(0)
253 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
254 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
255 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
256 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
257 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
261 #ifdef CONFIG_GPIOLIB_IRQCHIP
263 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
264 struct irq_chip *irqchip,
266 irq_flow_handler_t parent_handler);
268 int _gpiochip_irqchip_add(struct gpio_chip *gpiochip,
269 struct irq_chip *irqchip,
270 unsigned int first_irq,
271 irq_flow_handler_t handler,
273 struct lock_class_key *lock_key);
275 #ifdef CONFIG_LOCKDEP
276 #define gpiochip_irqchip_add(...) \
279 static struct lock_class_key _key; \
280 _gpiochip_irqchip_add(__VA_ARGS__, &_key); \
284 #define gpiochip_irqchip_add(...) \
285 _gpiochip_irqchip_add(__VA_ARGS__, NULL)
288 #endif /* CONFIG_GPIOLIB_IRQCHIP */
290 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
291 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
293 #ifdef CONFIG_PINCTRL
296 * struct gpio_pin_range - pin range controlled by a gpio chip
297 * @head: list for maintaining set of pin ranges, used internally
298 * @pctldev: pinctrl device which handles corresponding pins
299 * @range: actual range of pins controlled by a gpio controller
302 struct gpio_pin_range {
303 struct list_head node;
304 struct pinctrl_dev *pctldev;
305 struct pinctrl_gpio_range range;
308 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
309 unsigned int gpio_offset, unsigned int pin_offset,
311 int gpiochip_add_pingroup_range(struct gpio_chip *chip,
312 struct pinctrl_dev *pctldev,
313 unsigned int gpio_offset, const char *pin_group);
314 void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
319 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
320 unsigned int gpio_offset, unsigned int pin_offset,
326 gpiochip_add_pingroup_range(struct gpio_chip *chip,
327 struct pinctrl_dev *pctldev,
328 unsigned int gpio_offset, const char *pin_group)
334 gpiochip_remove_pin_ranges(struct gpio_chip *chip)
338 #endif /* CONFIG_PINCTRL */
340 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
342 void gpiochip_free_own_desc(struct gpio_desc *desc);
344 #else /* CONFIG_GPIOLIB */
346 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
348 /* GPIO can never have been requested */
350 return ERR_PTR(-ENODEV);
353 #endif /* CONFIG_GPIOLIB */