2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 #ifndef __LINUX_IPU_V3_H_
17 #define __LINUX_IPU_V3_H_
19 #include <linux/ipu.h>
21 /* IPU Driver channels definitions. */
22 /* Note these are different from IDMA channels */
24 #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
25 ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
26 #define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
27 #define IPU_CHAN_ID(ch) (ch >> 24)
28 #define IPU_CHAN_ALT(ch) (ch & 0x02000000)
29 #define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
30 #define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
31 #define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
32 #define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
36 * Enumeration of IPU logical channels. An IPU logical channel is defined as a
37 * combination of an input (memory to IPU), output (IPU to memory), and/or
38 * secondary input IDMA channels and in some cases an Image Converter task.
39 * Some channels consist of only an input or output.
43 MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48),
44 MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49),
45 MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50),
47 MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20),
48 MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21),
49 MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22),
51 MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
52 MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
53 MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
54 MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
56 MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
57 MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
58 MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
59 MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
61 DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
62 DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
64 CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0),
65 CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1),
66 CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2),
67 CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3),
71 CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20),
72 CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21),
74 /* for vdi mem->vdi->ic->mem , add graphics plane and alpha*/
75 MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21),
76 MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21),
77 MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21),
79 /* for vdi mem->vdi->mem */
80 MEM_VDI_MEM_P = _MAKE_CHAN(24, 8, NO_DMA, NO_DMA, 5),
81 MEM_VDI_MEM = _MAKE_CHAN(25, 9, NO_DMA, NO_DMA, 5),
82 MEM_VDI_MEM_N = _MAKE_CHAN(26, 10, NO_DMA, NO_DMA, 5),
84 /* fake channel for vdoa to link with IPU */
85 MEM_VDOA_MEM = _MAKE_CHAN(27, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
87 MEM_PP_ADC = CHAN_NONE,
93 * Enumeration of types of buffers for a logical channel.
96 IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */
97 IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */
98 IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */
99 IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */
100 IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
101 IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
104 #define IPU_PANEL_SERIAL 1
105 #define IPU_PANEL_PARALLEL 2
108 * Enumeration of ADC channel operation mode.
122 * Enumeration of ADC channel addressing mode.
128 } display_addressing_t;
131 * Union of initialization parameters for a logical channel.
144 uint32_t in_pixel_fmt;
147 uint32_t out_pixel_fmt;
148 uint32_t outh_resize_ratio;
149 uint32_t outv_resize_ratio;
158 uint32_t in_pixel_fmt;
161 uint32_t out_pixel_fmt;
162 uint32_t outh_resize_ratio;
163 uint32_t outv_resize_ratio;
168 uint32_t in_pixel_fmt;
171 uint32_t out_pixel_fmt;
176 uint32_t in_pixel_fmt;
179 uint32_t out_pixel_fmt;
180 uint32_t outh_resize_ratio;
181 uint32_t outv_resize_ratio;
182 bool graphics_combine_en;
183 bool global_alpha_en;
185 uint32_t in_g_pixel_fmt;
189 ipu_motion_sel motion_sel;
190 enum v4l2_field field_fmt;
199 uint32_t in_pixel_fmt;
202 uint32_t out_pixel_fmt;
203 bool graphics_combine_en;
204 bool global_alpha_en;
213 uint32_t in_pixel_fmt;
216 uint32_t out_pixel_fmt;
217 uint32_t outh_resize_ratio;
218 uint32_t outv_resize_ratio;
219 bool graphics_combine_en;
220 bool global_alpha_en;
222 uint32_t in_g_pixel_fmt;
226 ipu_motion_sel motion_sel;
227 enum v4l2_field field_fmt;
238 uint32_t in_pixel_fmt;
241 uint32_t out_pixel_fmt;
242 uint32_t outh_resize_ratio;
243 uint32_t outv_resize_ratio;
244 bool graphics_combine_en;
245 bool global_alpha_en;
247 uint32_t in_g_pixel_fmt;
258 uint32_t in_pixel_fmt;
261 uint32_t out_pixel_fmt;
262 bool graphics_combine_en;
263 bool global_alpha_en;
272 uint32_t in_pixel_fmt;
273 uint32_t out_pixel_fmt;
281 uint32_t in_pixel_fmt;
282 uint32_t out_pixel_fmt;
291 uint32_t in_pixel_fmt;
292 uint32_t out_pixel_fmt;
310 } ipu_channel_params_t;
313 * IPU_IRQF_ONESHOT - Interrupt is not reenabled after the irq handler finished.
315 #define IPU_IRQF_NONE 0x00000000
316 #define IPU_IRQF_ONESHOT 0x00000001
319 * Enumeration of IPU interrupt sources.
322 IPU_IRQ_CSI0_OUT_EOF = 0,
323 IPU_IRQ_CSI1_OUT_EOF = 1,
324 IPU_IRQ_CSI2_OUT_EOF = 2,
325 IPU_IRQ_CSI3_OUT_EOF = 3,
326 IPU_IRQ_VDIC_OUT_EOF = 5,
327 IPU_IRQ_VDI_P_IN_EOF = 8,
328 IPU_IRQ_VDI_C_IN_EOF = 9,
329 IPU_IRQ_VDI_N_IN_EOF = 10,
330 IPU_IRQ_PP_IN_EOF = 11,
331 IPU_IRQ_PRP_IN_EOF = 12,
332 IPU_IRQ_PRP_GRAPH_IN_EOF = 14,
333 IPU_IRQ_PP_GRAPH_IN_EOF = 15,
334 IPU_IRQ_PRP_ALPHA_IN_EOF = 17,
335 IPU_IRQ_PP_ALPHA_IN_EOF = 18,
336 IPU_IRQ_PRP_ENC_OUT_EOF = 20,
337 IPU_IRQ_PRP_VF_OUT_EOF = 21,
338 IPU_IRQ_PP_OUT_EOF = 22,
339 IPU_IRQ_BG_SYNC_EOF = 23,
340 IPU_IRQ_BG_ASYNC_EOF = 24,
341 IPU_IRQ_FG_SYNC_EOF = 27,
342 IPU_IRQ_DC_SYNC_EOF = 28,
343 IPU_IRQ_FG_ASYNC_EOF = 29,
344 IPU_IRQ_FG_ALPHA_SYNC_EOF = 31,
346 IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33,
347 IPU_IRQ_DC_READ_EOF = 40,
348 IPU_IRQ_DC_ASYNC_EOF = 41,
349 IPU_IRQ_DC_CMD1_EOF = 42,
350 IPU_IRQ_DC_CMD2_EOF = 43,
351 IPU_IRQ_DC_MASK_EOF = 44,
352 IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45,
353 IPU_IRQ_PRP_VF_ROT_IN_EOF = 46,
354 IPU_IRQ_PP_ROT_IN_EOF = 47,
355 IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48,
356 IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49,
357 IPU_IRQ_PP_ROT_OUT_EOF = 50,
358 IPU_IRQ_BG_ALPHA_SYNC_EOF = 51,
359 IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52,
361 IPU_IRQ_BG_SYNC_NFACK = 64 + 23,
362 IPU_IRQ_FG_SYNC_NFACK = 64 + 27,
363 IPU_IRQ_DC_SYNC_NFACK = 64 + 28,
365 IPU_IRQ_DP_SF_START = 448 + 2,
366 IPU_IRQ_DP_SF_END = 448 + 3,
367 IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END,
368 IPU_IRQ_DC_FC_0 = 448 + 8,
369 IPU_IRQ_DC_FC_1 = 448 + 9,
370 IPU_IRQ_DC_FC_2 = 448 + 10,
371 IPU_IRQ_DC_FC_3 = 448 + 11,
372 IPU_IRQ_DC_FC_4 = 448 + 12,
373 IPU_IRQ_DC_FC_6 = 448 + 13,
374 IPU_IRQ_VSYNC_PRE_0 = 448 + 14,
375 IPU_IRQ_VSYNC_PRE_1 = 448 + 15,
381 * Bitfield of Display Interface signal polarities.
384 unsigned datamask_en:1;
386 unsigned interlaced:1;
387 unsigned odd_field_first:1;
388 unsigned clksel_en:1;
389 unsigned clkidle_en:1;
390 unsigned data_pol:1; /* true = inverted */
391 unsigned clk_pol:1; /* true = rising edge */
392 unsigned enable_pol:1;
393 unsigned Hsync_pol:1; /* true = active high */
394 unsigned Vsync_pol:1;
395 } ipu_di_signal_cfg_t;
398 * Bitfield of CSI signal polarities and modes.
402 unsigned data_width:4;
404 unsigned ext_vsync:1;
405 unsigned Vsync_pol:1;
406 unsigned Hsync_pol:1;
407 unsigned pixclk_pol:1;
409 unsigned sens_clksrc:1;
410 unsigned pack_tight:1;
411 unsigned force_eof:1;
412 unsigned data_en_pol:1;
416 } ipu_csi_signal_cfg_t;
419 * Enumeration of CSI data bus widths.
422 IPU_CSI_DATA_WIDTH_4 = 0,
423 IPU_CSI_DATA_WIDTH_8 = 1,
424 IPU_CSI_DATA_WIDTH_10 = 3,
425 IPU_CSI_DATA_WIDTH_16 = 9,
429 * Enumeration of CSI clock modes.
432 IPU_CSI_CLK_MODE_GATED_CLK,
433 IPU_CSI_CLK_MODE_NONGATED_CLK,
434 IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
435 IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
436 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
437 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
438 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
439 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
456 * Enumeration of ADC vertical sync mode.
471 * Enumeration of ADC display update mode.
474 IPU_ADC_REFRESH_NONE,
475 IPU_ADC_AUTO_REFRESH,
476 IPU_ADC_AUTO_REFRESH_SNOOP,
478 } ipu_adc_update_mode_t;
481 * Enumeration of ADC display interface types (serial or parallel).
484 IPU_ADC_IFC_MODE_SYS80_TYPE1,
485 IPU_ADC_IFC_MODE_SYS80_TYPE2,
486 IPU_ADC_IFC_MODE_SYS68K_TYPE1,
487 IPU_ADC_IFC_MODE_SYS68K_TYPE2,
488 IPU_ADC_IFC_MODE_3WIRE_SERIAL,
489 IPU_ADC_IFC_MODE_4WIRE_SERIAL,
490 IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK,
491 IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS,
496 IPU_ADC_IFC_WIDTH_16,
500 * Enumeration of ADC display interface burst mode.
506 IPU_ADC_BURST_SERIAL,
510 * Enumeration of ADC display interface RW signal timing modes.
514 IPU_ADC_SER_RW_BEFORE_RS,
515 IPU_ADC_SER_RW_AFTER_RS,
519 * Bitfield of ADC signal polarities and modes.
528 unsigned write_pol:1;
529 unsigned Vsync_pol:1;
530 unsigned burst_pol:1;
531 unsigned burst_mode:2;
533 unsigned ifc_width:5;
534 unsigned ser_preamble_len:4;
535 unsigned ser_preamble:8;
536 unsigned ser_rw_mode:2;
540 * Enumeration of ADC template commands.
554 * Enumeration of ADC template command flow control.
563 /*Define template constants*/
564 #define ATM_ADDR_RANGE 0x20 /*offset address of DISP */
565 #define TEMPLATE_BUF_SIZE 0x20 /*size of template */
568 * Define to create ADC template command entry.
570 #define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \
571 ((oc) << 24) | (dat))
578 #define IPU_LPMC_REG_READ 0x80000000L
580 #define CSI_MCLK_VF 1
581 #define CSI_MCLK_ENC 2
582 #define CSI_MCLK_RAW 4
583 #define CSI_MCLK_I2C 8
587 struct ipu_soc *ipu_get_soc(int id);
588 int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
589 void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel);
590 void ipu_disable_hsp_clk(struct ipu_soc *ipu);
592 static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot)
594 #ifdef CONFIG_MXC_IPU_V3D
595 return (rot < IPU_ROTATE_HORIZ_FLIP);
597 return (rot < IPU_ROTATE_90_RIGHT);
601 int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
603 uint16_t width, uint16_t height,
605 ipu_rotate_mode_t rot_mode,
606 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
607 dma_addr_t phyaddr_2,
608 uint32_t u_offset, uint32_t v_offset);
610 int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
611 uint32_t bufNum, dma_addr_t phyaddr);
613 int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
615 uint16_t width, uint16_t height,
617 uint32_t u, uint32_t v,
618 uint32_t vertical_offset, uint32_t horizontal_offset);
620 int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
621 ipu_buffer_t type, uint32_t bufNum);
622 int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum);
624 int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
625 int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
627 int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel);
628 int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
630 void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
632 uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type);
633 int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel);
634 int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop);
635 int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch);
636 uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel);
638 int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi);
639 int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi);
641 int ipu_lowpwr_display_enable(void);
642 int ipu_lowpwr_display_disable(void);
644 int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq);
645 void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq);
646 void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq);
647 int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
648 irqreturn_t(*handler) (int, void *),
649 uint32_t irq_flags, const char *devname, void *dev_id);
650 void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id);
651 bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq);
652 void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
653 int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel,
654 ipu_buffer_t type, uint32_t band_height);
656 /* two stripe calculations */
658 unsigned int input_width; /* width of the input stripe */
659 unsigned int output_width; /* width of the output stripe */
660 unsigned int input_column; /* the first column on the input stripe */
661 unsigned int output_column; /* the first column on the output stripe */
663 /* inverse downisizing ratio parameter; expressed as a power of 2 */
665 /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */
667 int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
668 unsigned int output_frame_width,
669 const unsigned int maximal_stripe_width,
670 const unsigned long long cirr,
671 const unsigned int equal_stripes,
672 u32 input_pixelformat,
673 u32 output_pixelformat,
674 struct stripe_param *left,
675 struct stripe_param *right);
678 int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp,
680 uint16_t width, uint16_t height,
682 uint16_t h_start_width, uint16_t h_sync_width,
683 uint16_t h_end_width, uint16_t v_start_width,
684 uint16_t v_sync_width, uint16_t v_end_width,
685 uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
687 void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp);
689 int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos,
691 int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos,
693 int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
695 int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
697 int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
698 int constk[], int slopek[]);
700 int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
701 uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig);
702 void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset);
703 void ipu_reset_disp_panel(struct ipu_soc *ipu);
705 /* CMOS Sensor Interface API */
706 int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
707 uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig);
709 int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi);
711 int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait);
713 static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi,
714 bool flag, bool wait)
716 return ipu_csi_enable_mclk(ipu, csi, flag, wait);
719 int ipu_csi_read_mclk_flag(void);
721 void ipu_csi_flash_strobe(bool flag);
723 void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi);
725 void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi);
727 void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi);
729 uint32_t bytes_per_pixel(uint32_t fmt);
731 struct ipuv3_fb_platform_data {
733 u32 interface_pix_fmt;
739 resource_size_t res_base[2];
740 resource_size_t res_size[2];
743 * Late init to avoid display channel being
744 * re-initialized as we've probably setup the
745 * channel in bootloader.
750 #endif /* __LINUX_IPU_V3_H_ */