5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
27 #include <asm/ptrace.h>
28 #include <asm/irq_regs.h>
33 enum irqchip_irq_state;
38 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
40 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
48 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
54 * IRQ_TYPE_PROBE - Special flag for probing in progress
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
59 * bits are modified via irq_set_irq_type()
60 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
65 * IRQ_NOTHREAD - Interrupt cannot be threaded
66 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
70 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
71 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
72 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
77 IRQ_TYPE_NONE = 0x00000000,
78 IRQ_TYPE_EDGE_RISING = 0x00000001,
79 IRQ_TYPE_EDGE_FALLING = 0x00000002,
80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
81 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
82 IRQ_TYPE_LEVEL_LOW = 0x00000008,
83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
84 IRQ_TYPE_SENSE_MASK = 0x0000000f,
85 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
87 IRQ_TYPE_PROBE = 0x00000010,
90 IRQ_PER_CPU = (1 << 9),
91 IRQ_NOPROBE = (1 << 10),
92 IRQ_NOREQUEST = (1 << 11),
93 IRQ_NOAUTOEN = (1 << 12),
94 IRQ_NO_BALANCING = (1 << 13),
95 IRQ_MOVE_PCNTXT = (1 << 14),
96 IRQ_NESTED_THREAD = (1 << 15),
97 IRQ_NOTHREAD = (1 << 16),
98 IRQ_PER_CPU_DEVID = (1 << 17),
99 IRQ_IS_POLLED = (1 << 18),
102 #define IRQF_MODIFY_MASK \
103 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
104 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
105 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
108 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
111 * Return value for chip->irq_set_affinity()
113 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
114 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
115 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
116 * support stacked irqchips, which indicates skipping
117 * all descendent irqchips.
121 IRQ_SET_MASK_OK_NOCOPY,
122 IRQ_SET_MASK_OK_DONE,
129 * struct irq_common_data - per irq data shared by all irqchips
130 * @state_use_accessors: status information for irq chip functions.
131 * Use accessor functions to deal with it
133 struct irq_common_data {
134 unsigned int state_use_accessors;
138 * struct irq_data - per irq chip data passed down to chip functions
139 * @mask: precomputed bitmask for accessing the chip registers
140 * @irq: interrupt number
141 * @hwirq: hardware interrupt number, local to the interrupt domain
142 * @node: node index useful for balancing
143 * @common: point to data shared by all irqchips
144 * @chip: low level interrupt hardware access
145 * @domain: Interrupt translation domain; responsible for mapping
146 * between hwirq number and linux irq number.
147 * @parent_data: pointer to parent struct irq_data to support hierarchy
149 * @handler_data: per-IRQ data for the irq_chip methods
150 * @chip_data: platform-specific per-chip private data for the chip
151 * methods, to allow shared chip implementations
152 * @msi_desc: MSI descriptor
153 * @affinity: IRQ affinity on SMP
160 struct irq_common_data *common;
161 struct irq_chip *chip;
162 struct irq_domain *domain;
163 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
164 struct irq_data *parent_data;
168 struct msi_desc *msi_desc;
169 cpumask_var_t affinity;
173 * Bit masks for irq_common_data.state_use_accessors
175 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
176 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
177 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
178 * IRQD_PER_CPU - Interrupt is per cpu
179 * IRQD_AFFINITY_SET - Interrupt affinity was set
180 * IRQD_LEVEL - Interrupt is level triggered
181 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
183 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
185 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
186 * IRQD_IRQ_MASKED - Masked state of the interrupt
187 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
188 * IRQD_WAKEUP_ARMED - Wakeup mode armed
191 IRQD_TRIGGER_MASK = 0xf,
192 IRQD_SETAFFINITY_PENDING = (1 << 8),
193 IRQD_NO_BALANCING = (1 << 10),
194 IRQD_PER_CPU = (1 << 11),
195 IRQD_AFFINITY_SET = (1 << 12),
196 IRQD_LEVEL = (1 << 13),
197 IRQD_WAKEUP_STATE = (1 << 14),
198 IRQD_MOVE_PCNTXT = (1 << 15),
199 IRQD_IRQ_DISABLED = (1 << 16),
200 IRQD_IRQ_MASKED = (1 << 17),
201 IRQD_IRQ_INPROGRESS = (1 << 18),
202 IRQD_WAKEUP_ARMED = (1 << 19),
205 #define __irqd_to_state(d) ((d)->common->state_use_accessors)
207 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
209 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
212 static inline bool irqd_is_per_cpu(struct irq_data *d)
214 return __irqd_to_state(d) & IRQD_PER_CPU;
217 static inline bool irqd_can_balance(struct irq_data *d)
219 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
222 static inline bool irqd_affinity_was_set(struct irq_data *d)
224 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
227 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
229 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
232 static inline u32 irqd_get_trigger_type(struct irq_data *d)
234 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
238 * Must only be called inside irq_chip.irq_set_type() functions.
240 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
242 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
243 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
246 static inline bool irqd_is_level_type(struct irq_data *d)
248 return __irqd_to_state(d) & IRQD_LEVEL;
251 static inline bool irqd_is_wakeup_set(struct irq_data *d)
253 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
256 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
258 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
261 static inline bool irqd_irq_disabled(struct irq_data *d)
263 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
266 static inline bool irqd_irq_masked(struct irq_data *d)
268 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
271 static inline bool irqd_irq_inprogress(struct irq_data *d)
273 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
276 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
278 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
283 * Functions for chained handlers which can be enabled/disabled by the
284 * standard disable_irq/enable_irq calls. Must be called with
285 * irq_desc->lock held.
287 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
289 __irqd_to_state(d) |= IRQD_IRQ_INPROGRESS;
292 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
294 __irqd_to_state(d) &= ~IRQD_IRQ_INPROGRESS;
297 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
303 * struct irq_chip - hardware interrupt chip descriptor
305 * @name: name for /proc/interrupts
306 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
307 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
308 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
309 * @irq_disable: disable the interrupt
310 * @irq_ack: start of a new interrupt
311 * @irq_mask: mask an interrupt source
312 * @irq_mask_ack: ack and mask an interrupt source
313 * @irq_unmask: unmask an interrupt source
314 * @irq_eoi: end of interrupt
315 * @irq_set_affinity: set the CPU affinity on SMP machines
316 * @irq_retrigger: resend an IRQ to the CPU
317 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
318 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
319 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
320 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
321 * @irq_cpu_online: configure an interrupt source for a secondary CPU
322 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
323 * @irq_suspend: function called from core code on suspend once per
324 * chip, when one or more interrupts are installed
325 * @irq_resume: function called from core code on resume once per chip,
326 * when one ore more interrupts are installed
327 * @irq_pm_shutdown: function called from core code on shutdown once per chip
328 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
329 * @irq_print_chip: optional to print special chip info in show_interrupts
330 * @irq_request_resources: optional to request resources before calling
331 * any other callback related to this irq
332 * @irq_release_resources: optional to release resources acquired with
333 * irq_request_resources
334 * @irq_compose_msi_msg: optional to compose message content for MSI
335 * @irq_write_msi_msg: optional to write message content for MSI
336 * @irq_get_irqchip_state: return the internal state of an interrupt
337 * @irq_set_irqchip_state: set the internal state of a interrupt
338 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
339 * @flags: chip specific flags
343 unsigned int (*irq_startup)(struct irq_data *data);
344 void (*irq_shutdown)(struct irq_data *data);
345 void (*irq_enable)(struct irq_data *data);
346 void (*irq_disable)(struct irq_data *data);
348 void (*irq_ack)(struct irq_data *data);
349 void (*irq_mask)(struct irq_data *data);
350 void (*irq_mask_ack)(struct irq_data *data);
351 void (*irq_unmask)(struct irq_data *data);
352 void (*irq_eoi)(struct irq_data *data);
354 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
355 int (*irq_retrigger)(struct irq_data *data);
356 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
357 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
359 void (*irq_bus_lock)(struct irq_data *data);
360 void (*irq_bus_sync_unlock)(struct irq_data *data);
362 void (*irq_cpu_online)(struct irq_data *data);
363 void (*irq_cpu_offline)(struct irq_data *data);
365 void (*irq_suspend)(struct irq_data *data);
366 void (*irq_resume)(struct irq_data *data);
367 void (*irq_pm_shutdown)(struct irq_data *data);
369 void (*irq_calc_mask)(struct irq_data *data);
371 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
372 int (*irq_request_resources)(struct irq_data *data);
373 void (*irq_release_resources)(struct irq_data *data);
375 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
376 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
378 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
379 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
381 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
387 * irq_chip specific flags
389 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
390 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
391 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
392 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
394 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
395 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
396 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
399 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
400 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
401 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
402 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
403 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
404 IRQCHIP_ONESHOT_SAFE = (1 << 5),
405 IRQCHIP_EOI_THREADED = (1 << 6),
408 #include <linux/irqdesc.h>
411 * Pick up the arch-dependent methods:
413 #include <asm/hw_irq.h>
415 #ifndef NR_IRQS_LEGACY
416 # define NR_IRQS_LEGACY 0
419 #ifndef ARCH_IRQ_INIT_FLAGS
420 # define ARCH_IRQ_INIT_FLAGS 0
423 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
426 extern int setup_irq(unsigned int irq, struct irqaction *new);
427 extern void remove_irq(unsigned int irq, struct irqaction *act);
428 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
429 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
431 extern void irq_cpu_online(void);
432 extern void irq_cpu_offline(void);
433 extern int irq_set_affinity_locked(struct irq_data *data,
434 const struct cpumask *cpumask, bool force);
435 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
437 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
438 void irq_move_irq(struct irq_data *data);
439 void irq_move_masked_irq(struct irq_data *data);
441 static inline void irq_move_irq(struct irq_data *data) { }
442 static inline void irq_move_masked_irq(struct irq_data *data) { }
445 extern int no_irq_affinity;
447 #ifdef CONFIG_HARDIRQS_SW_RESEND
448 int irq_set_parent(int irq, int parent_irq);
450 static inline int irq_set_parent(int irq, int parent_irq)
457 * Built-in IRQ handlers for various IRQ types,
458 * callable via desc->handle_irq()
460 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
461 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
462 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
463 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
464 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
465 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
466 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
467 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
468 extern void handle_nested_irq(unsigned int irq);
470 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
471 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
472 extern void irq_chip_enable_parent(struct irq_data *data);
473 extern void irq_chip_disable_parent(struct irq_data *data);
474 extern void irq_chip_ack_parent(struct irq_data *data);
475 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
476 extern void irq_chip_mask_parent(struct irq_data *data);
477 extern void irq_chip_unmask_parent(struct irq_data *data);
478 extern void irq_chip_eoi_parent(struct irq_data *data);
479 extern int irq_chip_set_affinity_parent(struct irq_data *data,
480 const struct cpumask *dest,
482 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
483 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
485 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
488 /* Handling of unhandled and spurious interrupts: */
489 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
492 /* Enable/disable irq debugging output: */
493 extern int noirqdebug_setup(char *str);
495 /* Checks whether the interrupt can be requested by request_irq(): */
496 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
498 /* Dummy irq-chip implementations: */
499 extern struct irq_chip no_irq_chip;
500 extern struct irq_chip dummy_irq_chip;
503 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
504 irq_flow_handler_t handle, const char *name);
506 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
507 irq_flow_handler_t handle)
509 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
512 extern int irq_set_percpu_devid(unsigned int irq);
515 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
519 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
521 __irq_set_handler(irq, handle, 0, NULL);
525 * Set a highlevel chained flow handler for a given IRQ.
526 * (a chained handler is automatically enabled and set to
527 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
530 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
532 __irq_set_handler(irq, handle, 1, NULL);
536 * Set a highlevel chained flow handler and its data for a given IRQ.
537 * (a chained handler is automatically enabled and set to
538 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
541 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
544 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
546 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
548 irq_modify_status(irq, 0, set);
551 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
553 irq_modify_status(irq, clr, 0);
556 static inline void irq_set_noprobe(unsigned int irq)
558 irq_modify_status(irq, 0, IRQ_NOPROBE);
561 static inline void irq_set_probe(unsigned int irq)
563 irq_modify_status(irq, IRQ_NOPROBE, 0);
566 static inline void irq_set_nothread(unsigned int irq)
568 irq_modify_status(irq, 0, IRQ_NOTHREAD);
571 static inline void irq_set_thread(unsigned int irq)
573 irq_modify_status(irq, IRQ_NOTHREAD, 0);
576 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
579 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
581 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
584 static inline void irq_set_percpu_devid_flags(unsigned int irq)
586 irq_set_status_flags(irq,
587 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
588 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
591 /* Set/get chip/data for an IRQ: */
592 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
593 extern int irq_set_handler_data(unsigned int irq, void *data);
594 extern int irq_set_chip_data(unsigned int irq, void *data);
595 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
596 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
597 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
598 struct msi_desc *entry);
599 extern struct irq_data *irq_get_irq_data(unsigned int irq);
601 static inline struct irq_chip *irq_get_chip(unsigned int irq)
603 struct irq_data *d = irq_get_irq_data(irq);
604 return d ? d->chip : NULL;
607 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
612 static inline void *irq_get_chip_data(unsigned int irq)
614 struct irq_data *d = irq_get_irq_data(irq);
615 return d ? d->chip_data : NULL;
618 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
623 static inline void *irq_get_handler_data(unsigned int irq)
625 struct irq_data *d = irq_get_irq_data(irq);
626 return d ? d->handler_data : NULL;
629 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
631 return d->handler_data;
634 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
636 struct irq_data *d = irq_get_irq_data(irq);
637 return d ? d->msi_desc : NULL;
640 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
645 static inline u32 irq_get_trigger_type(unsigned int irq)
647 struct irq_data *d = irq_get_irq_data(irq);
648 return d ? irqd_get_trigger_type(d) : 0;
651 static inline int irq_data_get_node(struct irq_data *d)
656 static inline struct cpumask *irq_get_affinity_mask(int irq)
658 struct irq_data *d = irq_get_irq_data(irq);
660 return d ? d->affinity : NULL;
663 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
668 unsigned int arch_dynirq_lower_bound(unsigned int from);
670 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
671 struct module *owner);
673 /* use macros to avoid needing export.h for THIS_MODULE */
674 #define irq_alloc_descs(irq, from, cnt, node) \
675 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
677 #define irq_alloc_desc(node) \
678 irq_alloc_descs(-1, 0, 1, node)
680 #define irq_alloc_desc_at(at, node) \
681 irq_alloc_descs(at, at, 1, node)
683 #define irq_alloc_desc_from(from, node) \
684 irq_alloc_descs(-1, from, 1, node)
686 #define irq_alloc_descs_from(from, cnt, node) \
687 irq_alloc_descs(-1, from, cnt, node)
689 void irq_free_descs(unsigned int irq, unsigned int cnt);
690 static inline void irq_free_desc(unsigned int irq)
692 irq_free_descs(irq, 1);
695 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
696 unsigned int irq_alloc_hwirqs(int cnt, int node);
697 static inline unsigned int irq_alloc_hwirq(int node)
699 return irq_alloc_hwirqs(1, node);
701 void irq_free_hwirqs(unsigned int from, int cnt);
702 static inline void irq_free_hwirq(unsigned int irq)
704 return irq_free_hwirqs(irq, 1);
706 int arch_setup_hwirq(unsigned int irq, int node);
707 void arch_teardown_hwirq(unsigned int irq);
710 #ifdef CONFIG_GENERIC_IRQ_LEGACY
711 void irq_init_desc(unsigned int irq);
715 * struct irq_chip_regs - register offsets for struct irq_gci
716 * @enable: Enable register offset to reg_base
717 * @disable: Disable register offset to reg_base
718 * @mask: Mask register offset to reg_base
719 * @ack: Ack register offset to reg_base
720 * @eoi: Eoi register offset to reg_base
721 * @type: Type configuration register offset to reg_base
722 * @polarity: Polarity configuration register offset to reg_base
724 struct irq_chip_regs {
725 unsigned long enable;
726 unsigned long disable;
731 unsigned long polarity;
735 * struct irq_chip_type - Generic interrupt chip instance for a flow type
736 * @chip: The real interrupt chip which provides the callbacks
737 * @regs: Register offsets for this chip
738 * @handler: Flow handler associated with this chip
739 * @type: Chip can handle these flow types
740 * @mask_cache_priv: Cached mask register private to the chip type
741 * @mask_cache: Pointer to cached mask register
743 * A irq_generic_chip can have several instances of irq_chip_type when
744 * it requires different functions and register offsets for different
747 struct irq_chip_type {
748 struct irq_chip chip;
749 struct irq_chip_regs regs;
750 irq_flow_handler_t handler;
757 * struct irq_chip_generic - Generic irq chip data structure
758 * @lock: Lock to protect register and cache data access
759 * @reg_base: Register base address (virtual)
760 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
761 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
762 * @suspend: Function called from core code on suspend once per
763 * chip; can be useful instead of irq_chip::suspend to
764 * handle chip details even when no interrupts are in use
765 * @resume: Function called from core code on resume once per chip;
766 * can be useful instead of irq_chip::suspend to handle
767 * chip details even when no interrupts are in use
768 * @irq_base: Interrupt base nr for this chip
769 * @irq_cnt: Number of interrupts handled by this chip
770 * @mask_cache: Cached mask register shared between all chip types
771 * @type_cache: Cached type register
772 * @polarity_cache: Cached polarity register
773 * @wake_enabled: Interrupt can wakeup from suspend
774 * @wake_active: Interrupt is marked as an wakeup from suspend source
775 * @num_ct: Number of available irq_chip_type instances (usually 1)
776 * @private: Private data for non generic chip callbacks
777 * @installed: bitfield to denote installed interrupts
778 * @unused: bitfield to denote unused interrupts
779 * @domain: irq domain pointer
780 * @list: List head for keeping track of instances
781 * @chip_types: Array of interrupt irq_chip_types
783 * Note, that irq_chip_generic can have multiple irq_chip_type
784 * implementations which can be associated to a particular irq line of
785 * an irq_chip_generic instance. That allows to share and protect
786 * state in an irq_chip_generic instance when we need to implement
787 * different flow mechanisms (level/edge) for it.
789 struct irq_chip_generic {
791 void __iomem *reg_base;
792 u32 (*reg_readl)(void __iomem *addr);
793 void (*reg_writel)(u32 val, void __iomem *addr);
794 void (*suspend)(struct irq_chip_generic *gc);
795 void (*resume)(struct irq_chip_generic *gc);
796 unsigned int irq_base;
797 unsigned int irq_cnt;
805 unsigned long installed;
806 unsigned long unused;
807 struct irq_domain *domain;
808 struct list_head list;
809 struct irq_chip_type chip_types[0];
813 * enum irq_gc_flags - Initialization flags for generic irq chips
814 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
815 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
816 * irq chips which need to call irq_set_wake() on
817 * the parent irq. Usually GPIO implementations
818 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
819 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
820 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
823 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
824 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
825 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
826 IRQ_GC_NO_MASK = 1 << 3,
827 IRQ_GC_BE_IO = 1 << 4,
831 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
832 * @irqs_per_chip: Number of interrupts per chip
833 * @num_chips: Number of chips
834 * @irq_flags_to_set: IRQ* flags to set on irq setup
835 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
836 * @gc_flags: Generic chip specific setup flags
837 * @gc: Array of pointers to generic interrupt chips
839 struct irq_domain_chip_generic {
840 unsigned int irqs_per_chip;
841 unsigned int num_chips;
842 unsigned int irq_flags_to_clear;
843 unsigned int irq_flags_to_set;
844 enum irq_gc_flags gc_flags;
845 struct irq_chip_generic *gc[0];
848 /* Generic chip callback functions */
849 void irq_gc_noop(struct irq_data *d);
850 void irq_gc_mask_disable_reg(struct irq_data *d);
851 void irq_gc_mask_set_bit(struct irq_data *d);
852 void irq_gc_mask_clr_bit(struct irq_data *d);
853 void irq_gc_unmask_enable_reg(struct irq_data *d);
854 void irq_gc_ack_set_bit(struct irq_data *d);
855 void irq_gc_ack_clr_bit(struct irq_data *d);
856 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
857 void irq_gc_eoi(struct irq_data *d);
858 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
860 /* Setup functions for irq_chip_generic */
861 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
862 irq_hw_number_t hw_irq);
863 struct irq_chip_generic *
864 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
865 void __iomem *reg_base, irq_flow_handler_t handler);
866 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
867 enum irq_gc_flags flags, unsigned int clr,
869 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
870 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
871 unsigned int clr, unsigned int set);
873 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
874 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
875 int num_ct, const char *name,
876 irq_flow_handler_t handler,
877 unsigned int clr, unsigned int set,
878 enum irq_gc_flags flags);
881 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
883 return container_of(d->chip, struct irq_chip_type, chip);
886 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
889 static inline void irq_gc_lock(struct irq_chip_generic *gc)
891 raw_spin_lock(&gc->lock);
894 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
896 raw_spin_unlock(&gc->lock);
899 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
900 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
903 static inline void irq_reg_writel(struct irq_chip_generic *gc,
904 u32 val, int reg_offset)
907 gc->reg_writel(val, gc->reg_base + reg_offset);
909 writel(val, gc->reg_base + reg_offset);
912 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
916 return gc->reg_readl(gc->reg_base + reg_offset);
918 return readl(gc->reg_base + reg_offset);
921 #endif /* _LINUX_IRQ_H */