5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
25 #include <linux/slab.h>
28 #include <asm/ptrace.h>
29 #include <asm/irq_regs.h>
34 enum irqchip_irq_state;
39 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
41 * IRQ_TYPE_NONE - default, unspecified type
42 * IRQ_TYPE_EDGE_RISING - rising edge triggered
43 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
44 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
45 * IRQ_TYPE_LEVEL_HIGH - high level triggered
46 * IRQ_TYPE_LEVEL_LOW - low level triggered
47 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
48 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
49 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
50 * to setup the HW to a sane default (used
51 * by irqdomain map() callbacks to synchronize
52 * the HW state and SW flags for a newly
53 * allocated descriptor).
55 * IRQ_TYPE_PROBE - Special flag for probing in progress
57 * Bits which can be modified via irq_set/clear/modify_status_flags()
58 * IRQ_LEVEL - Interrupt is level type. Will be also
59 * updated in the code when the above trigger
60 * bits are modified via irq_set_irq_type()
61 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
62 * it from affinity setting
63 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
64 * IRQ_NOREQUEST - Interrupt cannot be requested via
66 * IRQ_NOTHREAD - Interrupt cannot be threaded
67 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
69 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
70 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
71 * IRQ_NESTED_THREAD - Interrupt nests into another thread
72 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
73 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
74 * it from the spurious interrupt detection
75 * mechanism and from core side polling.
76 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
79 IRQ_TYPE_NONE = 0x00000000,
80 IRQ_TYPE_EDGE_RISING = 0x00000001,
81 IRQ_TYPE_EDGE_FALLING = 0x00000002,
82 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
83 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
84 IRQ_TYPE_LEVEL_LOW = 0x00000008,
85 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
86 IRQ_TYPE_SENSE_MASK = 0x0000000f,
87 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
89 IRQ_TYPE_PROBE = 0x00000010,
92 IRQ_PER_CPU = (1 << 9),
93 IRQ_NOPROBE = (1 << 10),
94 IRQ_NOREQUEST = (1 << 11),
95 IRQ_NOAUTOEN = (1 << 12),
96 IRQ_NO_BALANCING = (1 << 13),
97 IRQ_MOVE_PCNTXT = (1 << 14),
98 IRQ_NESTED_THREAD = (1 << 15),
99 IRQ_NOTHREAD = (1 << 16),
100 IRQ_PER_CPU_DEVID = (1 << 17),
101 IRQ_IS_POLLED = (1 << 18),
102 IRQ_DISABLE_UNLAZY = (1 << 19),
105 #define IRQF_MODIFY_MASK \
106 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
107 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
108 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
109 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
111 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
114 * Return value for chip->irq_set_affinity()
116 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
117 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
118 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
119 * support stacked irqchips, which indicates skipping
120 * all descendent irqchips.
124 IRQ_SET_MASK_OK_NOCOPY,
125 IRQ_SET_MASK_OK_DONE,
132 * struct irq_common_data - per irq data shared by all irqchips
133 * @state_use_accessors: status information for irq chip functions.
134 * Use accessor functions to deal with it
135 * @node: node index useful for balancing
136 * @handler_data: per-IRQ data for the irq_chip methods
137 * @affinity: IRQ affinity on SMP. If this is an IPI
138 * related irq, then this is the mask of the
139 * CPUs to which an IPI can be sent.
140 * @effective_affinity: The effective IRQ affinity on SMP as some irq
141 * chips do not allow multi CPU destinations.
142 * A subset of @affinity.
143 * @msi_desc: MSI descriptor
144 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
146 struct irq_common_data {
147 unsigned int __private state_use_accessors;
152 struct msi_desc *msi_desc;
153 cpumask_var_t affinity;
154 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
155 cpumask_var_t effective_affinity;
157 #ifdef CONFIG_GENERIC_IRQ_IPI
158 unsigned int ipi_offset;
163 * struct irq_data - per irq chip data passed down to chip functions
164 * @mask: precomputed bitmask for accessing the chip registers
165 * @irq: interrupt number
166 * @hwirq: hardware interrupt number, local to the interrupt domain
167 * @common: point to data shared by all irqchips
168 * @chip: low level interrupt hardware access
169 * @domain: Interrupt translation domain; responsible for mapping
170 * between hwirq number and linux irq number.
171 * @parent_data: pointer to parent struct irq_data to support hierarchy
173 * @chip_data: platform-specific per-chip private data for the chip
174 * methods, to allow shared chip implementations
180 struct irq_common_data *common;
181 struct irq_chip *chip;
182 struct irq_domain *domain;
183 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
184 struct irq_data *parent_data;
190 * Bit masks for irq_common_data.state_use_accessors
192 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
193 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
194 * IRQD_ACTIVATED - Interrupt has already been activated
195 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
196 * IRQD_PER_CPU - Interrupt is per cpu
197 * IRQD_AFFINITY_SET - Interrupt affinity was set
198 * IRQD_LEVEL - Interrupt is level triggered
199 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
201 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
203 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
204 * IRQD_IRQ_MASKED - Masked state of the interrupt
205 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
206 * IRQD_WAKEUP_ARMED - Wakeup mode armed
207 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
208 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
209 * IRQD_IRQ_STARTED - Startup state of the interrupt
210 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
211 * mask. Applies only to affinity managed irqs.
214 IRQD_TRIGGER_MASK = 0xf,
215 IRQD_SETAFFINITY_PENDING = (1 << 8),
216 IRQD_ACTIVATED = (1 << 9),
217 IRQD_NO_BALANCING = (1 << 10),
218 IRQD_PER_CPU = (1 << 11),
219 IRQD_AFFINITY_SET = (1 << 12),
220 IRQD_LEVEL = (1 << 13),
221 IRQD_WAKEUP_STATE = (1 << 14),
222 IRQD_MOVE_PCNTXT = (1 << 15),
223 IRQD_IRQ_DISABLED = (1 << 16),
224 IRQD_IRQ_MASKED = (1 << 17),
225 IRQD_IRQ_INPROGRESS = (1 << 18),
226 IRQD_WAKEUP_ARMED = (1 << 19),
227 IRQD_FORWARDED_TO_VCPU = (1 << 20),
228 IRQD_AFFINITY_MANAGED = (1 << 21),
229 IRQD_IRQ_STARTED = (1 << 22),
230 IRQD_MANAGED_SHUTDOWN = (1 << 23),
233 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
235 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
237 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
240 static inline bool irqd_is_per_cpu(struct irq_data *d)
242 return __irqd_to_state(d) & IRQD_PER_CPU;
245 static inline bool irqd_can_balance(struct irq_data *d)
247 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
250 static inline bool irqd_affinity_was_set(struct irq_data *d)
252 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
255 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
257 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
260 static inline u32 irqd_get_trigger_type(struct irq_data *d)
262 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
266 * Must only be called inside irq_chip.irq_set_type() functions.
268 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
270 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
271 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
274 static inline bool irqd_is_level_type(struct irq_data *d)
276 return __irqd_to_state(d) & IRQD_LEVEL;
279 static inline bool irqd_is_wakeup_set(struct irq_data *d)
281 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
284 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
286 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
289 static inline bool irqd_irq_disabled(struct irq_data *d)
291 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
294 static inline bool irqd_irq_masked(struct irq_data *d)
296 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
299 static inline bool irqd_irq_inprogress(struct irq_data *d)
301 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
304 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
306 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
309 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
311 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
314 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
316 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
319 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
321 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
324 static inline bool irqd_affinity_is_managed(struct irq_data *d)
326 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
329 static inline bool irqd_is_activated(struct irq_data *d)
331 return __irqd_to_state(d) & IRQD_ACTIVATED;
334 static inline void irqd_set_activated(struct irq_data *d)
336 __irqd_to_state(d) |= IRQD_ACTIVATED;
339 static inline void irqd_clr_activated(struct irq_data *d)
341 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
344 static inline bool irqd_is_started(struct irq_data *d)
346 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
349 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
351 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
354 #undef __irqd_to_state
356 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
362 * struct irq_chip - hardware interrupt chip descriptor
364 * @parent_device: pointer to parent device for irqchip
365 * @name: name for /proc/interrupts
366 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
367 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
368 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
369 * @irq_disable: disable the interrupt
370 * @irq_ack: start of a new interrupt
371 * @irq_mask: mask an interrupt source
372 * @irq_mask_ack: ack and mask an interrupt source
373 * @irq_unmask: unmask an interrupt source
374 * @irq_eoi: end of interrupt
375 * @irq_set_affinity: set the CPU affinity on SMP machines
376 * @irq_retrigger: resend an IRQ to the CPU
377 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
378 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
379 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
380 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
381 * @irq_cpu_online: configure an interrupt source for a secondary CPU
382 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
383 * @irq_suspend: function called from core code on suspend once per
384 * chip, when one or more interrupts are installed
385 * @irq_resume: function called from core code on resume once per chip,
386 * when one ore more interrupts are installed
387 * @irq_pm_shutdown: function called from core code on shutdown once per chip
388 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
389 * @irq_print_chip: optional to print special chip info in show_interrupts
390 * @irq_request_resources: optional to request resources before calling
391 * any other callback related to this irq
392 * @irq_release_resources: optional to release resources acquired with
393 * irq_request_resources
394 * @irq_compose_msi_msg: optional to compose message content for MSI
395 * @irq_write_msi_msg: optional to write message content for MSI
396 * @irq_get_irqchip_state: return the internal state of an interrupt
397 * @irq_set_irqchip_state: set the internal state of a interrupt
398 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
399 * @ipi_send_single: send a single IPI to destination cpus
400 * @ipi_send_mask: send an IPI to destination cpus in cpumask
401 * @flags: chip specific flags
404 struct device *parent_device;
406 unsigned int (*irq_startup)(struct irq_data *data);
407 void (*irq_shutdown)(struct irq_data *data);
408 void (*irq_enable)(struct irq_data *data);
409 void (*irq_disable)(struct irq_data *data);
411 void (*irq_ack)(struct irq_data *data);
412 void (*irq_mask)(struct irq_data *data);
413 void (*irq_mask_ack)(struct irq_data *data);
414 void (*irq_unmask)(struct irq_data *data);
415 void (*irq_eoi)(struct irq_data *data);
417 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
418 int (*irq_retrigger)(struct irq_data *data);
419 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
420 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
422 void (*irq_bus_lock)(struct irq_data *data);
423 void (*irq_bus_sync_unlock)(struct irq_data *data);
425 void (*irq_cpu_online)(struct irq_data *data);
426 void (*irq_cpu_offline)(struct irq_data *data);
428 void (*irq_suspend)(struct irq_data *data);
429 void (*irq_resume)(struct irq_data *data);
430 void (*irq_pm_shutdown)(struct irq_data *data);
432 void (*irq_calc_mask)(struct irq_data *data);
434 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
435 int (*irq_request_resources)(struct irq_data *data);
436 void (*irq_release_resources)(struct irq_data *data);
438 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
439 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
441 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
442 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
444 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
446 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
447 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
453 * irq_chip specific flags
455 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
456 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
457 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
458 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
460 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
461 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
462 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
465 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
466 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
467 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
468 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
469 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
470 IRQCHIP_ONESHOT_SAFE = (1 << 5),
471 IRQCHIP_EOI_THREADED = (1 << 6),
474 #include <linux/irqdesc.h>
477 * Pick up the arch-dependent methods:
479 #include <asm/hw_irq.h>
481 #ifndef NR_IRQS_LEGACY
482 # define NR_IRQS_LEGACY 0
485 #ifndef ARCH_IRQ_INIT_FLAGS
486 # define ARCH_IRQ_INIT_FLAGS 0
489 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
492 extern int setup_irq(unsigned int irq, struct irqaction *new);
493 extern void remove_irq(unsigned int irq, struct irqaction *act);
494 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
495 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
497 extern void irq_cpu_online(void);
498 extern void irq_cpu_offline(void);
499 extern int irq_set_affinity_locked(struct irq_data *data,
500 const struct cpumask *cpumask, bool force);
501 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
503 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
504 extern void irq_migrate_all_off_this_cpu(void);
505 extern int irq_affinity_online_cpu(unsigned int cpu);
507 # define irq_affinity_online_cpu NULL
510 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
511 void irq_move_irq(struct irq_data *data);
512 void irq_move_masked_irq(struct irq_data *data);
513 void irq_force_complete_move(struct irq_desc *desc);
515 static inline void irq_move_irq(struct irq_data *data) { }
516 static inline void irq_move_masked_irq(struct irq_data *data) { }
517 static inline void irq_force_complete_move(struct irq_desc *desc) { }
520 extern int no_irq_affinity;
522 #ifdef CONFIG_HARDIRQS_SW_RESEND
523 int irq_set_parent(int irq, int parent_irq);
525 static inline int irq_set_parent(int irq, int parent_irq)
532 * Built-in IRQ handlers for various IRQ types,
533 * callable via desc->handle_irq()
535 extern void handle_level_irq(struct irq_desc *desc);
536 extern void handle_fasteoi_irq(struct irq_desc *desc);
537 extern void handle_edge_irq(struct irq_desc *desc);
538 extern void handle_edge_eoi_irq(struct irq_desc *desc);
539 extern void handle_simple_irq(struct irq_desc *desc);
540 extern void handle_untracked_irq(struct irq_desc *desc);
541 extern void handle_percpu_irq(struct irq_desc *desc);
542 extern void handle_percpu_devid_irq(struct irq_desc *desc);
543 extern void handle_bad_irq(struct irq_desc *desc);
544 extern void handle_nested_irq(unsigned int irq);
546 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
547 extern int irq_chip_pm_get(struct irq_data *data);
548 extern int irq_chip_pm_put(struct irq_data *data);
549 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
550 extern void irq_chip_enable_parent(struct irq_data *data);
551 extern void irq_chip_disable_parent(struct irq_data *data);
552 extern void irq_chip_ack_parent(struct irq_data *data);
553 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
554 extern void irq_chip_mask_parent(struct irq_data *data);
555 extern void irq_chip_unmask_parent(struct irq_data *data);
556 extern void irq_chip_eoi_parent(struct irq_data *data);
557 extern int irq_chip_set_affinity_parent(struct irq_data *data,
558 const struct cpumask *dest,
560 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
561 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
563 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
566 /* Handling of unhandled and spurious interrupts: */
567 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
570 /* Enable/disable irq debugging output: */
571 extern int noirqdebug_setup(char *str);
573 /* Checks whether the interrupt can be requested by request_irq(): */
574 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
576 /* Dummy irq-chip implementations: */
577 extern struct irq_chip no_irq_chip;
578 extern struct irq_chip dummy_irq_chip;
581 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
582 irq_flow_handler_t handle, const char *name);
584 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
585 irq_flow_handler_t handle)
587 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
590 extern int irq_set_percpu_devid(unsigned int irq);
591 extern int irq_set_percpu_devid_partition(unsigned int irq,
592 const struct cpumask *affinity);
593 extern int irq_get_percpu_devid_partition(unsigned int irq,
594 struct cpumask *affinity);
597 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
601 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
603 __irq_set_handler(irq, handle, 0, NULL);
607 * Set a highlevel chained flow handler for a given IRQ.
608 * (a chained handler is automatically enabled and set to
609 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
612 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
614 __irq_set_handler(irq, handle, 1, NULL);
618 * Set a highlevel chained flow handler and its data for a given IRQ.
619 * (a chained handler is automatically enabled and set to
620 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
623 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
626 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
628 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
630 irq_modify_status(irq, 0, set);
633 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
635 irq_modify_status(irq, clr, 0);
638 static inline void irq_set_noprobe(unsigned int irq)
640 irq_modify_status(irq, 0, IRQ_NOPROBE);
643 static inline void irq_set_probe(unsigned int irq)
645 irq_modify_status(irq, IRQ_NOPROBE, 0);
648 static inline void irq_set_nothread(unsigned int irq)
650 irq_modify_status(irq, 0, IRQ_NOTHREAD);
653 static inline void irq_set_thread(unsigned int irq)
655 irq_modify_status(irq, IRQ_NOTHREAD, 0);
658 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
661 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
663 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
666 static inline void irq_set_percpu_devid_flags(unsigned int irq)
668 irq_set_status_flags(irq,
669 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
670 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
673 /* Set/get chip/data for an IRQ: */
674 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
675 extern int irq_set_handler_data(unsigned int irq, void *data);
676 extern int irq_set_chip_data(unsigned int irq, void *data);
677 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
678 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
679 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
680 struct msi_desc *entry);
681 extern struct irq_data *irq_get_irq_data(unsigned int irq);
683 static inline struct irq_chip *irq_get_chip(unsigned int irq)
685 struct irq_data *d = irq_get_irq_data(irq);
686 return d ? d->chip : NULL;
689 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
694 static inline void *irq_get_chip_data(unsigned int irq)
696 struct irq_data *d = irq_get_irq_data(irq);
697 return d ? d->chip_data : NULL;
700 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
705 static inline void *irq_get_handler_data(unsigned int irq)
707 struct irq_data *d = irq_get_irq_data(irq);
708 return d ? d->common->handler_data : NULL;
711 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
713 return d->common->handler_data;
716 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
718 struct irq_data *d = irq_get_irq_data(irq);
719 return d ? d->common->msi_desc : NULL;
722 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
724 return d->common->msi_desc;
727 static inline u32 irq_get_trigger_type(unsigned int irq)
729 struct irq_data *d = irq_get_irq_data(irq);
730 return d ? irqd_get_trigger_type(d) : 0;
733 static inline int irq_common_data_get_node(struct irq_common_data *d)
742 static inline int irq_data_get_node(struct irq_data *d)
744 return irq_common_data_get_node(d->common);
747 static inline struct cpumask *irq_get_affinity_mask(int irq)
749 struct irq_data *d = irq_get_irq_data(irq);
751 return d ? d->common->affinity : NULL;
754 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
756 return d->common->affinity;
759 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
761 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
763 return d->common->effective_affinity;
765 static inline void irq_data_update_effective_affinity(struct irq_data *d,
766 const struct cpumask *m)
768 cpumask_copy(d->common->effective_affinity, m);
771 static inline void irq_data_update_effective_affinity(struct irq_data *d,
772 const struct cpumask *m)
776 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
778 return d->common->affinity;
782 unsigned int arch_dynirq_lower_bound(unsigned int from);
784 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
785 struct module *owner, const struct cpumask *affinity);
787 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
788 unsigned int cnt, int node, struct module *owner,
789 const struct cpumask *affinity);
791 /* use macros to avoid needing export.h for THIS_MODULE */
792 #define irq_alloc_descs(irq, from, cnt, node) \
793 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
795 #define irq_alloc_desc(node) \
796 irq_alloc_descs(-1, 0, 1, node)
798 #define irq_alloc_desc_at(at, node) \
799 irq_alloc_descs(at, at, 1, node)
801 #define irq_alloc_desc_from(from, node) \
802 irq_alloc_descs(-1, from, 1, node)
804 #define irq_alloc_descs_from(from, cnt, node) \
805 irq_alloc_descs(-1, from, cnt, node)
807 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
808 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
810 #define devm_irq_alloc_desc(dev, node) \
811 devm_irq_alloc_descs(dev, -1, 0, 1, node)
813 #define devm_irq_alloc_desc_at(dev, at, node) \
814 devm_irq_alloc_descs(dev, at, at, 1, node)
816 #define devm_irq_alloc_desc_from(dev, from, node) \
817 devm_irq_alloc_descs(dev, -1, from, 1, node)
819 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
820 devm_irq_alloc_descs(dev, -1, from, cnt, node)
822 void irq_free_descs(unsigned int irq, unsigned int cnt);
823 static inline void irq_free_desc(unsigned int irq)
825 irq_free_descs(irq, 1);
828 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
829 unsigned int irq_alloc_hwirqs(int cnt, int node);
830 static inline unsigned int irq_alloc_hwirq(int node)
832 return irq_alloc_hwirqs(1, node);
834 void irq_free_hwirqs(unsigned int from, int cnt);
835 static inline void irq_free_hwirq(unsigned int irq)
837 return irq_free_hwirqs(irq, 1);
839 int arch_setup_hwirq(unsigned int irq, int node);
840 void arch_teardown_hwirq(unsigned int irq);
843 #ifdef CONFIG_GENERIC_IRQ_LEGACY
844 void irq_init_desc(unsigned int irq);
848 * struct irq_chip_regs - register offsets for struct irq_gci
849 * @enable: Enable register offset to reg_base
850 * @disable: Disable register offset to reg_base
851 * @mask: Mask register offset to reg_base
852 * @ack: Ack register offset to reg_base
853 * @eoi: Eoi register offset to reg_base
854 * @type: Type configuration register offset to reg_base
855 * @polarity: Polarity configuration register offset to reg_base
857 struct irq_chip_regs {
858 unsigned long enable;
859 unsigned long disable;
864 unsigned long polarity;
868 * struct irq_chip_type - Generic interrupt chip instance for a flow type
869 * @chip: The real interrupt chip which provides the callbacks
870 * @regs: Register offsets for this chip
871 * @handler: Flow handler associated with this chip
872 * @type: Chip can handle these flow types
873 * @mask_cache_priv: Cached mask register private to the chip type
874 * @mask_cache: Pointer to cached mask register
876 * A irq_generic_chip can have several instances of irq_chip_type when
877 * it requires different functions and register offsets for different
880 struct irq_chip_type {
881 struct irq_chip chip;
882 struct irq_chip_regs regs;
883 irq_flow_handler_t handler;
890 * struct irq_chip_generic - Generic irq chip data structure
891 * @lock: Lock to protect register and cache data access
892 * @reg_base: Register base address (virtual)
893 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
894 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
895 * @suspend: Function called from core code on suspend once per
896 * chip; can be useful instead of irq_chip::suspend to
897 * handle chip details even when no interrupts are in use
898 * @resume: Function called from core code on resume once per chip;
899 * can be useful instead of irq_chip::suspend to handle
900 * chip details even when no interrupts are in use
901 * @irq_base: Interrupt base nr for this chip
902 * @irq_cnt: Number of interrupts handled by this chip
903 * @mask_cache: Cached mask register shared between all chip types
904 * @type_cache: Cached type register
905 * @polarity_cache: Cached polarity register
906 * @wake_enabled: Interrupt can wakeup from suspend
907 * @wake_active: Interrupt is marked as an wakeup from suspend source
908 * @num_ct: Number of available irq_chip_type instances (usually 1)
909 * @private: Private data for non generic chip callbacks
910 * @installed: bitfield to denote installed interrupts
911 * @unused: bitfield to denote unused interrupts
912 * @domain: irq domain pointer
913 * @list: List head for keeping track of instances
914 * @chip_types: Array of interrupt irq_chip_types
916 * Note, that irq_chip_generic can have multiple irq_chip_type
917 * implementations which can be associated to a particular irq line of
918 * an irq_chip_generic instance. That allows to share and protect
919 * state in an irq_chip_generic instance when we need to implement
920 * different flow mechanisms (level/edge) for it.
922 struct irq_chip_generic {
924 void __iomem *reg_base;
925 u32 (*reg_readl)(void __iomem *addr);
926 void (*reg_writel)(u32 val, void __iomem *addr);
927 void (*suspend)(struct irq_chip_generic *gc);
928 void (*resume)(struct irq_chip_generic *gc);
929 unsigned int irq_base;
930 unsigned int irq_cnt;
938 unsigned long installed;
939 unsigned long unused;
940 struct irq_domain *domain;
941 struct list_head list;
942 struct irq_chip_type chip_types[0];
946 * enum irq_gc_flags - Initialization flags for generic irq chips
947 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
948 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
949 * irq chips which need to call irq_set_wake() on
950 * the parent irq. Usually GPIO implementations
951 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
952 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
953 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
956 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
957 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
958 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
959 IRQ_GC_NO_MASK = 1 << 3,
960 IRQ_GC_BE_IO = 1 << 4,
964 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
965 * @irqs_per_chip: Number of interrupts per chip
966 * @num_chips: Number of chips
967 * @irq_flags_to_set: IRQ* flags to set on irq setup
968 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
969 * @gc_flags: Generic chip specific setup flags
970 * @gc: Array of pointers to generic interrupt chips
972 struct irq_domain_chip_generic {
973 unsigned int irqs_per_chip;
974 unsigned int num_chips;
975 unsigned int irq_flags_to_clear;
976 unsigned int irq_flags_to_set;
977 enum irq_gc_flags gc_flags;
978 struct irq_chip_generic *gc[0];
981 /* Generic chip callback functions */
982 void irq_gc_noop(struct irq_data *d);
983 void irq_gc_mask_disable_reg(struct irq_data *d);
984 void irq_gc_mask_set_bit(struct irq_data *d);
985 void irq_gc_mask_clr_bit(struct irq_data *d);
986 void irq_gc_unmask_enable_reg(struct irq_data *d);
987 void irq_gc_ack_set_bit(struct irq_data *d);
988 void irq_gc_ack_clr_bit(struct irq_data *d);
989 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
990 void irq_gc_eoi(struct irq_data *d);
991 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
993 /* Setup functions for irq_chip_generic */
994 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
995 irq_hw_number_t hw_irq);
996 struct irq_chip_generic *
997 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
998 void __iomem *reg_base, irq_flow_handler_t handler);
999 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1000 enum irq_gc_flags flags, unsigned int clr,
1002 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1003 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1004 unsigned int clr, unsigned int set);
1006 struct irq_chip_generic *
1007 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1008 unsigned int irq_base, void __iomem *reg_base,
1009 irq_flow_handler_t handler);
1010 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1011 u32 msk, enum irq_gc_flags flags,
1012 unsigned int clr, unsigned int set);
1014 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1016 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1017 int num_ct, const char *name,
1018 irq_flow_handler_t handler,
1019 unsigned int clr, unsigned int set,
1020 enum irq_gc_flags flags);
1022 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1023 handler, clr, set, flags) \
1025 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1026 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1027 handler, clr, set, flags); \
1030 static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1035 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1036 u32 msk, unsigned int clr,
1039 irq_remove_generic_chip(gc, msk, clr, set);
1040 irq_free_generic_chip(gc);
1043 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1045 return container_of(d->chip, struct irq_chip_type, chip);
1048 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1051 static inline void irq_gc_lock(struct irq_chip_generic *gc)
1053 raw_spin_lock(&gc->lock);
1056 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1058 raw_spin_unlock(&gc->lock);
1061 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
1062 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1066 * The irqsave variants are for usage in non interrupt code. Do not use
1067 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1069 #define irq_gc_lock_irqsave(gc, flags) \
1070 raw_spin_lock_irqsave(&(gc)->lock, flags)
1072 #define irq_gc_unlock_irqrestore(gc, flags) \
1073 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1075 static inline void irq_reg_writel(struct irq_chip_generic *gc,
1076 u32 val, int reg_offset)
1079 gc->reg_writel(val, gc->reg_base + reg_offset);
1081 writel(val, gc->reg_base + reg_offset);
1084 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1088 return gc->reg_readl(gc->reg_base + reg_offset);
1090 return readl(gc->reg_base + reg_offset);
1093 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1094 #define INVALID_HWIRQ (~0UL)
1095 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1096 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1097 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1098 int ipi_send_single(unsigned int virq, unsigned int cpu);
1099 int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1101 #endif /* _LINUX_IRQ_H */