include/linux/mfd/dbx500-prcmu.h

   1 /*
   2  * Copyright (C) ST Ericsson SA 2011
   3  *
   4  * License Terms: GNU General Public License v2
   5  *
   6  * STE Ux500 PRCMU API
   7  */
   8 #ifndef __MACH_PRCMU_H
   9 #define __MACH_PRCMU_H
  10
  11 #include <linux/interrupt.h>
  12 #include <linux/notifier.h>
  13 #include <linux/err.h>
  14
  15 /* PRCMU Wakeup defines */
  16 enum prcmu_wakeup_index {
  17         PRCMU_WAKEUP_INDEX_RTC,
  18         PRCMU_WAKEUP_INDEX_RTT0,
  19         PRCMU_WAKEUP_INDEX_RTT1,
  20         PRCMU_WAKEUP_INDEX_HSI0,
  21         PRCMU_WAKEUP_INDEX_HSI1,
  22         PRCMU_WAKEUP_INDEX_USB,
  23         PRCMU_WAKEUP_INDEX_ABB,
  24         PRCMU_WAKEUP_INDEX_ABB_FIFO,
  25         PRCMU_WAKEUP_INDEX_ARM,
  26         PRCMU_WAKEUP_INDEX_CD_IRQ,
  27         NUM_PRCMU_WAKEUP_INDICES
  28 };
  29 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
  30
  31 /* EPOD (power domain) IDs */
  32
  33 /*
  34  * DB8500 EPODs
  35  * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
  36  * - EPOD_ID_SVAPIPE: power domain for SVA pipe
  37  * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
  38  * - EPOD_ID_SIAPIPE: power domain for SIA pipe
  39  * - EPOD_ID_SGA: power domain for SGA
  40  * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
  41  * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
  42  * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
  43  * - NUM_EPOD_ID: number of power domains
  44  *
  45  * TODO: These should be prefixed.
  46  */
  47 #define EPOD_ID_SVAMMDSP        0
  48 #define EPOD_ID_SVAPIPE         1
  49 #define EPOD_ID_SIAMMDSP        2
  50 #define EPOD_ID_SIAPIPE         3
  51 #define EPOD_ID_SGA             4
  52 #define EPOD_ID_B2R2_MCDE       5
  53 #define EPOD_ID_ESRAM12         6
  54 #define EPOD_ID_ESRAM34         7
  55 #define NUM_EPOD_ID             8
  56
  57 /*
  58  * DB5500 EPODs
  59  */
  60 #define DB5500_EPOD_ID_BASE 0x0100
  61 #define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
  62 #define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
  63 #define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
  64 #define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
  65 #define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
  66 #define DB5500_NUM_EPOD_ID 7
  67
  68 /*
  69  * state definition for EPOD (power domain)
  70  * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
  71  * - EPOD_STATE_OFF: The EPOD is switched off
  72  * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
  73  *                         retention
  74  * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
  75  * - EPOD_STATE_ON: Same as above, but with clock enabled
  76  */
  77 #define EPOD_STATE_NO_CHANGE    0x00
  78 #define EPOD_STATE_OFF          0x01
  79 #define EPOD_STATE_RAMRET       0x02
  80 #define EPOD_STATE_ON_CLK_OFF   0x03
  81 #define EPOD_STATE_ON           0x04
  82
  83 /* DB5500 CLKOUT IDs */
  84 enum {
  85         DB5500_CLKOUT0 = 0,
  86         DB5500_CLKOUT1,
  87 };
  88
  89 /* DB5500 CLKOUTx sources */
  90 enum {
  91         DB5500_CLKOUT_REF_CLK_SEL0,
  92         DB5500_CLKOUT_RTC_CLK0_SEL0,
  93         DB5500_CLKOUT_ULP_CLK_SEL0,
  94         DB5500_CLKOUT_STATIC0,
  95         DB5500_CLKOUT_REFCLK,
  96         DB5500_CLKOUT_ULPCLK,
  97         DB5500_CLKOUT_ARMCLK,
  98         DB5500_CLKOUT_SYSACC0CLK,
  99         DB5500_CLKOUT_SOC0PLLCLK,
 100         DB5500_CLKOUT_SOC1PLLCLK,
 101         DB5500_CLKOUT_DDRPLLCLK,
 102         DB5500_CLKOUT_TVCLK,
 103         DB5500_CLKOUT_IRDACLK,
 104 };
 105
 106 /*
 107  * CLKOUT sources
 108  */
 109 #define PRCMU_CLKSRC_CLK38M             0x00
 110 #define PRCMU_CLKSRC_ACLK               0x01
 111 #define PRCMU_CLKSRC_SYSCLK             0x02
 112 #define PRCMU_CLKSRC_LCDCLK             0x03
 113 #define PRCMU_CLKSRC_SDMMCCLK           0x04
 114 #define PRCMU_CLKSRC_TVCLK              0x05
 115 #define PRCMU_CLKSRC_TIMCLK             0x06
 116 #define PRCMU_CLKSRC_CLK009             0x07
 117 /* These are only valid for CLKOUT1: */
 118 #define PRCMU_CLKSRC_SIAMMDSPCLK        0x40
 119 #define PRCMU_CLKSRC_I2CCLK             0x41
 120 #define PRCMU_CLKSRC_MSP02CLK           0x42
 121 #define PRCMU_CLKSRC_ARMPLL_OBSCLK      0x43
 122 #define PRCMU_CLKSRC_HSIRXCLK           0x44
 123 #define PRCMU_CLKSRC_HSITXCLK           0x45
 124 #define PRCMU_CLKSRC_ARMCLKFIX          0x46
 125 #define PRCMU_CLKSRC_HDMICLK            0x47
 126
 127 /*
 128  * Clock identifiers.
 129  */
 130 enum prcmu_clock {
 131         PRCMU_SGACLK,
 132         PRCMU_UARTCLK,
 133         PRCMU_MSP02CLK,
 134         PRCMU_MSP1CLK,
 135         PRCMU_I2CCLK,
 136         PRCMU_SDMMCCLK,
 137         PRCMU_SPARE1CLK,
 138         PRCMU_SLIMCLK,
 139         PRCMU_PER1CLK,
 140         PRCMU_PER2CLK,
 141         PRCMU_PER3CLK,
 142         PRCMU_PER5CLK,
 143         PRCMU_PER6CLK,
 144         PRCMU_PER7CLK,
 145         PRCMU_LCDCLK,
 146         PRCMU_BMLCLK,
 147         PRCMU_HSITXCLK,
 148         PRCMU_HSIRXCLK,
 149         PRCMU_HDMICLK,
 150         PRCMU_APEATCLK,
 151         PRCMU_APETRACECLK,
 152         PRCMU_MCDECLK,
 153         PRCMU_IPI2CCLK,
 154         PRCMU_DSIALTCLK,
 155         PRCMU_DMACLK,
 156         PRCMU_B2R2CLK,
 157         PRCMU_TVCLK,
 158         PRCMU_SSPCLK,
 159         PRCMU_RNGCLK,
 160         PRCMU_UICCCLK,
 161         PRCMU_PWMCLK,
 162         PRCMU_IRDACLK,
 163         PRCMU_IRRCCLK,
 164         PRCMU_SIACLK,
 165         PRCMU_SVACLK,
 166         PRCMU_ACLK,
 167         PRCMU_NUM_REG_CLOCKS,
 168         PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
 169         PRCMU_CDCLK,
 170         PRCMU_TIMCLK,
 171         PRCMU_PLLSOC0,
 172         PRCMU_PLLSOC1,
 173         PRCMU_PLLDDR,
 174         PRCMU_PLLDSI,
 175         PRCMU_DSI0CLK,
 176         PRCMU_DSI1CLK,
 177         PRCMU_DSI0ESCCLK,
 178         PRCMU_DSI1ESCCLK,
 179         PRCMU_DSI2ESCCLK,
 180 };
 181
 182 /**
 183  * enum ape_opp - APE OPP states definition
 184  * @APE_OPP_INIT:
 185  * @APE_NO_CHANGE: The APE operating point is unchanged
 186  * @APE_100_OPP: The new APE operating point is ape100opp
 187  * @APE_50_OPP: 50%
 188  * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
 189  */
 190 enum ape_opp {
 191         APE_OPP_INIT = 0x00,
 192         APE_NO_CHANGE = 0x01,
 193         APE_100_OPP = 0x02,
 194         APE_50_OPP = 0x03,
 195         APE_50_PARTLY_25_OPP = 0xFF,
 196 };
 197
 198 /**
 199  * enum arm_opp - ARM OPP states definition
 200  * @ARM_OPP_INIT:
 201  * @ARM_NO_CHANGE: The ARM operating point is unchanged
 202  * @ARM_100_OPP: The new ARM operating point is arm100opp
 203  * @ARM_50_OPP: The new ARM operating point is arm50opp
 204  * @ARM_MAX_OPP: Operating point is "max" (more than 100)
 205  * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
 206  * @ARM_EXTCLK: The new ARM operating point is armExtClk
 207  */
 208 enum arm_opp {
 209         ARM_OPP_INIT = 0x00,
 210         ARM_NO_CHANGE = 0x01,
 211         ARM_100_OPP = 0x02,
 212         ARM_50_OPP = 0x03,
 213         ARM_MAX_OPP = 0x04,
 214         ARM_MAX_FREQ100OPP = 0x05,
 215         ARM_EXTCLK = 0x07
 216 };
 217
 218 /**
 219  * enum ddr_opp - DDR OPP states definition
 220  * @DDR_100_OPP: The new DDR operating point is ddr100opp
 221  * @DDR_50_OPP: The new DDR operating point is ddr50opp
 222  * @DDR_25_OPP: The new DDR operating point is ddr25opp
 223  */
 224 enum ddr_opp {
 225         DDR_100_OPP = 0x00,
 226         DDR_50_OPP = 0x01,
 227         DDR_25_OPP = 0x02,
 228 };
 229
 230 /*
 231  * Definitions for controlling ESRAM0 in deep sleep.
 232  */
 233 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1
 234 #define ESRAM0_DEEP_SLEEP_STATE_RET 2
 235
 236 /**
 237  * enum ddr_pwrst - DDR power states definition
 238  * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
 239  * @DDR_PWR_STATE_ON:
 240  * @DDR_PWR_STATE_OFFLOWLAT:
 241  * @DDR_PWR_STATE_OFFHIGHLAT:
 242  */
 243 enum ddr_pwrst {
 244         DDR_PWR_STATE_UNCHANGED     = 0x00,
 245         DDR_PWR_STATE_ON            = 0x01,
 246         DDR_PWR_STATE_OFFLOWLAT     = 0x02,
 247         DDR_PWR_STATE_OFFHIGHLAT    = 0x03
 248 };
 249
 250 #include <linux/mfd/db8500-prcmu.h>
 251 #include <linux/mfd/db5500-prcmu.h>
 252
 253 #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
 254
 255 #include <mach/id.h>
 256
 257 static inline void __init prcmu_early_init(void)
 258 {
 259         if (cpu_is_u5500())
 260                 return db5500_prcmu_early_init();
 261         else
 262                 return db8500_prcmu_early_init();
 263 }
 264
 265 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
 266                 bool keep_ap_pll)
 267 {
 268         if (cpu_is_u5500())
 269                 return db5500_prcmu_set_power_state(state, keep_ulp_clk,
 270                         keep_ap_pll);
 271         else
 272                 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
 273                         keep_ap_pll);
 274 }
 275
 276 static inline u8 prcmu_get_power_state_result(void)
 277 {
 278         if (cpu_is_u5500())
 279                 return -EINVAL;
 280         else
 281                 return db8500_prcmu_get_power_state_result();
 282 }
 283
 284 static inline int prcmu_gic_decouple(void)
 285 {
 286         if (cpu_is_u5500())
 287                 return -EINVAL;
 288         else
 289                 return db8500_prcmu_gic_decouple();
 290 }
 291
 292 static inline int prcmu_gic_recouple(void)
 293 {
 294         if (cpu_is_u5500())
 295                 return -EINVAL;
 296         else
 297                 return db8500_prcmu_gic_recouple();
 298 }
 299
 300 static inline bool prcmu_gic_pending_irq(void)
 301 {
 302         if (cpu_is_u5500())
 303                 return -EINVAL;
 304         else
 305                 return db8500_prcmu_gic_pending_irq();
 306 }
 307
 308 static inline bool prcmu_is_cpu_in_wfi(int cpu)
 309 {
 310         if (cpu_is_u5500())
 311                 return -EINVAL;
 312         else
 313                 return db8500_prcmu_is_cpu_in_wfi(cpu);
 314 }
 315
 316 static inline int prcmu_copy_gic_settings(void)
 317 {
 318         if (cpu_is_u5500())
 319                 return -EINVAL;
 320         else
 321                 return db8500_prcmu_copy_gic_settings();
 322 }
 323
 324 static inline bool prcmu_pending_irq(void)
 325 {
 326         if (cpu_is_u5500())
 327                 return -EINVAL;
 328         else
 329                 return db8500_prcmu_pending_irq();
 330 }
 331
 332 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
 333 {
 334         if (cpu_is_u5500())
 335                 return -EINVAL;
 336         else
 337                 return db8500_prcmu_set_epod(epod_id, epod_state);
 338 }
 339
 340 static inline void prcmu_enable_wakeups(u32 wakeups)
 341 {
 342         if (cpu_is_u5500())
 343                 db5500_prcmu_enable_wakeups(wakeups);
 344         else
 345                 db8500_prcmu_enable_wakeups(wakeups);
 346 }
 347
 348 static inline void prcmu_disable_wakeups(void)
 349 {
 350         prcmu_enable_wakeups(0);
 351 }
 352
 353 static inline void prcmu_config_abb_event_readout(u32 abb_events)
 354 {
 355         if (cpu_is_u5500())
 356                 db5500_prcmu_config_abb_event_readout(abb_events);
 357         else
 358                 db8500_prcmu_config_abb_event_readout(abb_events);
 359 }
 360
 361 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
 362 {
 363         if (cpu_is_u5500())
 364                 db5500_prcmu_get_abb_event_buffer(buf);
 365         else
 366                 db8500_prcmu_get_abb_event_buffer(buf);
 367 }
 368
 369 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
 370 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
 371 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
 372
 373 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
 374
 375 static inline int prcmu_request_clock(u8 clock, bool enable)
 376 {
 377         if (cpu_is_u5500())
 378                 return db5500_prcmu_request_clock(clock, enable);
 379         else
 380                 return db8500_prcmu_request_clock(clock, enable);
 381 }
 382
 383 unsigned long prcmu_clock_rate(u8 clock);
 384 long prcmu_round_clock_rate(u8 clock, unsigned long rate);
 385 int prcmu_set_clock_rate(u8 clock, unsigned long rate);
 386
 387 static inline int prcmu_set_ddr_opp(u8 opp)
 388 {
 389         if (cpu_is_u5500())
 390                 return -EINVAL;
 391         else
 392                 return db8500_prcmu_set_ddr_opp(opp);
 393 }
 394 static inline int prcmu_get_ddr_opp(void)
 395 {
 396         if (cpu_is_u5500())
 397                 return -EINVAL;
 398         else
 399                 return db8500_prcmu_get_ddr_opp();
 400 }
 401
 402 static inline int prcmu_set_arm_opp(u8 opp)
 403 {
 404         if (cpu_is_u5500())
 405                 return -EINVAL;
 406         else
 407                 return db8500_prcmu_set_arm_opp(opp);
 408 }
 409
 410 static inline int prcmu_get_arm_opp(void)
 411 {
 412         if (cpu_is_u5500())
 413                 return -EINVAL;
 414         else
 415                 return db8500_prcmu_get_arm_opp();
 416 }
 417
 418 static inline int prcmu_set_ape_opp(u8 opp)
 419 {
 420         if (cpu_is_u5500())
 421                 return -EINVAL;
 422         else
 423                 return db8500_prcmu_set_ape_opp(opp);
 424 }
 425
 426 static inline int prcmu_get_ape_opp(void)
 427 {
 428         if (cpu_is_u5500())
 429                 return -EINVAL;
 430         else
 431                 return db8500_prcmu_get_ape_opp();
 432 }
 433
 434 static inline void prcmu_system_reset(u16 reset_code)
 435 {
 436         if (cpu_is_u5500())
 437                 return db5500_prcmu_system_reset(reset_code);
 438         else
 439                 return db8500_prcmu_system_reset(reset_code);
 440 }
 441
 442 static inline u16 prcmu_get_reset_code(void)
 443 {
 444         if (cpu_is_u5500())
 445                 return db5500_prcmu_get_reset_code();
 446         else
 447                 return db8500_prcmu_get_reset_code();
 448 }
 449
 450 void prcmu_ac_wake_req(void);
 451 void prcmu_ac_sleep_req(void);
 452 static inline void prcmu_modem_reset(void)
 453 {
 454         if (cpu_is_u5500())
 455                 return;
 456         else
 457                 return db8500_prcmu_modem_reset();
 458 }
 459
 460 static inline bool prcmu_is_ac_wake_requested(void)
 461 {
 462         if (cpu_is_u5500())
 463                 return db5500_prcmu_is_ac_wake_requested();
 464         else
 465                 return db8500_prcmu_is_ac_wake_requested();
 466 }
 467
 468 static inline int prcmu_set_display_clocks(void)
 469 {
 470         if (cpu_is_u5500())
 471                 return db5500_prcmu_set_display_clocks();
 472         else
 473                 return db8500_prcmu_set_display_clocks();
 474 }
 475
 476 static inline int prcmu_disable_dsipll(void)
 477 {
 478         if (cpu_is_u5500())
 479                 return db5500_prcmu_disable_dsipll();
 480         else
 481                 return db8500_prcmu_disable_dsipll();
 482 }
 483
 484 static inline int prcmu_enable_dsipll(void)
 485 {
 486         if (cpu_is_u5500())
 487                 return db5500_prcmu_enable_dsipll();
 488         else
 489                 return db8500_prcmu_enable_dsipll();
 490 }
 491
 492 static inline int prcmu_config_esram0_deep_sleep(u8 state)
 493 {
 494         if (cpu_is_u5500())
 495                 return -EINVAL;
 496         else
 497                 return db8500_prcmu_config_esram0_deep_sleep(state);
 498 }
 499
 500 static inline int prcmu_config_hotdog(u8 threshold)
 501 {
 502         if (cpu_is_u5500())
 503                 return -EINVAL;
 504         else
 505                 return db8500_prcmu_config_hotdog(threshold);
 506 }
 507
 508 static inline int prcmu_config_hotmon(u8 low, u8 high)
 509 {
 510         if (cpu_is_u5500())
 511                 return -EINVAL;
 512         else
 513                 return db8500_prcmu_config_hotmon(low, high);
 514 }
 515
 516 static inline int prcmu_start_temp_sense(u16 cycles32k)
 517 {
 518         if (cpu_is_u5500())
 519                 return  -EINVAL;
 520         else
 521                 return  db8500_prcmu_start_temp_sense(cycles32k);
 522 }
 523
 524 static inline int prcmu_stop_temp_sense(void)
 525 {
 526         if (cpu_is_u5500())
 527                 return  -EINVAL;
 528         else
 529                 return  db8500_prcmu_stop_temp_sense();
 530 }
 531
 532 static inline u32 prcmu_read(unsigned int reg)
 533 {
 534         if (cpu_is_u5500())
 535                 return -EINVAL;
 536         else
 537                 return db8500_prcmu_read(reg);
 538 }
 539
 540 static inline void prcmu_write(unsigned int reg, u32 value)
 541 {
 542         if (cpu_is_u5500())
 543                 return;
 544         else
 545                 db8500_prcmu_write(reg, value);
 546 }
 547
 548 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
 549 {
 550         if (cpu_is_u5500())
 551                 return;
 552         else
 553                 db8500_prcmu_write_masked(reg, mask, value);
 554 }
 555
 556 static inline int prcmu_enable_a9wdog(u8 id)
 557 {
 558         if (cpu_is_u5500())
 559                 return -EINVAL;
 560         else
 561                 return db8500_prcmu_enable_a9wdog(id);
 562 }
 563
 564 static inline int prcmu_disable_a9wdog(u8 id)
 565 {
 566         if (cpu_is_u5500())
 567                 return -EINVAL;
 568         else
 569                 return db8500_prcmu_disable_a9wdog(id);
 570 }
 571
 572 static inline int prcmu_kick_a9wdog(u8 id)
 573 {
 574         if (cpu_is_u5500())
 575                 return -EINVAL;
 576         else
 577                 return db8500_prcmu_kick_a9wdog(id);
 578 }
 579
 580 static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
 581 {
 582         if (cpu_is_u5500())
 583                 return -EINVAL;
 584         else
 585                 return db8500_prcmu_load_a9wdog(id, timeout);
 586 }
 587
 588 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
 589 {
 590         if (cpu_is_u5500())
 591                 return -EINVAL;
 592         else
 593                 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
 594 }
 595 #else
 596
 597 static inline void __init prcmu_early_init(void) {}
 598
 599 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
 600         bool keep_ap_pll)
 601 {
 602         return 0;
 603 }
 604
 605 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
 606 {
 607         return 0;
 608 }
 609
 610 static inline void prcmu_enable_wakeups(u32 wakeups) {}
 611
 612 static inline void prcmu_disable_wakeups(void) {}
 613
 614 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
 615 {
 616         return -ENOSYS;
 617 }
 618
 619 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
 620 {
 621         return -ENOSYS;
 622 }
 623
 624 static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
 625         u8 size)
 626 {
 627         return -ENOSYS;
 628 }
 629
 630 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 631 {
 632         return 0;
 633 }
 634
 635 static inline int prcmu_request_clock(u8 clock, bool enable)
 636 {
 637         return 0;
 638 }
 639
 640 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
 641 {
 642         return 0;
 643 }
 644
 645 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
 646 {
 647         return 0;
 648 }
 649
 650 static inline unsigned long prcmu_clock_rate(u8 clock)
 651 {
 652         return 0;
 653 }
 654
 655 static inline int prcmu_set_ape_opp(u8 opp)
 656 {
 657         return 0;
 658 }
 659
 660 static inline int prcmu_get_ape_opp(void)
 661 {
 662         return APE_100_OPP;
 663 }
 664
 665 static inline int prcmu_set_arm_opp(u8 opp)
 666 {
 667         return 0;
 668 }
 669
 670 static inline int prcmu_get_arm_opp(void)
 671 {
 672         return ARM_100_OPP;
 673 }
 674
 675 static inline int prcmu_set_ddr_opp(u8 opp)
 676 {
 677         return 0;
 678 }
 679
 680 static inline int prcmu_get_ddr_opp(void)
 681 {
 682         return DDR_100_OPP;
 683 }
 684
 685 static inline void prcmu_system_reset(u16 reset_code) {}
 686
 687 static inline u16 prcmu_get_reset_code(void)
 688 {
 689         return 0;
 690 }
 691
 692 static inline void prcmu_ac_wake_req(void) {}
 693
 694 static inline void prcmu_ac_sleep_req(void) {}
 695
 696 static inline void prcmu_modem_reset(void) {}
 697
 698 static inline bool prcmu_is_ac_wake_requested(void)
 699 {
 700         return false;
 701 }
 702
 703 static inline int prcmu_set_display_clocks(void)
 704 {
 705         return 0;
 706 }
 707
 708 static inline int prcmu_disable_dsipll(void)
 709 {
 710         return 0;
 711 }
 712
 713 static inline int prcmu_enable_dsipll(void)
 714 {
 715         return 0;
 716 }
 717
 718 static inline int prcmu_config_esram0_deep_sleep(u8 state)
 719 {
 720         return 0;
 721 }
 722
 723 static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
 724
 725 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
 726 {
 727         *buf = NULL;
 728 }
 729
 730 static inline int prcmu_config_hotdog(u8 threshold)
 731 {
 732         return 0;
 733 }
 734
 735 static inline int prcmu_config_hotmon(u8 low, u8 high)
 736 {
 737         return 0;
 738 }
 739
 740 static inline int prcmu_start_temp_sense(u16 cycles32k)
 741 {
 742         return 0;
 743 }
 744
 745 static inline int prcmu_stop_temp_sense(void)
 746 {
 747         return 0;
 748 }
 749
 750 static inline u32 prcmu_read(unsigned int reg)
 751 {
 752         return 0;
 753 }
 754
 755 static inline void prcmu_write(unsigned int reg, u32 value) {}
 756
 757 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
 758
 759 #endif
 760
 761 static inline void prcmu_set(unsigned int reg, u32 bits)
 762 {
 763         prcmu_write_masked(reg, bits, bits);
 764 }
 765
 766 static inline void prcmu_clear(unsigned int reg, u32 bits)
 767 {
 768         prcmu_write_masked(reg, bits, 0);
 769 }
 770
 771 #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
 772
 773 /**
 774  * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
 775  */
 776 static inline void prcmu_enable_spi2(void)
 777 {
 778         if (cpu_is_u8500())
 779                 prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
 780 }
 781
 782 /**
 783  * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
 784  */
 785 static inline void prcmu_disable_spi2(void)
 786 {
 787         if (cpu_is_u8500())
 788                 prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
 789 }
 790
 791 /**
 792  * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
 793  * and UARTMOD on OtherAlternateC3.
 794  */
 795 static inline void prcmu_enable_stm_mod_uart(void)
 796 {
 797         if (cpu_is_u8500()) {
 798                 prcmu_set(DB8500_PRCM_GPIOCR,
 799                         (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
 800                          DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
 801         }
 802 }
 803
 804 /**
 805  * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
 806  * and UARTMOD on OtherAlternateC3.
 807  */
 808 static inline void prcmu_disable_stm_mod_uart(void)
 809 {
 810         if (cpu_is_u8500()) {
 811                 prcmu_clear(DB8500_PRCM_GPIOCR,
 812                         (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
 813                          DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
 814         }
 815 }
 816
 817 /**
 818  * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
 819  */
 820 static inline void prcmu_enable_stm_ape(void)
 821 {
 822         if (cpu_is_u8500()) {
 823                 prcmu_set(DB8500_PRCM_GPIOCR,
 824                         DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
 825         }
 826 }
 827
 828 /**
 829  * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
 830  */
 831 static inline void prcmu_disable_stm_ape(void)
 832 {
 833         if (cpu_is_u8500()) {
 834                 prcmu_clear(DB8500_PRCM_GPIOCR,
 835                         DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
 836         }
 837 }
 838
 839 #else
 840
 841 static inline void prcmu_enable_spi2(void) {}
 842 static inline void prcmu_disable_spi2(void) {}
 843 static inline void prcmu_enable_stm_mod_uart(void) {}
 844 static inline void prcmu_disable_stm_mod_uart(void) {}
 845 static inline void prcmu_enable_stm_ape(void) {}
 846 static inline void prcmu_disable_stm_ape(void) {}
 847
 848 #endif
 849
 850 /* PRCMU QoS APE OPP class */
 851 #define PRCMU_QOS_APE_OPP 1
 852 #define PRCMU_QOS_DDR_OPP 2
 853 #define PRCMU_QOS_ARM_OPP 3
 854 #define PRCMU_QOS_DEFAULT_VALUE -1
 855
 856 #ifdef CONFIG_DBX500_PRCMU_QOS_POWER
 857
 858 unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
 859 void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
 860 void prcmu_qos_force_opp(int, s32);
 861 int prcmu_qos_requirement(int pm_qos_class);
 862 int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
 863 int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
 864 void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
 865 int prcmu_qos_add_notifier(int prcmu_qos_class,
 866                            struct notifier_block *notifier);
 867 int prcmu_qos_remove_notifier(int prcmu_qos_class,
 868                               struct notifier_block *notifier);
 869
 870 #else
 871
 872 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
 873 {
 874         return 0;
 875 }
 876
 877 static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
 878
 879 static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
 880
 881 static inline int prcmu_qos_requirement(int prcmu_qos_class)
 882 {
 883         return 0;
 884 }
 885
 886 static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
 887                                             char *name, s32 value)
 888 {
 889         return 0;
 890 }
 891
 892 static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
 893                                                char *name, s32 new_value)
 894 {
 895         return 0;
 896 }
 897
 898 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
 899 {
 900 }
 901
 902 static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
 903                                          struct notifier_block *notifier)
 904 {
 905         return 0;
 906 }
 907 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
 908                                             struct notifier_block *notifier)
 909 {
 910         return 0;
 911 }
 912
 913 #endif
 914
 915 #endif /* __MACH_PRCMU_H */