2 * Copyright (C) ST Ericsson SA 2011
4 * License Terms: GNU General Public License v2
11 #include <linux/interrupt.h>
12 #include <linux/notifier.h>
13 #include <linux/err.h>
15 /* PRCMU Wakeup defines */
16 enum prcmu_wakeup_index {
17 PRCMU_WAKEUP_INDEX_RTC,
18 PRCMU_WAKEUP_INDEX_RTT0,
19 PRCMU_WAKEUP_INDEX_RTT1,
20 PRCMU_WAKEUP_INDEX_HSI0,
21 PRCMU_WAKEUP_INDEX_HSI1,
22 PRCMU_WAKEUP_INDEX_USB,
23 PRCMU_WAKEUP_INDEX_ABB,
24 PRCMU_WAKEUP_INDEX_ABB_FIFO,
25 PRCMU_WAKEUP_INDEX_ARM,
26 PRCMU_WAKEUP_INDEX_CD_IRQ,
27 NUM_PRCMU_WAKEUP_INDICES
29 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
31 /* EPOD (power domain) IDs */
35 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
36 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
37 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
38 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
39 * - EPOD_ID_SGA: power domain for SGA
40 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
41 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
42 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
43 * - NUM_EPOD_ID: number of power domains
45 * TODO: These should be prefixed.
47 #define EPOD_ID_SVAMMDSP 0
48 #define EPOD_ID_SVAPIPE 1
49 #define EPOD_ID_SIAMMDSP 2
50 #define EPOD_ID_SIAPIPE 3
52 #define EPOD_ID_B2R2_MCDE 5
53 #define EPOD_ID_ESRAM12 6
54 #define EPOD_ID_ESRAM34 7
60 #define DB5500_EPOD_ID_BASE 0x0100
61 #define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
62 #define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
63 #define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
64 #define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
65 #define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
66 #define DB5500_NUM_EPOD_ID 7
69 * state definition for EPOD (power domain)
70 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
71 * - EPOD_STATE_OFF: The EPOD is switched off
72 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
74 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
75 * - EPOD_STATE_ON: Same as above, but with clock enabled
77 #define EPOD_STATE_NO_CHANGE 0x00
78 #define EPOD_STATE_OFF 0x01
79 #define EPOD_STATE_RAMRET 0x02
80 #define EPOD_STATE_ON_CLK_OFF 0x03
81 #define EPOD_STATE_ON 0x04
83 /* DB5500 CLKOUT IDs */
89 /* DB5500 CLKOUTx sources */
91 DB5500_CLKOUT_REF_CLK_SEL0,
92 DB5500_CLKOUT_RTC_CLK0_SEL0,
93 DB5500_CLKOUT_ULP_CLK_SEL0,
94 DB5500_CLKOUT_STATIC0,
98 DB5500_CLKOUT_SYSACC0CLK,
99 DB5500_CLKOUT_SOC0PLLCLK,
100 DB5500_CLKOUT_SOC1PLLCLK,
101 DB5500_CLKOUT_DDRPLLCLK,
103 DB5500_CLKOUT_IRDACLK,
109 #define PRCMU_CLKSRC_CLK38M 0x00
110 #define PRCMU_CLKSRC_ACLK 0x01
111 #define PRCMU_CLKSRC_SYSCLK 0x02
112 #define PRCMU_CLKSRC_LCDCLK 0x03
113 #define PRCMU_CLKSRC_SDMMCCLK 0x04
114 #define PRCMU_CLKSRC_TVCLK 0x05
115 #define PRCMU_CLKSRC_TIMCLK 0x06
116 #define PRCMU_CLKSRC_CLK009 0x07
117 /* These are only valid for CLKOUT1: */
118 #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
119 #define PRCMU_CLKSRC_I2CCLK 0x41
120 #define PRCMU_CLKSRC_MSP02CLK 0x42
121 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
122 #define PRCMU_CLKSRC_HSIRXCLK 0x44
123 #define PRCMU_CLKSRC_HSITXCLK 0x45
124 #define PRCMU_CLKSRC_ARMCLKFIX 0x46
125 #define PRCMU_CLKSRC_HDMICLK 0x47
167 PRCMU_NUM_REG_CLOCKS,
168 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
183 * enum ape_opp - APE OPP states definition
185 * @APE_NO_CHANGE: The APE operating point is unchanged
186 * @APE_100_OPP: The new APE operating point is ape100opp
188 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
192 APE_NO_CHANGE = 0x01,
195 APE_50_PARTLY_25_OPP = 0xFF,
199 * enum arm_opp - ARM OPP states definition
201 * @ARM_NO_CHANGE: The ARM operating point is unchanged
202 * @ARM_100_OPP: The new ARM operating point is arm100opp
203 * @ARM_50_OPP: The new ARM operating point is arm50opp
204 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
205 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
206 * @ARM_EXTCLK: The new ARM operating point is armExtClk
210 ARM_NO_CHANGE = 0x01,
214 ARM_MAX_FREQ100OPP = 0x05,
219 * enum ddr_opp - DDR OPP states definition
220 * @DDR_100_OPP: The new DDR operating point is ddr100opp
221 * @DDR_50_OPP: The new DDR operating point is ddr50opp
222 * @DDR_25_OPP: The new DDR operating point is ddr25opp
231 * Definitions for controlling ESRAM0 in deep sleep.
233 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1
234 #define ESRAM0_DEEP_SLEEP_STATE_RET 2
237 * enum ddr_pwrst - DDR power states definition
238 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
240 * @DDR_PWR_STATE_OFFLOWLAT:
241 * @DDR_PWR_STATE_OFFHIGHLAT:
244 DDR_PWR_STATE_UNCHANGED = 0x00,
245 DDR_PWR_STATE_ON = 0x01,
246 DDR_PWR_STATE_OFFLOWLAT = 0x02,
247 DDR_PWR_STATE_OFFHIGHLAT = 0x03
250 #include <linux/mfd/db8500-prcmu.h>
251 #include <linux/mfd/db5500-prcmu.h>
253 #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
257 static inline void __init prcmu_early_init(void)
260 return db5500_prcmu_early_init();
262 return db8500_prcmu_early_init();
265 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
269 return db5500_prcmu_set_power_state(state, keep_ulp_clk,
272 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
276 static inline u8 prcmu_get_power_state_result(void)
281 return db8500_prcmu_get_power_state_result();
284 static inline int prcmu_gic_decouple(void)
289 return db8500_prcmu_gic_decouple();
292 static inline int prcmu_gic_recouple(void)
297 return db8500_prcmu_gic_recouple();
300 static inline bool prcmu_gic_pending_irq(void)
305 return db8500_prcmu_gic_pending_irq();
308 static inline bool prcmu_is_cpu_in_wfi(int cpu)
313 return db8500_prcmu_is_cpu_in_wfi(cpu);
316 static inline int prcmu_copy_gic_settings(void)
321 return db8500_prcmu_copy_gic_settings();
324 static inline bool prcmu_pending_irq(void)
329 return db8500_prcmu_pending_irq();
332 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
337 return db8500_prcmu_set_epod(epod_id, epod_state);
340 static inline void prcmu_enable_wakeups(u32 wakeups)
343 db5500_prcmu_enable_wakeups(wakeups);
345 db8500_prcmu_enable_wakeups(wakeups);
348 static inline void prcmu_disable_wakeups(void)
350 prcmu_enable_wakeups(0);
353 static inline void prcmu_config_abb_event_readout(u32 abb_events)
356 db5500_prcmu_config_abb_event_readout(abb_events);
358 db8500_prcmu_config_abb_event_readout(abb_events);
361 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
364 db5500_prcmu_get_abb_event_buffer(buf);
366 db8500_prcmu_get_abb_event_buffer(buf);
369 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
370 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
371 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
373 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
375 static inline int prcmu_request_clock(u8 clock, bool enable)
378 return db5500_prcmu_request_clock(clock, enable);
380 return db8500_prcmu_request_clock(clock, enable);
383 unsigned long prcmu_clock_rate(u8 clock);
384 long prcmu_round_clock_rate(u8 clock, unsigned long rate);
385 int prcmu_set_clock_rate(u8 clock, unsigned long rate);
387 static inline int prcmu_set_ddr_opp(u8 opp)
392 return db8500_prcmu_set_ddr_opp(opp);
394 static inline int prcmu_get_ddr_opp(void)
399 return db8500_prcmu_get_ddr_opp();
402 static inline int prcmu_set_arm_opp(u8 opp)
407 return db8500_prcmu_set_arm_opp(opp);
410 static inline int prcmu_get_arm_opp(void)
415 return db8500_prcmu_get_arm_opp();
418 static inline int prcmu_set_ape_opp(u8 opp)
423 return db8500_prcmu_set_ape_opp(opp);
426 static inline int prcmu_get_ape_opp(void)
431 return db8500_prcmu_get_ape_opp();
434 static inline void prcmu_system_reset(u16 reset_code)
437 return db5500_prcmu_system_reset(reset_code);
439 return db8500_prcmu_system_reset(reset_code);
442 static inline u16 prcmu_get_reset_code(void)
445 return db5500_prcmu_get_reset_code();
447 return db8500_prcmu_get_reset_code();
450 void prcmu_ac_wake_req(void);
451 void prcmu_ac_sleep_req(void);
452 static inline void prcmu_modem_reset(void)
457 return db8500_prcmu_modem_reset();
460 static inline bool prcmu_is_ac_wake_requested(void)
463 return db5500_prcmu_is_ac_wake_requested();
465 return db8500_prcmu_is_ac_wake_requested();
468 static inline int prcmu_set_display_clocks(void)
471 return db5500_prcmu_set_display_clocks();
473 return db8500_prcmu_set_display_clocks();
476 static inline int prcmu_disable_dsipll(void)
479 return db5500_prcmu_disable_dsipll();
481 return db8500_prcmu_disable_dsipll();
484 static inline int prcmu_enable_dsipll(void)
487 return db5500_prcmu_enable_dsipll();
489 return db8500_prcmu_enable_dsipll();
492 static inline int prcmu_config_esram0_deep_sleep(u8 state)
497 return db8500_prcmu_config_esram0_deep_sleep(state);
500 static inline int prcmu_config_hotdog(u8 threshold)
505 return db8500_prcmu_config_hotdog(threshold);
508 static inline int prcmu_config_hotmon(u8 low, u8 high)
513 return db8500_prcmu_config_hotmon(low, high);
516 static inline int prcmu_start_temp_sense(u16 cycles32k)
521 return db8500_prcmu_start_temp_sense(cycles32k);
524 static inline int prcmu_stop_temp_sense(void)
529 return db8500_prcmu_stop_temp_sense();
532 static inline u32 prcmu_read(unsigned int reg)
537 return db8500_prcmu_read(reg);
540 static inline void prcmu_write(unsigned int reg, u32 value)
545 db8500_prcmu_write(reg, value);
548 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
553 db8500_prcmu_write_masked(reg, mask, value);
556 static inline int prcmu_enable_a9wdog(u8 id)
561 return db8500_prcmu_enable_a9wdog(id);
564 static inline int prcmu_disable_a9wdog(u8 id)
569 return db8500_prcmu_disable_a9wdog(id);
572 static inline int prcmu_kick_a9wdog(u8 id)
577 return db8500_prcmu_kick_a9wdog(id);
580 static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
585 return db8500_prcmu_load_a9wdog(id, timeout);
588 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
593 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
597 static inline void __init prcmu_early_init(void) {}
599 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
605 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
610 static inline void prcmu_enable_wakeups(u32 wakeups) {}
612 static inline void prcmu_disable_wakeups(void) {}
614 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
619 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
624 static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
630 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
635 static inline int prcmu_request_clock(u8 clock, bool enable)
640 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
645 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
650 static inline unsigned long prcmu_clock_rate(u8 clock)
655 static inline int prcmu_set_ape_opp(u8 opp)
660 static inline int prcmu_get_ape_opp(void)
665 static inline int prcmu_set_arm_opp(u8 opp)
670 static inline int prcmu_get_arm_opp(void)
675 static inline int prcmu_set_ddr_opp(u8 opp)
680 static inline int prcmu_get_ddr_opp(void)
685 static inline void prcmu_system_reset(u16 reset_code) {}
687 static inline u16 prcmu_get_reset_code(void)
692 static inline void prcmu_ac_wake_req(void) {}
694 static inline void prcmu_ac_sleep_req(void) {}
696 static inline void prcmu_modem_reset(void) {}
698 static inline bool prcmu_is_ac_wake_requested(void)
703 static inline int prcmu_set_display_clocks(void)
708 static inline int prcmu_disable_dsipll(void)
713 static inline int prcmu_enable_dsipll(void)
718 static inline int prcmu_config_esram0_deep_sleep(u8 state)
723 static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
725 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
730 static inline int prcmu_config_hotdog(u8 threshold)
735 static inline int prcmu_config_hotmon(u8 low, u8 high)
740 static inline int prcmu_start_temp_sense(u16 cycles32k)
745 static inline int prcmu_stop_temp_sense(void)
750 static inline u32 prcmu_read(unsigned int reg)
755 static inline void prcmu_write(unsigned int reg, u32 value) {}
757 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
761 static inline void prcmu_set(unsigned int reg, u32 bits)
763 prcmu_write_masked(reg, bits, bits);
766 static inline void prcmu_clear(unsigned int reg, u32 bits)
768 prcmu_write_masked(reg, bits, 0);
771 #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
774 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
776 static inline void prcmu_enable_spi2(void)
779 prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
783 * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
785 static inline void prcmu_disable_spi2(void)
788 prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
792 * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
793 * and UARTMOD on OtherAlternateC3.
795 static inline void prcmu_enable_stm_mod_uart(void)
797 if (cpu_is_u8500()) {
798 prcmu_set(DB8500_PRCM_GPIOCR,
799 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
800 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
805 * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
806 * and UARTMOD on OtherAlternateC3.
808 static inline void prcmu_disable_stm_mod_uart(void)
810 if (cpu_is_u8500()) {
811 prcmu_clear(DB8500_PRCM_GPIOCR,
812 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
813 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
818 * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
820 static inline void prcmu_enable_stm_ape(void)
822 if (cpu_is_u8500()) {
823 prcmu_set(DB8500_PRCM_GPIOCR,
824 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
829 * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
831 static inline void prcmu_disable_stm_ape(void)
833 if (cpu_is_u8500()) {
834 prcmu_clear(DB8500_PRCM_GPIOCR,
835 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
841 static inline void prcmu_enable_spi2(void) {}
842 static inline void prcmu_disable_spi2(void) {}
843 static inline void prcmu_enable_stm_mod_uart(void) {}
844 static inline void prcmu_disable_stm_mod_uart(void) {}
845 static inline void prcmu_enable_stm_ape(void) {}
846 static inline void prcmu_disable_stm_ape(void) {}
850 /* PRCMU QoS APE OPP class */
851 #define PRCMU_QOS_APE_OPP 1
852 #define PRCMU_QOS_DDR_OPP 2
853 #define PRCMU_QOS_ARM_OPP 3
854 #define PRCMU_QOS_DEFAULT_VALUE -1
856 #ifdef CONFIG_DBX500_PRCMU_QOS_POWER
858 unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
859 void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
860 void prcmu_qos_force_opp(int, s32);
861 int prcmu_qos_requirement(int pm_qos_class);
862 int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
863 int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
864 void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
865 int prcmu_qos_add_notifier(int prcmu_qos_class,
866 struct notifier_block *notifier);
867 int prcmu_qos_remove_notifier(int prcmu_qos_class,
868 struct notifier_block *notifier);
872 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
877 static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
879 static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
881 static inline int prcmu_qos_requirement(int prcmu_qos_class)
886 static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
887 char *name, s32 value)
892 static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
893 char *name, s32 new_value)
898 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
902 static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
903 struct notifier_block *notifier)
907 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
908 struct notifier_block *notifier)
915 #endif /* __MACH_PRCMU_H */