2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <asm/atomic.h>
42 #define MAX_MSIX_P_PORT 17
44 #define MSIX_LEGACY_SZ 4
45 #define MIN_MSIX_P_PORT 5
48 MLX4_FLAG_MSI_X = 1 << 0,
49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
57 MLX4_BOARD_ID_LEN = 64
61 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
62 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
63 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
64 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
65 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
66 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
67 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
68 MLX4_DEV_CAP_FLAG_DPDP = 1 << 12,
69 MLX4_DEV_CAP_FLAG_BLH = 1 << 15,
70 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
71 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
72 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
73 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
74 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
75 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21,
76 MLX4_DEV_CAP_FLAG_IBOE = 1 << 30
80 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
81 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
82 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
83 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
84 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
88 MLX4_EVENT_TYPE_COMP = 0x00,
89 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
90 MLX4_EVENT_TYPE_COMM_EST = 0x02,
91 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
92 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
93 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
94 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
95 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
96 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
97 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
98 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
99 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
100 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
101 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
102 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
103 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
104 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
105 MLX4_EVENT_TYPE_CMD = 0x0a
109 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
110 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
114 MLX4_PERM_LOCAL_READ = 1 << 10,
115 MLX4_PERM_LOCAL_WRITE = 1 << 11,
116 MLX4_PERM_REMOTE_READ = 1 << 12,
117 MLX4_PERM_REMOTE_WRITE = 1 << 13,
118 MLX4_PERM_ATOMIC = 1 << 14
122 MLX4_OPCODE_NOP = 0x00,
123 MLX4_OPCODE_SEND_INVAL = 0x01,
124 MLX4_OPCODE_RDMA_WRITE = 0x08,
125 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
126 MLX4_OPCODE_SEND = 0x0a,
127 MLX4_OPCODE_SEND_IMM = 0x0b,
128 MLX4_OPCODE_LSO = 0x0e,
129 MLX4_OPCODE_RDMA_READ = 0x10,
130 MLX4_OPCODE_ATOMIC_CS = 0x11,
131 MLX4_OPCODE_ATOMIC_FA = 0x12,
132 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
133 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
134 MLX4_OPCODE_BIND_MW = 0x18,
135 MLX4_OPCODE_FMR = 0x19,
136 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
137 MLX4_OPCODE_CONFIG_CMD = 0x1f,
139 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
140 MLX4_RECV_OPCODE_SEND = 0x01,
141 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
142 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
144 MLX4_CQE_OPCODE_ERROR = 0x1e,
145 MLX4_CQE_OPCODE_RESIZE = 0x16,
149 MLX4_STAT_RATE_OFFSET = 5
153 MLX4_PROT_IB_IPV6 = 0,
160 MLX4_MTT_FLAG_PRESENT = 1
163 enum mlx4_qp_region {
164 MLX4_QP_REGION_FW = 0,
165 MLX4_QP_REGION_ETH_ADDR,
166 MLX4_QP_REGION_FC_ADDR,
167 MLX4_QP_REGION_FC_EXCH,
171 enum mlx4_port_type {
172 MLX4_PORT_TYPE_IB = 1,
173 MLX4_PORT_TYPE_ETH = 2,
174 MLX4_PORT_TYPE_AUTO = 3
177 enum mlx4_special_vlan_idx {
178 MLX4_NO_VLAN_IDX = 0,
183 enum mlx4_steer_type {
190 MLX4_NUM_FEXCH = 64 * 1024,
194 MLX4_MAX_FAST_REG_PAGES = 511,
197 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
199 return (major << 32) | (minor << 16) | subminor;
205 int vl_cap[MLX4_MAX_PORTS + 1];
206 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
207 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
208 u64 def_mac[MLX4_MAX_PORTS + 1];
209 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
210 int gid_table_len[MLX4_MAX_PORTS + 1];
211 int pkey_table_len[MLX4_MAX_PORTS + 1];
212 int trans_type[MLX4_MAX_PORTS + 1];
213 int vendor_oui[MLX4_MAX_PORTS + 1];
214 int wavelength[MLX4_MAX_PORTS + 1];
215 u64 trans_code[MLX4_MAX_PORTS + 1];
216 int local_ca_ack_delay;
219 int bf_regs_per_page;
226 int max_qp_init_rdma;
227 int max_qp_dest_rdma;
238 int num_comp_vectors;
243 int fmr_reserved_mtts;
259 u16 stat_rate_support;
261 int loopback_support;
265 u8 port_width_cap[MLX4_MAX_PORTS + 1];
267 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
269 int reserved_qps_base[MLX4_NUM_QP_REGION];
273 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
274 u8 supported_type[MLX4_MAX_PORTS + 1];
276 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
279 struct mlx4_buf_list {
285 struct mlx4_buf_list direct;
286 struct mlx4_buf_list *page_list;
299 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
302 struct mlx4_db_pgdir {
303 struct list_head list;
304 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
305 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
306 unsigned long *bits[2];
311 struct mlx4_ib_user_db_page;
316 struct mlx4_db_pgdir *pgdir;
317 struct mlx4_ib_user_db_page *user_page;
324 struct mlx4_hwq_resources {
342 struct mlx4_mpt_entry *mpt;
344 dma_addr_t dma_handle;
357 void (*comp) (struct mlx4_cq *);
358 void (*event) (struct mlx4_cq *, enum mlx4_event);
360 struct mlx4_uar *uar;
372 struct completion free;
376 void (*event) (struct mlx4_qp *, enum mlx4_event);
381 struct completion free;
385 void (*event) (struct mlx4_srq *, enum mlx4_event);
393 struct completion free;
405 __be32 sl_tclass_flowlabel;
418 __be32 sl_tclass_flowlabel;
427 struct mlx4_eth_av eth;
431 struct pci_dev *pdev;
433 struct mlx4_caps caps;
434 struct radix_tree_root qp_table_tree;
436 char board_id[MLX4_BOARD_ID_LEN];
439 struct mlx4_init_port_param {
453 #define mlx4_foreach_port(port, dev, type) \
454 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
455 if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
456 ~(dev)->caps.port_mask) & 1 << ((port) - 1))
458 #define mlx4_foreach_ib_transport_port(port, dev) \
459 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
460 if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \
461 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
464 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
465 struct mlx4_buf *buf);
466 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
467 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
469 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
470 return buf->direct.buf + offset;
472 return buf->page_list[offset >> PAGE_SHIFT].buf +
473 (offset & (PAGE_SIZE - 1));
476 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
477 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
479 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
480 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
482 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
483 struct mlx4_mtt *mtt);
484 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
485 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
487 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
488 int npages, int page_shift, struct mlx4_mr *mr);
489 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
490 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
491 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
492 int start_index, int npages, u64 *page_list);
493 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
494 struct mlx4_buf *buf);
496 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
497 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
499 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
500 int size, int max_direct);
501 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
504 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
505 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
506 unsigned vector, int collapsed);
507 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
509 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
510 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
512 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
513 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
515 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
516 u64 db_rec, struct mlx4_srq *srq);
517 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
518 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
519 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
521 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
522 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
524 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
525 int block_mcast_loopback, enum mlx4_protocol protocol);
526 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
527 enum mlx4_protocol protocol);
528 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
529 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
530 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
531 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
532 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
534 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn, u8 wrap);
535 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn);
536 int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap);
538 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
539 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
540 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
542 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
543 int npages, u64 iova, u32 *lkey, u32 *rkey);
544 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
545 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
546 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
547 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
548 u32 *lkey, u32 *rkey);
549 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
550 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
551 int mlx4_test_interrupts(struct mlx4_dev *dev);
552 int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
553 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
555 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
556 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
558 #endif /* MLX4_DEVICE_H */