include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  71         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  72 };
  73
  74 enum {
  75         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  76         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  77         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  78         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  79         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  80         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  81         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  82         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  83         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  84         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  85         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  86         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  87         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  88         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  89         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  90         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  91         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  92         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  93         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  94         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  95         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  96         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  97         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  98         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  99         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 100         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 101         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 102         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 103         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 104         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 105         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 106         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 107         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 108         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 109         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 110         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 111         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 112         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 113         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 114         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 115         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 116         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 117         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 118         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 119         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 120         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 121         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 122         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 123         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 124         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 125         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 126         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 127         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 128         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 129         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 130         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 131         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 132         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 133         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 134         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 135         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 136         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 137         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 138         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 139         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 140         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 141         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 143         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 144         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 145         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 146         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 147         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 148         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 149         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 150         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 151         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 152         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 153         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 154         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 155         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 156         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 157         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 158         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 159         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 160         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 161         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 162         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 163         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 164         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 165         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 166         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 167         MLX5_CMD_OP_NOP                           = 0x80d,
 168         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 169         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 170         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 171         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 172         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 173         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 174         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 175         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 176         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 177         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 178         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 179         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 180         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 181         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 182         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 183         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 184         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 185         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 186         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 187         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 188         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 189         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 190         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 191         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 192         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 193         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 194         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 195         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 196         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 197         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 198         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 199         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 200         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 201         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 202         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 203         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 204         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 205         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 206         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 207         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 208         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 209         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 210         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 211         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 212         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 213         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 214         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 215         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 216         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 217         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 218         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 219         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 220         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 221         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 222         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 223         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 224         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 225         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 226         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 227         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 228         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 229         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 230         MLX5_CMD_OP_MAX
 231 };
 232
 233 struct mlx5_ifc_flow_table_fields_supported_bits {
 234         u8         outer_dmac[0x1];
 235         u8         outer_smac[0x1];
 236         u8         outer_ether_type[0x1];
 237         u8         reserved_at_3[0x1];
 238         u8         outer_first_prio[0x1];
 239         u8         outer_first_cfi[0x1];
 240         u8         outer_first_vid[0x1];
 241         u8         reserved_at_7[0x1];
 242         u8         outer_second_prio[0x1];
 243         u8         outer_second_cfi[0x1];
 244         u8         outer_second_vid[0x1];
 245         u8         reserved_at_b[0x1];
 246         u8         outer_sip[0x1];
 247         u8         outer_dip[0x1];
 248         u8         outer_frag[0x1];
 249         u8         outer_ip_protocol[0x1];
 250         u8         outer_ip_ecn[0x1];
 251         u8         outer_ip_dscp[0x1];
 252         u8         outer_udp_sport[0x1];
 253         u8         outer_udp_dport[0x1];
 254         u8         outer_tcp_sport[0x1];
 255         u8         outer_tcp_dport[0x1];
 256         u8         outer_tcp_flags[0x1];
 257         u8         outer_gre_protocol[0x1];
 258         u8         outer_gre_key[0x1];
 259         u8         outer_vxlan_vni[0x1];
 260         u8         reserved_at_1a[0x5];
 261         u8         source_eswitch_port[0x1];
 262
 263         u8         inner_dmac[0x1];
 264         u8         inner_smac[0x1];
 265         u8         inner_ether_type[0x1];
 266         u8         reserved_at_23[0x1];
 267         u8         inner_first_prio[0x1];
 268         u8         inner_first_cfi[0x1];
 269         u8         inner_first_vid[0x1];
 270         u8         reserved_at_27[0x1];
 271         u8         inner_second_prio[0x1];
 272         u8         inner_second_cfi[0x1];
 273         u8         inner_second_vid[0x1];
 274         u8         reserved_at_2b[0x1];
 275         u8         inner_sip[0x1];
 276         u8         inner_dip[0x1];
 277         u8         inner_frag[0x1];
 278         u8         inner_ip_protocol[0x1];
 279         u8         inner_ip_ecn[0x1];
 280         u8         inner_ip_dscp[0x1];
 281         u8         inner_udp_sport[0x1];
 282         u8         inner_udp_dport[0x1];
 283         u8         inner_tcp_sport[0x1];
 284         u8         inner_tcp_dport[0x1];
 285         u8         inner_tcp_flags[0x1];
 286         u8         reserved_at_37[0x9];
 287
 288         u8         reserved_at_40[0x40];
 289 };
 290
 291 struct mlx5_ifc_flow_table_prop_layout_bits {
 292         u8         ft_support[0x1];
 293         u8         reserved_at_1[0x1];
 294         u8         flow_counter[0x1];
 295         u8         flow_modify_en[0x1];
 296         u8         modify_root[0x1];
 297         u8         identified_miss_table_mode[0x1];
 298         u8         flow_table_modify[0x1];
 299         u8         encap[0x1];
 300         u8         decap[0x1];
 301         u8         reserved_at_9[0x17];
 302
 303         u8         reserved_at_20[0x2];
 304         u8         log_max_ft_size[0x6];
 305         u8         reserved_at_28[0x10];
 306         u8         max_ft_level[0x8];
 307
 308         u8         reserved_at_40[0x20];
 309
 310         u8         reserved_at_60[0x18];
 311         u8         log_max_ft_num[0x8];
 312
 313         u8         reserved_at_80[0x18];
 314         u8         log_max_destination[0x8];
 315
 316         u8         reserved_at_a0[0x18];
 317         u8         log_max_flow[0x8];
 318
 319         u8         reserved_at_c0[0x40];
 320
 321         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 322
 323         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 324 };
 325
 326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 327         u8         send[0x1];
 328         u8         receive[0x1];
 329         u8         write[0x1];
 330         u8         read[0x1];
 331         u8         atomic[0x1];
 332         u8         srq_receive[0x1];
 333         u8         reserved_at_6[0x1a];
 334 };
 335
 336 struct mlx5_ifc_ipv4_layout_bits {
 337         u8         reserved_at_0[0x60];
 338
 339         u8         ipv4[0x20];
 340 };
 341
 342 struct mlx5_ifc_ipv6_layout_bits {
 343         u8         ipv6[16][0x8];
 344 };
 345
 346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 347         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 348         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 349         u8         reserved_at_0[0x80];
 350 };
 351
 352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 353         u8         smac_47_16[0x20];
 354
 355         u8         smac_15_0[0x10];
 356         u8         ethertype[0x10];
 357
 358         u8         dmac_47_16[0x20];
 359
 360         u8         dmac_15_0[0x10];
 361         u8         first_prio[0x3];
 362         u8         first_cfi[0x1];
 363         u8         first_vid[0xc];
 364
 365         u8         ip_protocol[0x8];
 366         u8         ip_dscp[0x6];
 367         u8         ip_ecn[0x2];
 368         u8         cvlan_tag[0x1];
 369         u8         svlan_tag[0x1];
 370         u8         frag[0x1];
 371         u8         reserved_at_93[0x4];
 372         u8         tcp_flags[0x9];
 373
 374         u8         tcp_sport[0x10];
 375         u8         tcp_dport[0x10];
 376
 377         u8         reserved_at_c0[0x20];
 378
 379         u8         udp_sport[0x10];
 380         u8         udp_dport[0x10];
 381
 382         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 383
 384         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 385 };
 386
 387 struct mlx5_ifc_fte_match_set_misc_bits {
 388         u8         reserved_at_0[0x8];
 389         u8         source_sqn[0x18];
 390
 391         u8         reserved_at_20[0x10];
 392         u8         source_port[0x10];
 393
 394         u8         outer_second_prio[0x3];
 395         u8         outer_second_cfi[0x1];
 396         u8         outer_second_vid[0xc];
 397         u8         inner_second_prio[0x3];
 398         u8         inner_second_cfi[0x1];
 399         u8         inner_second_vid[0xc];
 400
 401         u8         outer_second_cvlan_tag[0x1];
 402         u8         inner_second_cvlan_tag[0x1];
 403         u8         outer_second_svlan_tag[0x1];
 404         u8         inner_second_svlan_tag[0x1];
 405         u8         reserved_at_64[0xc];
 406         u8         gre_protocol[0x10];
 407
 408         u8         gre_key_h[0x18];
 409         u8         gre_key_l[0x8];
 410
 411         u8         vxlan_vni[0x18];
 412         u8         reserved_at_b8[0x8];
 413
 414         u8         reserved_at_c0[0x20];
 415
 416         u8         reserved_at_e0[0xc];
 417         u8         outer_ipv6_flow_label[0x14];
 418
 419         u8         reserved_at_100[0xc];
 420         u8         inner_ipv6_flow_label[0x14];
 421
 422         u8         reserved_at_120[0xe0];
 423 };
 424
 425 struct mlx5_ifc_cmd_pas_bits {
 426         u8         pa_h[0x20];
 427
 428         u8         pa_l[0x14];
 429         u8         reserved_at_34[0xc];
 430 };
 431
 432 struct mlx5_ifc_uint64_bits {
 433         u8         hi[0x20];
 434
 435         u8         lo[0x20];
 436 };
 437
 438 enum {
 439         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 440         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 441         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 442         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 443         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 444         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 445         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 446         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 447         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 448         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 449 };
 450
 451 struct mlx5_ifc_ads_bits {
 452         u8         fl[0x1];
 453         u8         free_ar[0x1];
 454         u8         reserved_at_2[0xe];
 455         u8         pkey_index[0x10];
 456
 457         u8         reserved_at_20[0x8];
 458         u8         grh[0x1];
 459         u8         mlid[0x7];
 460         u8         rlid[0x10];
 461
 462         u8         ack_timeout[0x5];
 463         u8         reserved_at_45[0x3];
 464         u8         src_addr_index[0x8];
 465         u8         reserved_at_50[0x4];
 466         u8         stat_rate[0x4];
 467         u8         hop_limit[0x8];
 468
 469         u8         reserved_at_60[0x4];
 470         u8         tclass[0x8];
 471         u8         flow_label[0x14];
 472
 473         u8         rgid_rip[16][0x8];
 474
 475         u8         reserved_at_100[0x4];
 476         u8         f_dscp[0x1];
 477         u8         f_ecn[0x1];
 478         u8         reserved_at_106[0x1];
 479         u8         f_eth_prio[0x1];
 480         u8         ecn[0x2];
 481         u8         dscp[0x6];
 482         u8         udp_sport[0x10];
 483
 484         u8         dei_cfi[0x1];
 485         u8         eth_prio[0x3];
 486         u8         sl[0x4];
 487         u8         port[0x8];
 488         u8         rmac_47_32[0x10];
 489
 490         u8         rmac_31_0[0x20];
 491 };
 492
 493 struct mlx5_ifc_flow_table_nic_cap_bits {
 494         u8         nic_rx_multi_path_tirs[0x1];
 495         u8         nic_rx_multi_path_tirs_fts[0x1];
 496         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 497         u8         reserved_at_3[0x1fd];
 498
 499         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 500
 501         u8         reserved_at_400[0x200];
 502
 503         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 504
 505         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 506
 507         u8         reserved_at_a00[0x200];
 508
 509         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 510
 511         u8         reserved_at_e00[0x7200];
 512 };
 513
 514 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 515         u8     reserved_at_0[0x200];
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 518
 519         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 520
 521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 522
 523         u8      reserved_at_800[0x7800];
 524 };
 525
 526 struct mlx5_ifc_e_switch_cap_bits {
 527         u8         vport_svlan_strip[0x1];
 528         u8         vport_cvlan_strip[0x1];
 529         u8         vport_svlan_insert[0x1];
 530         u8         vport_cvlan_insert_if_not_exist[0x1];
 531         u8         vport_cvlan_insert_overwrite[0x1];
 532         u8         reserved_at_5[0x19];
 533         u8         nic_vport_node_guid_modify[0x1];
 534         u8         nic_vport_port_guid_modify[0x1];
 535
 536         u8         vxlan_encap_decap[0x1];
 537         u8         nvgre_encap_decap[0x1];
 538         u8         reserved_at_22[0x9];
 539         u8         log_max_encap_headers[0x5];
 540         u8         reserved_2b[0x6];
 541         u8         max_encap_header_size[0xa];
 542
 543         u8         reserved_40[0x7c0];
 544
 545 };
 546
 547 struct mlx5_ifc_qos_cap_bits {
 548         u8         packet_pacing[0x1];
 549         u8         esw_scheduling[0x1];
 550         u8         esw_bw_share[0x1];
 551         u8         esw_rate_limit[0x1];
 552         u8         reserved_at_4[0x1c];
 553
 554         u8         reserved_at_20[0x20];
 555
 556         u8         packet_pacing_max_rate[0x20];
 557
 558         u8         packet_pacing_min_rate[0x20];
 559
 560         u8         reserved_at_80[0x10];
 561         u8         packet_pacing_rate_table_size[0x10];
 562
 563         u8         esw_element_type[0x10];
 564         u8         esw_tsar_type[0x10];
 565
 566         u8         reserved_at_c0[0x10];
 567         u8         max_qos_para_vport[0x10];
 568
 569         u8         max_tsar_bw_share[0x20];
 570
 571         u8         reserved_at_100[0x700];
 572 };
 573
 574 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 575         u8         csum_cap[0x1];
 576         u8         vlan_cap[0x1];
 577         u8         lro_cap[0x1];
 578         u8         lro_psh_flag[0x1];
 579         u8         lro_time_stamp[0x1];
 580         u8         reserved_at_5[0x3];
 581         u8         self_lb_en_modifiable[0x1];
 582         u8         reserved_at_9[0x2];
 583         u8         max_lso_cap[0x5];
 584         u8         multi_pkt_send_wqe[0x2];
 585         u8         wqe_inline_mode[0x2];
 586         u8         rss_ind_tbl_cap[0x4];
 587         u8         reg_umr_sq[0x1];
 588         u8         scatter_fcs[0x1];
 589         u8         reserved_at_1a[0x1];
 590         u8         tunnel_lso_const_out_ip_id[0x1];
 591         u8         reserved_at_1c[0x2];
 592         u8         tunnel_statless_gre[0x1];
 593         u8         tunnel_stateless_vxlan[0x1];
 594
 595         u8         reserved_at_20[0x20];
 596
 597         u8         reserved_at_40[0x10];
 598         u8         lro_min_mss_size[0x10];
 599
 600         u8         reserved_at_60[0x120];
 601
 602         u8         lro_timer_supported_periods[4][0x20];
 603
 604         u8         reserved_at_200[0x600];
 605 };
 606
 607 struct mlx5_ifc_roce_cap_bits {
 608         u8         roce_apm[0x1];
 609         u8         reserved_at_1[0x1f];
 610
 611         u8         reserved_at_20[0x60];
 612
 613         u8         reserved_at_80[0xc];
 614         u8         l3_type[0x4];
 615         u8         reserved_at_90[0x8];
 616         u8         roce_version[0x8];
 617
 618         u8         reserved_at_a0[0x10];
 619         u8         r_roce_dest_udp_port[0x10];
 620
 621         u8         r_roce_max_src_udp_port[0x10];
 622         u8         r_roce_min_src_udp_port[0x10];
 623
 624         u8         reserved_at_e0[0x10];
 625         u8         roce_address_table_size[0x10];
 626
 627         u8         reserved_at_100[0x700];
 628 };
 629
 630 enum {
 631         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 632         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 633         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 634         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 635         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 636         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 637         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 638         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 639         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 640 };
 641
 642 enum {
 643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 648         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 649         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 650         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 651         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 652 };
 653
 654 struct mlx5_ifc_atomic_caps_bits {
 655         u8         reserved_at_0[0x40];
 656
 657         u8         atomic_req_8B_endianess_mode[0x2];
 658         u8         reserved_at_42[0x4];
 659         u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 660
 661         u8         reserved_at_47[0x19];
 662
 663         u8         reserved_at_60[0x20];
 664
 665         u8         reserved_at_80[0x10];
 666         u8         atomic_operations[0x10];
 667
 668         u8         reserved_at_a0[0x10];
 669         u8         atomic_size_qp[0x10];
 670
 671         u8         reserved_at_c0[0x10];
 672         u8         atomic_size_dc[0x10];
 673
 674         u8         reserved_at_e0[0x720];
 675 };
 676
 677 struct mlx5_ifc_odp_cap_bits {
 678         u8         reserved_at_0[0x40];
 679
 680         u8         sig[0x1];
 681         u8         reserved_at_41[0x1f];
 682
 683         u8         reserved_at_60[0x20];
 684
 685         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 686
 687         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 688
 689         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 690
 691         u8         reserved_at_e0[0x720];
 692 };
 693
 694 struct mlx5_ifc_calc_op {
 695         u8        reserved_at_0[0x10];
 696         u8        reserved_at_10[0x9];
 697         u8        op_swap_endianness[0x1];
 698         u8        op_min[0x1];
 699         u8        op_xor[0x1];
 700         u8        op_or[0x1];
 701         u8        op_and[0x1];
 702         u8        op_max[0x1];
 703         u8        op_add[0x1];
 704 };
 705
 706 struct mlx5_ifc_vector_calc_cap_bits {
 707         u8         calc_matrix[0x1];
 708         u8         reserved_at_1[0x1f];
 709         u8         reserved_at_20[0x8];
 710         u8         max_vec_count[0x8];
 711         u8         reserved_at_30[0xd];
 712         u8         max_chunk_size[0x3];
 713         struct mlx5_ifc_calc_op calc0;
 714         struct mlx5_ifc_calc_op calc1;
 715         struct mlx5_ifc_calc_op calc2;
 716         struct mlx5_ifc_calc_op calc3;
 717
 718         u8         reserved_at_e0[0x720];
 719 };
 720
 721 enum {
 722         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 723         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 724         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 725 };
 726
 727 enum {
 728         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 729         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 730 };
 731
 732 enum {
 733         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 734         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 735         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 736         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 737         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 738 };
 739
 740 enum {
 741         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 742         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 743         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 744         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 745         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 746         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 747 };
 748
 749 enum {
 750         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 751         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 752 };
 753
 754 enum {
 755         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 756         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 757         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 758 };
 759
 760 enum {
 761         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 762         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 763 };
 764
 765 struct mlx5_ifc_cmd_hca_cap_bits {
 766         u8         reserved_at_0[0x80];
 767
 768         u8         log_max_srq_sz[0x8];
 769         u8         log_max_qp_sz[0x8];
 770         u8         reserved_at_90[0xb];
 771         u8         log_max_qp[0x5];
 772
 773         u8         reserved_at_a0[0xb];
 774         u8         log_max_srq[0x5];
 775         u8         reserved_at_b0[0x10];
 776
 777         u8         reserved_at_c0[0x8];
 778         u8         log_max_cq_sz[0x8];
 779         u8         reserved_at_d0[0xb];
 780         u8         log_max_cq[0x5];
 781
 782         u8         log_max_eq_sz[0x8];
 783         u8         reserved_at_e8[0x2];
 784         u8         log_max_mkey[0x6];
 785         u8         reserved_at_f0[0xc];
 786         u8         log_max_eq[0x4];
 787
 788         u8         max_indirection[0x8];
 789         u8         fixed_buffer_size[0x1];
 790         u8         log_max_mrw_sz[0x7];
 791         u8         reserved_at_110[0x2];
 792         u8         log_max_bsf_list_size[0x6];
 793         u8         umr_extended_translation_offset[0x1];
 794         u8         null_mkey[0x1];
 795         u8         log_max_klm_list_size[0x6];
 796
 797         u8         reserved_at_120[0xa];
 798         u8         log_max_ra_req_dc[0x6];
 799         u8         reserved_at_130[0xa];
 800         u8         log_max_ra_res_dc[0x6];
 801
 802         u8         reserved_at_140[0xa];
 803         u8         log_max_ra_req_qp[0x6];
 804         u8         reserved_at_150[0xa];
 805         u8         log_max_ra_res_qp[0x6];
 806
 807         u8         end_pad[0x1];
 808         u8         cc_query_allowed[0x1];
 809         u8         cc_modify_allowed[0x1];
 810         u8         start_pad[0x1];
 811         u8         cache_line_128byte[0x1];
 812         u8         reserved_at_163[0xb];
 813         u8         gid_table_size[0x10];
 814
 815         u8         out_of_seq_cnt[0x1];
 816         u8         vport_counters[0x1];
 817         u8         retransmission_q_counters[0x1];
 818         u8         reserved_at_183[0x1];
 819         u8         modify_rq_counter_set_id[0x1];
 820         u8         reserved_at_185[0x1];
 821         u8         max_qp_cnt[0xa];
 822         u8         pkey_table_size[0x10];
 823
 824         u8         vport_group_manager[0x1];
 825         u8         vhca_group_manager[0x1];
 826         u8         ib_virt[0x1];
 827         u8         eth_virt[0x1];
 828         u8         reserved_at_1a4[0x1];
 829         u8         ets[0x1];
 830         u8         nic_flow_table[0x1];
 831         u8         eswitch_flow_table[0x1];
 832         u8         early_vf_enable[0x1];
 833         u8         mcam_reg[0x1];
 834         u8         pcam_reg[0x1];
 835         u8         local_ca_ack_delay[0x5];
 836         u8         port_module_event[0x1];
 837         u8         reserved_at_1b1[0x1];
 838         u8         ports_check[0x1];
 839         u8         reserved_at_1b3[0x1];
 840         u8         disable_link_up[0x1];
 841         u8         beacon_led[0x1];
 842         u8         port_type[0x2];
 843         u8         num_ports[0x8];
 844
 845         u8         reserved_at_1c0[0x1];
 846         u8         pps[0x1];
 847         u8         pps_modify[0x1];
 848         u8         log_max_msg[0x5];
 849         u8         reserved_at_1c8[0x4];
 850         u8         max_tc[0x4];
 851         u8         reserved_at_1d0[0x1];
 852         u8         dcbx[0x1];
 853         u8         reserved_at_1d2[0x4];
 854         u8         rol_s[0x1];
 855         u8         rol_g[0x1];
 856         u8         reserved_at_1d8[0x1];
 857         u8         wol_s[0x1];
 858         u8         wol_g[0x1];
 859         u8         wol_a[0x1];
 860         u8         wol_b[0x1];
 861         u8         wol_m[0x1];
 862         u8         wol_u[0x1];
 863         u8         wol_p[0x1];
 864
 865         u8         stat_rate_support[0x10];
 866         u8         reserved_at_1f0[0xc];
 867         u8         cqe_version[0x4];
 868
 869         u8         compact_address_vector[0x1];
 870         u8         striding_rq[0x1];
 871         u8         reserved_at_202[0x2];
 872         u8         ipoib_basic_offloads[0x1];
 873         u8         reserved_at_205[0xa];
 874         u8         drain_sigerr[0x1];
 875         u8         cmdif_checksum[0x2];
 876         u8         sigerr_cqe[0x1];
 877         u8         reserved_at_213[0x1];
 878         u8         wq_signature[0x1];
 879         u8         sctr_data_cqe[0x1];
 880         u8         reserved_at_216[0x1];
 881         u8         sho[0x1];
 882         u8         tph[0x1];
 883         u8         rf[0x1];
 884         u8         dct[0x1];
 885         u8         qos[0x1];
 886         u8         eth_net_offloads[0x1];
 887         u8         roce[0x1];
 888         u8         atomic[0x1];
 889         u8         reserved_at_21f[0x1];
 890
 891         u8         cq_oi[0x1];
 892         u8         cq_resize[0x1];
 893         u8         cq_moderation[0x1];
 894         u8         reserved_at_223[0x3];
 895         u8         cq_eq_remap[0x1];
 896         u8         pg[0x1];
 897         u8         block_lb_mc[0x1];
 898         u8         reserved_at_229[0x1];
 899         u8         scqe_break_moderation[0x1];
 900         u8         cq_period_start_from_cqe[0x1];
 901         u8         cd[0x1];
 902         u8         reserved_at_22d[0x1];
 903         u8         apm[0x1];
 904         u8         vector_calc[0x1];
 905         u8         umr_ptr_rlky[0x1];
 906         u8         imaicl[0x1];
 907         u8         reserved_at_232[0x4];
 908         u8         qkv[0x1];
 909         u8         pkv[0x1];
 910         u8         set_deth_sqpn[0x1];
 911         u8         reserved_at_239[0x3];
 912         u8         xrc[0x1];
 913         u8         ud[0x1];
 914         u8         uc[0x1];
 915         u8         rc[0x1];
 916
 917         u8         uar_4k[0x1];
 918         u8         reserved_at_241[0x9];
 919         u8         uar_sz[0x6];
 920         u8         reserved_at_250[0x8];
 921         u8         log_pg_sz[0x8];
 922
 923         u8         bf[0x1];
 924         u8         driver_version[0x1];
 925         u8         pad_tx_eth_packet[0x1];
 926         u8         reserved_at_263[0x8];
 927         u8         log_bf_reg_size[0x5];
 928
 929         u8         reserved_at_270[0xb];
 930         u8         lag_master[0x1];
 931         u8         num_lag_ports[0x4];
 932
 933         u8         reserved_at_280[0x10];
 934         u8         max_wqe_sz_sq[0x10];
 935
 936         u8         reserved_at_2a0[0x10];
 937         u8         max_wqe_sz_rq[0x10];
 938
 939         u8         reserved_at_2c0[0x10];
 940         u8         max_wqe_sz_sq_dc[0x10];
 941
 942         u8         reserved_at_2e0[0x7];
 943         u8         max_qp_mcg[0x19];
 944
 945         u8         reserved_at_300[0x18];
 946         u8         log_max_mcg[0x8];
 947
 948         u8         reserved_at_320[0x3];
 949         u8         log_max_transport_domain[0x5];
 950         u8         reserved_at_328[0x3];
 951         u8         log_max_pd[0x5];
 952         u8         reserved_at_330[0xb];
 953         u8         log_max_xrcd[0x5];
 954
 955         u8         reserved_at_340[0x8];
 956         u8         log_max_flow_counter_bulk[0x8];
 957         u8         max_flow_counter[0x10];
 958
 959
 960         u8         reserved_at_360[0x3];
 961         u8         log_max_rq[0x5];
 962         u8         reserved_at_368[0x3];
 963         u8         log_max_sq[0x5];
 964         u8         reserved_at_370[0x3];
 965         u8         log_max_tir[0x5];
 966         u8         reserved_at_378[0x3];
 967         u8         log_max_tis[0x5];
 968
 969         u8         basic_cyclic_rcv_wqe[0x1];
 970         u8         reserved_at_381[0x2];
 971         u8         log_max_rmp[0x5];
 972         u8         reserved_at_388[0x3];
 973         u8         log_max_rqt[0x5];
 974         u8         reserved_at_390[0x3];
 975         u8         log_max_rqt_size[0x5];
 976         u8         reserved_at_398[0x3];
 977         u8         log_max_tis_per_sq[0x5];
 978
 979         u8         reserved_at_3a0[0x3];
 980         u8         log_max_stride_sz_rq[0x5];
 981         u8         reserved_at_3a8[0x3];
 982         u8         log_min_stride_sz_rq[0x5];
 983         u8         reserved_at_3b0[0x3];
 984         u8         log_max_stride_sz_sq[0x5];
 985         u8         reserved_at_3b8[0x3];
 986         u8         log_min_stride_sz_sq[0x5];
 987
 988         u8         reserved_at_3c0[0x1b];
 989         u8         log_max_wq_sz[0x5];
 990
 991         u8         nic_vport_change_event[0x1];
 992         u8         reserved_at_3e1[0xa];
 993         u8         log_max_vlan_list[0x5];
 994         u8         reserved_at_3f0[0x3];
 995         u8         log_max_current_mc_list[0x5];
 996         u8         reserved_at_3f8[0x3];
 997         u8         log_max_current_uc_list[0x5];
 998
 999         u8         reserved_at_400[0x80];
1000
1001         u8         reserved_at_480[0x3];
1002         u8         log_max_l2_table[0x5];
1003         u8         reserved_at_488[0x8];
1004         u8         log_uar_page_sz[0x10];
1005
1006         u8         reserved_at_4a0[0x20];
1007         u8         device_frequency_mhz[0x20];
1008         u8         device_frequency_khz[0x20];
1009
1010         u8         reserved_at_500[0x20];
1011         u8         num_of_uars_per_page[0x20];
1012         u8         reserved_at_540[0x40];
1013
1014         u8         reserved_at_580[0x3f];
1015         u8         cqe_compression[0x1];
1016
1017         u8         cqe_compression_timeout[0x10];
1018         u8         cqe_compression_max_num[0x10];
1019
1020         u8         reserved_at_5e0[0x10];
1021         u8         tag_matching[0x1];
1022         u8         rndv_offload_rc[0x1];
1023         u8         rndv_offload_dc[0x1];
1024         u8         log_tag_matching_list_sz[0x5];
1025         u8         reserved_at_5f8[0x3];
1026         u8         log_max_xrq[0x5];
1027
1028         u8         reserved_at_600[0x200];
1029 };
1030
1031 enum mlx5_flow_destination_type {
1032         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1033         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1034         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1035
1036         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1037 };
1038
1039 struct mlx5_ifc_dest_format_struct_bits {
1040         u8         destination_type[0x8];
1041         u8         destination_id[0x18];
1042
1043         u8         reserved_at_20[0x20];
1044 };
1045
1046 struct mlx5_ifc_flow_counter_list_bits {
1047         u8         clear[0x1];
1048         u8         num_of_counters[0xf];
1049         u8         flow_counter_id[0x10];
1050
1051         u8         reserved_at_20[0x20];
1052 };
1053
1054 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1055         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1056         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1057         u8         reserved_at_0[0x40];
1058 };
1059
1060 struct mlx5_ifc_fte_match_param_bits {
1061         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1062
1063         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1064
1065         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1066
1067         u8         reserved_at_600[0xa00];
1068 };
1069
1070 enum {
1071         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1072         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1073         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1074         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1075         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1076 };
1077
1078 struct mlx5_ifc_rx_hash_field_select_bits {
1079         u8         l3_prot_type[0x1];
1080         u8         l4_prot_type[0x1];
1081         u8         selected_fields[0x1e];
1082 };
1083
1084 enum {
1085         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1086         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1087 };
1088
1089 enum {
1090         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1091         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1092 };
1093
1094 struct mlx5_ifc_wq_bits {
1095         u8         wq_type[0x4];
1096         u8         wq_signature[0x1];
1097         u8         end_padding_mode[0x2];
1098         u8         cd_slave[0x1];
1099         u8         reserved_at_8[0x18];
1100
1101         u8         hds_skip_first_sge[0x1];
1102         u8         log2_hds_buf_size[0x3];
1103         u8         reserved_at_24[0x7];
1104         u8         page_offset[0x5];
1105         u8         lwm[0x10];
1106
1107         u8         reserved_at_40[0x8];
1108         u8         pd[0x18];
1109
1110         u8         reserved_at_60[0x8];
1111         u8         uar_page[0x18];
1112
1113         u8         dbr_addr[0x40];
1114
1115         u8         hw_counter[0x20];
1116
1117         u8         sw_counter[0x20];
1118
1119         u8         reserved_at_100[0xc];
1120         u8         log_wq_stride[0x4];
1121         u8         reserved_at_110[0x3];
1122         u8         log_wq_pg_sz[0x5];
1123         u8         reserved_at_118[0x3];
1124         u8         log_wq_sz[0x5];
1125
1126         u8         reserved_at_120[0x15];
1127         u8         log_wqe_num_of_strides[0x3];
1128         u8         two_byte_shift_en[0x1];
1129         u8         reserved_at_139[0x4];
1130         u8         log_wqe_stride_size[0x3];
1131
1132         u8         reserved_at_140[0x4c0];
1133
1134         struct mlx5_ifc_cmd_pas_bits pas[0];
1135 };
1136
1137 struct mlx5_ifc_rq_num_bits {
1138         u8         reserved_at_0[0x8];
1139         u8         rq_num[0x18];
1140 };
1141
1142 struct mlx5_ifc_mac_address_layout_bits {
1143         u8         reserved_at_0[0x10];
1144         u8         mac_addr_47_32[0x10];
1145
1146         u8         mac_addr_31_0[0x20];
1147 };
1148
1149 struct mlx5_ifc_vlan_layout_bits {
1150         u8         reserved_at_0[0x14];
1151         u8         vlan[0x0c];
1152
1153         u8         reserved_at_20[0x20];
1154 };
1155
1156 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1157         u8         reserved_at_0[0xa0];
1158
1159         u8         min_time_between_cnps[0x20];
1160
1161         u8         reserved_at_c0[0x12];
1162         u8         cnp_dscp[0x6];
1163         u8         reserved_at_d8[0x5];
1164         u8         cnp_802p_prio[0x3];
1165
1166         u8         reserved_at_e0[0x720];
1167 };
1168
1169 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1170         u8         reserved_at_0[0x60];
1171
1172         u8         reserved_at_60[0x4];
1173         u8         clamp_tgt_rate[0x1];
1174         u8         reserved_at_65[0x3];
1175         u8         clamp_tgt_rate_after_time_inc[0x1];
1176         u8         reserved_at_69[0x17];
1177
1178         u8         reserved_at_80[0x20];
1179
1180         u8         rpg_time_reset[0x20];
1181
1182         u8         rpg_byte_reset[0x20];
1183
1184         u8         rpg_threshold[0x20];
1185
1186         u8         rpg_max_rate[0x20];
1187
1188         u8         rpg_ai_rate[0x20];
1189
1190         u8         rpg_hai_rate[0x20];
1191
1192         u8         rpg_gd[0x20];
1193
1194         u8         rpg_min_dec_fac[0x20];
1195
1196         u8         rpg_min_rate[0x20];
1197
1198         u8         reserved_at_1c0[0xe0];
1199
1200         u8         rate_to_set_on_first_cnp[0x20];
1201
1202         u8         dce_tcp_g[0x20];
1203
1204         u8         dce_tcp_rtt[0x20];
1205
1206         u8         rate_reduce_monitor_period[0x20];
1207
1208         u8         reserved_at_320[0x20];
1209
1210         u8         initial_alpha_value[0x20];
1211
1212         u8         reserved_at_360[0x4a0];
1213 };
1214
1215 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1216         u8         reserved_at_0[0x80];
1217
1218         u8         rppp_max_rps[0x20];
1219
1220         u8         rpg_time_reset[0x20];
1221
1222         u8         rpg_byte_reset[0x20];
1223
1224         u8         rpg_threshold[0x20];
1225
1226         u8         rpg_max_rate[0x20];
1227
1228         u8         rpg_ai_rate[0x20];
1229
1230         u8         rpg_hai_rate[0x20];
1231
1232         u8         rpg_gd[0x20];
1233
1234         u8         rpg_min_dec_fac[0x20];
1235
1236         u8         rpg_min_rate[0x20];
1237
1238         u8         reserved_at_1c0[0x640];
1239 };
1240
1241 enum {
1242         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1243         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1244         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1245 };
1246
1247 struct mlx5_ifc_resize_field_select_bits {
1248         u8         resize_field_select[0x20];
1249 };
1250
1251 enum {
1252         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1253         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1254         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1255         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1256 };
1257
1258 struct mlx5_ifc_modify_field_select_bits {
1259         u8         modify_field_select[0x20];
1260 };
1261
1262 struct mlx5_ifc_field_select_r_roce_np_bits {
1263         u8         field_select_r_roce_np[0x20];
1264 };
1265
1266 struct mlx5_ifc_field_select_r_roce_rp_bits {
1267         u8         field_select_r_roce_rp[0x20];
1268 };
1269
1270 enum {
1271         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1272         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1273         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1274         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1275         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1276         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1277         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1278         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1279         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1280         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1281 };
1282
1283 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1284         u8         field_select_8021qaurp[0x20];
1285 };
1286
1287 struct mlx5_ifc_phys_layer_cntrs_bits {
1288         u8         time_since_last_clear_high[0x20];
1289
1290         u8         time_since_last_clear_low[0x20];
1291
1292         u8         symbol_errors_high[0x20];
1293
1294         u8         symbol_errors_low[0x20];
1295
1296         u8         sync_headers_errors_high[0x20];
1297
1298         u8         sync_headers_errors_low[0x20];
1299
1300         u8         edpl_bip_errors_lane0_high[0x20];
1301
1302         u8         edpl_bip_errors_lane0_low[0x20];
1303
1304         u8         edpl_bip_errors_lane1_high[0x20];
1305
1306         u8         edpl_bip_errors_lane1_low[0x20];
1307
1308         u8         edpl_bip_errors_lane2_high[0x20];
1309
1310         u8         edpl_bip_errors_lane2_low[0x20];
1311
1312         u8         edpl_bip_errors_lane3_high[0x20];
1313
1314         u8         edpl_bip_errors_lane3_low[0x20];
1315
1316         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1317
1318         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1319
1320         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1321
1322         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1323
1324         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1325
1326         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1327
1328         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1329
1330         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1331
1332         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1333
1334         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1335
1336         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1337
1338         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1339
1340         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1341
1342         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1343
1344         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1345
1346         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1347
1348         u8         rs_fec_corrected_blocks_high[0x20];
1349
1350         u8         rs_fec_corrected_blocks_low[0x20];
1351
1352         u8         rs_fec_uncorrectable_blocks_high[0x20];
1353
1354         u8         rs_fec_uncorrectable_blocks_low[0x20];
1355
1356         u8         rs_fec_no_errors_blocks_high[0x20];
1357
1358         u8         rs_fec_no_errors_blocks_low[0x20];
1359
1360         u8         rs_fec_single_error_blocks_high[0x20];
1361
1362         u8         rs_fec_single_error_blocks_low[0x20];
1363
1364         u8         rs_fec_corrected_symbols_total_high[0x20];
1365
1366         u8         rs_fec_corrected_symbols_total_low[0x20];
1367
1368         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1369
1370         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1371
1372         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1373
1374         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1375
1376         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1377
1378         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1379
1380         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1381
1382         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1383
1384         u8         link_down_events[0x20];
1385
1386         u8         successful_recovery_events[0x20];
1387
1388         u8         reserved_at_640[0x180];
1389 };
1390
1391 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1392         u8         time_since_last_clear_high[0x20];
1393
1394         u8         time_since_last_clear_low[0x20];
1395
1396         u8         phy_received_bits_high[0x20];
1397
1398         u8         phy_received_bits_low[0x20];
1399
1400         u8         phy_symbol_errors_high[0x20];
1401
1402         u8         phy_symbol_errors_low[0x20];
1403
1404         u8         phy_corrected_bits_high[0x20];
1405
1406         u8         phy_corrected_bits_low[0x20];
1407
1408         u8         phy_corrected_bits_lane0_high[0x20];
1409
1410         u8         phy_corrected_bits_lane0_low[0x20];
1411
1412         u8         phy_corrected_bits_lane1_high[0x20];
1413
1414         u8         phy_corrected_bits_lane1_low[0x20];
1415
1416         u8         phy_corrected_bits_lane2_high[0x20];
1417
1418         u8         phy_corrected_bits_lane2_low[0x20];
1419
1420         u8         phy_corrected_bits_lane3_high[0x20];
1421
1422         u8         phy_corrected_bits_lane3_low[0x20];
1423
1424         u8         reserved_at_200[0x5c0];
1425 };
1426
1427 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1428         u8         symbol_error_counter[0x10];
1429
1430         u8         link_error_recovery_counter[0x8];
1431
1432         u8         link_downed_counter[0x8];
1433
1434         u8         port_rcv_errors[0x10];
1435
1436         u8         port_rcv_remote_physical_errors[0x10];
1437
1438         u8         port_rcv_switch_relay_errors[0x10];
1439
1440         u8         port_xmit_discards[0x10];
1441
1442         u8         port_xmit_constraint_errors[0x8];
1443
1444         u8         port_rcv_constraint_errors[0x8];
1445
1446         u8         reserved_at_70[0x8];
1447
1448         u8         link_overrun_errors[0x8];
1449
1450         u8         reserved_at_80[0x10];
1451
1452         u8         vl_15_dropped[0x10];
1453
1454         u8         reserved_at_a0[0xa0];
1455 };
1456
1457 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1458         u8         transmit_queue_high[0x20];
1459
1460         u8         transmit_queue_low[0x20];
1461
1462         u8         reserved_at_40[0x780];
1463 };
1464
1465 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1466         u8         rx_octets_high[0x20];
1467
1468         u8         rx_octets_low[0x20];
1469
1470         u8         reserved_at_40[0xc0];
1471
1472         u8         rx_frames_high[0x20];
1473
1474         u8         rx_frames_low[0x20];
1475
1476         u8         tx_octets_high[0x20];
1477
1478         u8         tx_octets_low[0x20];
1479
1480         u8         reserved_at_180[0xc0];
1481
1482         u8         tx_frames_high[0x20];
1483
1484         u8         tx_frames_low[0x20];
1485
1486         u8         rx_pause_high[0x20];
1487
1488         u8         rx_pause_low[0x20];
1489
1490         u8         rx_pause_duration_high[0x20];
1491
1492         u8         rx_pause_duration_low[0x20];
1493
1494         u8         tx_pause_high[0x20];
1495
1496         u8         tx_pause_low[0x20];
1497
1498         u8         tx_pause_duration_high[0x20];
1499
1500         u8         tx_pause_duration_low[0x20];
1501
1502         u8         rx_pause_transition_high[0x20];
1503
1504         u8         rx_pause_transition_low[0x20];
1505
1506         u8         reserved_at_3c0[0x400];
1507 };
1508
1509 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1510         u8         port_transmit_wait_high[0x20];
1511
1512         u8         port_transmit_wait_low[0x20];
1513
1514         u8         reserved_at_40[0x780];
1515 };
1516
1517 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1518         u8         dot3stats_alignment_errors_high[0x20];
1519
1520         u8         dot3stats_alignment_errors_low[0x20];
1521
1522         u8         dot3stats_fcs_errors_high[0x20];
1523
1524         u8         dot3stats_fcs_errors_low[0x20];
1525
1526         u8         dot3stats_single_collision_frames_high[0x20];
1527
1528         u8         dot3stats_single_collision_frames_low[0x20];
1529
1530         u8         dot3stats_multiple_collision_frames_high[0x20];
1531
1532         u8         dot3stats_multiple_collision_frames_low[0x20];
1533
1534         u8         dot3stats_sqe_test_errors_high[0x20];
1535
1536         u8         dot3stats_sqe_test_errors_low[0x20];
1537
1538         u8         dot3stats_deferred_transmissions_high[0x20];
1539
1540         u8         dot3stats_deferred_transmissions_low[0x20];
1541
1542         u8         dot3stats_late_collisions_high[0x20];
1543
1544         u8         dot3stats_late_collisions_low[0x20];
1545
1546         u8         dot3stats_excessive_collisions_high[0x20];
1547
1548         u8         dot3stats_excessive_collisions_low[0x20];
1549
1550         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1551
1552         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1553
1554         u8         dot3stats_carrier_sense_errors_high[0x20];
1555
1556         u8         dot3stats_carrier_sense_errors_low[0x20];
1557
1558         u8         dot3stats_frame_too_longs_high[0x20];
1559
1560         u8         dot3stats_frame_too_longs_low[0x20];
1561
1562         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1563
1564         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1565
1566         u8         dot3stats_symbol_errors_high[0x20];
1567
1568         u8         dot3stats_symbol_errors_low[0x20];
1569
1570         u8         dot3control_in_unknown_opcodes_high[0x20];
1571
1572         u8         dot3control_in_unknown_opcodes_low[0x20];
1573
1574         u8         dot3in_pause_frames_high[0x20];
1575
1576         u8         dot3in_pause_frames_low[0x20];
1577
1578         u8         dot3out_pause_frames_high[0x20];
1579
1580         u8         dot3out_pause_frames_low[0x20];
1581
1582         u8         reserved_at_400[0x3c0];
1583 };
1584
1585 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1586         u8         ether_stats_drop_events_high[0x20];
1587
1588         u8         ether_stats_drop_events_low[0x20];
1589
1590         u8         ether_stats_octets_high[0x20];
1591
1592         u8         ether_stats_octets_low[0x20];
1593
1594         u8         ether_stats_pkts_high[0x20];
1595
1596         u8         ether_stats_pkts_low[0x20];
1597
1598         u8         ether_stats_broadcast_pkts_high[0x20];
1599
1600         u8         ether_stats_broadcast_pkts_low[0x20];
1601
1602         u8         ether_stats_multicast_pkts_high[0x20];
1603
1604         u8         ether_stats_multicast_pkts_low[0x20];
1605
1606         u8         ether_stats_crc_align_errors_high[0x20];
1607
1608         u8         ether_stats_crc_align_errors_low[0x20];
1609
1610         u8         ether_stats_undersize_pkts_high[0x20];
1611
1612         u8         ether_stats_undersize_pkts_low[0x20];
1613
1614         u8         ether_stats_oversize_pkts_high[0x20];
1615
1616         u8         ether_stats_oversize_pkts_low[0x20];
1617
1618         u8         ether_stats_fragments_high[0x20];
1619
1620         u8         ether_stats_fragments_low[0x20];
1621
1622         u8         ether_stats_jabbers_high[0x20];
1623
1624         u8         ether_stats_jabbers_low[0x20];
1625
1626         u8         ether_stats_collisions_high[0x20];
1627
1628         u8         ether_stats_collisions_low[0x20];
1629
1630         u8         ether_stats_pkts64octets_high[0x20];
1631
1632         u8         ether_stats_pkts64octets_low[0x20];
1633
1634         u8         ether_stats_pkts65to127octets_high[0x20];
1635
1636         u8         ether_stats_pkts65to127octets_low[0x20];
1637
1638         u8         ether_stats_pkts128to255octets_high[0x20];
1639
1640         u8         ether_stats_pkts128to255octets_low[0x20];
1641
1642         u8         ether_stats_pkts256to511octets_high[0x20];
1643
1644         u8         ether_stats_pkts256to511octets_low[0x20];
1645
1646         u8         ether_stats_pkts512to1023octets_high[0x20];
1647
1648         u8         ether_stats_pkts512to1023octets_low[0x20];
1649
1650         u8         ether_stats_pkts1024to1518octets_high[0x20];
1651
1652         u8         ether_stats_pkts1024to1518octets_low[0x20];
1653
1654         u8         ether_stats_pkts1519to2047octets_high[0x20];
1655
1656         u8         ether_stats_pkts1519to2047octets_low[0x20];
1657
1658         u8         ether_stats_pkts2048to4095octets_high[0x20];
1659
1660         u8         ether_stats_pkts2048to4095octets_low[0x20];
1661
1662         u8         ether_stats_pkts4096to8191octets_high[0x20];
1663
1664         u8         ether_stats_pkts4096to8191octets_low[0x20];
1665
1666         u8         ether_stats_pkts8192to10239octets_high[0x20];
1667
1668         u8         ether_stats_pkts8192to10239octets_low[0x20];
1669
1670         u8         reserved_at_540[0x280];
1671 };
1672
1673 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1674         u8         if_in_octets_high[0x20];
1675
1676         u8         if_in_octets_low[0x20];
1677
1678         u8         if_in_ucast_pkts_high[0x20];
1679
1680         u8         if_in_ucast_pkts_low[0x20];
1681
1682         u8         if_in_discards_high[0x20];
1683
1684         u8         if_in_discards_low[0x20];
1685
1686         u8         if_in_errors_high[0x20];
1687
1688         u8         if_in_errors_low[0x20];
1689
1690         u8         if_in_unknown_protos_high[0x20];
1691
1692         u8         if_in_unknown_protos_low[0x20];
1693
1694         u8         if_out_octets_high[0x20];
1695
1696         u8         if_out_octets_low[0x20];
1697
1698         u8         if_out_ucast_pkts_high[0x20];
1699
1700         u8         if_out_ucast_pkts_low[0x20];
1701
1702         u8         if_out_discards_high[0x20];
1703
1704         u8         if_out_discards_low[0x20];
1705
1706         u8         if_out_errors_high[0x20];
1707
1708         u8         if_out_errors_low[0x20];
1709
1710         u8         if_in_multicast_pkts_high[0x20];
1711
1712         u8         if_in_multicast_pkts_low[0x20];
1713
1714         u8         if_in_broadcast_pkts_high[0x20];
1715
1716         u8         if_in_broadcast_pkts_low[0x20];
1717
1718         u8         if_out_multicast_pkts_high[0x20];
1719
1720         u8         if_out_multicast_pkts_low[0x20];
1721
1722         u8         if_out_broadcast_pkts_high[0x20];
1723
1724         u8         if_out_broadcast_pkts_low[0x20];
1725
1726         u8         reserved_at_340[0x480];
1727 };
1728
1729 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1730         u8         a_frames_transmitted_ok_high[0x20];
1731
1732         u8         a_frames_transmitted_ok_low[0x20];
1733
1734         u8         a_frames_received_ok_high[0x20];
1735
1736         u8         a_frames_received_ok_low[0x20];
1737
1738         u8         a_frame_check_sequence_errors_high[0x20];
1739
1740         u8         a_frame_check_sequence_errors_low[0x20];
1741
1742         u8         a_alignment_errors_high[0x20];
1743
1744         u8         a_alignment_errors_low[0x20];
1745
1746         u8         a_octets_transmitted_ok_high[0x20];
1747
1748         u8         a_octets_transmitted_ok_low[0x20];
1749
1750         u8         a_octets_received_ok_high[0x20];
1751
1752         u8         a_octets_received_ok_low[0x20];
1753
1754         u8         a_multicast_frames_xmitted_ok_high[0x20];
1755
1756         u8         a_multicast_frames_xmitted_ok_low[0x20];
1757
1758         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1759
1760         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1761
1762         u8         a_multicast_frames_received_ok_high[0x20];
1763
1764         u8         a_multicast_frames_received_ok_low[0x20];
1765
1766         u8         a_broadcast_frames_received_ok_high[0x20];
1767
1768         u8         a_broadcast_frames_received_ok_low[0x20];
1769
1770         u8         a_in_range_length_errors_high[0x20];
1771
1772         u8         a_in_range_length_errors_low[0x20];
1773
1774         u8         a_out_of_range_length_field_high[0x20];
1775
1776         u8         a_out_of_range_length_field_low[0x20];
1777
1778         u8         a_frame_too_long_errors_high[0x20];
1779
1780         u8         a_frame_too_long_errors_low[0x20];
1781
1782         u8         a_symbol_error_during_carrier_high[0x20];
1783
1784         u8         a_symbol_error_during_carrier_low[0x20];
1785
1786         u8         a_mac_control_frames_transmitted_high[0x20];
1787
1788         u8         a_mac_control_frames_transmitted_low[0x20];
1789
1790         u8         a_mac_control_frames_received_high[0x20];
1791
1792         u8         a_mac_control_frames_received_low[0x20];
1793
1794         u8         a_unsupported_opcodes_received_high[0x20];
1795
1796         u8         a_unsupported_opcodes_received_low[0x20];
1797
1798         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1799
1800         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1801
1802         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1803
1804         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1805
1806         u8         reserved_at_4c0[0x300];
1807 };
1808
1809 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1810         u8         life_time_counter_high[0x20];
1811
1812         u8         life_time_counter_low[0x20];
1813
1814         u8         rx_errors[0x20];
1815
1816         u8         tx_errors[0x20];
1817
1818         u8         l0_to_recovery_eieos[0x20];
1819
1820         u8         l0_to_recovery_ts[0x20];
1821
1822         u8         l0_to_recovery_framing[0x20];
1823
1824         u8         l0_to_recovery_retrain[0x20];
1825
1826         u8         crc_error_dllp[0x20];
1827
1828         u8         crc_error_tlp[0x20];
1829
1830         u8         reserved_at_140[0x680];
1831 };
1832
1833 struct mlx5_ifc_cmd_inter_comp_event_bits {
1834         u8         command_completion_vector[0x20];
1835
1836         u8         reserved_at_20[0xc0];
1837 };
1838
1839 struct mlx5_ifc_stall_vl_event_bits {
1840         u8         reserved_at_0[0x18];
1841         u8         port_num[0x1];
1842         u8         reserved_at_19[0x3];
1843         u8         vl[0x4];
1844
1845         u8         reserved_at_20[0xa0];
1846 };
1847
1848 struct mlx5_ifc_db_bf_congestion_event_bits {
1849         u8         event_subtype[0x8];
1850         u8         reserved_at_8[0x8];
1851         u8         congestion_level[0x8];
1852         u8         reserved_at_18[0x8];
1853
1854         u8         reserved_at_20[0xa0];
1855 };
1856
1857 struct mlx5_ifc_gpio_event_bits {
1858         u8         reserved_at_0[0x60];
1859
1860         u8         gpio_event_hi[0x20];
1861
1862         u8         gpio_event_lo[0x20];
1863
1864         u8         reserved_at_a0[0x40];
1865 };
1866
1867 struct mlx5_ifc_port_state_change_event_bits {
1868         u8         reserved_at_0[0x40];
1869
1870         u8         port_num[0x4];
1871         u8         reserved_at_44[0x1c];
1872
1873         u8         reserved_at_60[0x80];
1874 };
1875
1876 struct mlx5_ifc_dropped_packet_logged_bits {
1877         u8         reserved_at_0[0xe0];
1878 };
1879
1880 enum {
1881         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1882         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1883 };
1884
1885 struct mlx5_ifc_cq_error_bits {
1886         u8         reserved_at_0[0x8];
1887         u8         cqn[0x18];
1888
1889         u8         reserved_at_20[0x20];
1890
1891         u8         reserved_at_40[0x18];
1892         u8         syndrome[0x8];
1893
1894         u8         reserved_at_60[0x80];
1895 };
1896
1897 struct mlx5_ifc_rdma_page_fault_event_bits {
1898         u8         bytes_committed[0x20];
1899
1900         u8         r_key[0x20];
1901
1902         u8         reserved_at_40[0x10];
1903         u8         packet_len[0x10];
1904
1905         u8         rdma_op_len[0x20];
1906
1907         u8         rdma_va[0x40];
1908
1909         u8         reserved_at_c0[0x5];
1910         u8         rdma[0x1];
1911         u8         write[0x1];
1912         u8         requestor[0x1];
1913         u8         qp_number[0x18];
1914 };
1915
1916 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1917         u8         bytes_committed[0x20];
1918
1919         u8         reserved_at_20[0x10];
1920         u8         wqe_index[0x10];
1921
1922         u8         reserved_at_40[0x10];
1923         u8         len[0x10];
1924
1925         u8         reserved_at_60[0x60];
1926
1927         u8         reserved_at_c0[0x5];
1928         u8         rdma[0x1];
1929         u8         write_read[0x1];
1930         u8         requestor[0x1];
1931         u8         qpn[0x18];
1932 };
1933
1934 struct mlx5_ifc_qp_events_bits {
1935         u8         reserved_at_0[0xa0];
1936
1937         u8         type[0x8];
1938         u8         reserved_at_a8[0x18];
1939
1940         u8         reserved_at_c0[0x8];
1941         u8         qpn_rqn_sqn[0x18];
1942 };
1943
1944 struct mlx5_ifc_dct_events_bits {
1945         u8         reserved_at_0[0xc0];
1946
1947         u8         reserved_at_c0[0x8];
1948         u8         dct_number[0x18];
1949 };
1950
1951 struct mlx5_ifc_comp_event_bits {
1952         u8         reserved_at_0[0xc0];
1953
1954         u8         reserved_at_c0[0x8];
1955         u8         cq_number[0x18];
1956 };
1957
1958 enum {
1959         MLX5_QPC_STATE_RST        = 0x0,
1960         MLX5_QPC_STATE_INIT       = 0x1,
1961         MLX5_QPC_STATE_RTR        = 0x2,
1962         MLX5_QPC_STATE_RTS        = 0x3,
1963         MLX5_QPC_STATE_SQER       = 0x4,
1964         MLX5_QPC_STATE_ERR        = 0x6,
1965         MLX5_QPC_STATE_SQD        = 0x7,
1966         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1967 };
1968
1969 enum {
1970         MLX5_QPC_ST_RC            = 0x0,
1971         MLX5_QPC_ST_UC            = 0x1,
1972         MLX5_QPC_ST_UD            = 0x2,
1973         MLX5_QPC_ST_XRC           = 0x3,
1974         MLX5_QPC_ST_DCI           = 0x5,
1975         MLX5_QPC_ST_QP0           = 0x7,
1976         MLX5_QPC_ST_QP1           = 0x8,
1977         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1978         MLX5_QPC_ST_REG_UMR       = 0xc,
1979 };
1980
1981 enum {
1982         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1983         MLX5_QPC_PM_STATE_REARM     = 0x1,
1984         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1985         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1986 };
1987
1988 enum {
1989         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1990         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1991 };
1992
1993 enum {
1994         MLX5_QPC_MTU_256_BYTES        = 0x1,
1995         MLX5_QPC_MTU_512_BYTES        = 0x2,
1996         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1997         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1998         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1999         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2000 };
2001
2002 enum {
2003         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2004         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2005         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2006         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2007         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2008         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2009         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2010         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2011 };
2012
2013 enum {
2014         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2015         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2016         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2017 };
2018
2019 enum {
2020         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2021         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2022         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2023 };
2024
2025 struct mlx5_ifc_qpc_bits {
2026         u8         state[0x4];
2027         u8         lag_tx_port_affinity[0x4];
2028         u8         st[0x8];
2029         u8         reserved_at_10[0x3];
2030         u8         pm_state[0x2];
2031         u8         reserved_at_15[0x7];
2032         u8         end_padding_mode[0x2];
2033         u8         reserved_at_1e[0x2];
2034
2035         u8         wq_signature[0x1];
2036         u8         block_lb_mc[0x1];
2037         u8         atomic_like_write_en[0x1];
2038         u8         latency_sensitive[0x1];
2039         u8         reserved_at_24[0x1];
2040         u8         drain_sigerr[0x1];
2041         u8         reserved_at_26[0x2];
2042         u8         pd[0x18];
2043
2044         u8         mtu[0x3];
2045         u8         log_msg_max[0x5];
2046         u8         reserved_at_48[0x1];
2047         u8         log_rq_size[0x4];
2048         u8         log_rq_stride[0x3];
2049         u8         no_sq[0x1];
2050         u8         log_sq_size[0x4];
2051         u8         reserved_at_55[0x6];
2052         u8         rlky[0x1];
2053         u8         ulp_stateless_offload_mode[0x4];
2054
2055         u8         counter_set_id[0x8];
2056         u8         uar_page[0x18];
2057
2058         u8         reserved_at_80[0x8];
2059         u8         user_index[0x18];
2060
2061         u8         reserved_at_a0[0x3];
2062         u8         log_page_size[0x5];
2063         u8         remote_qpn[0x18];
2064
2065         struct mlx5_ifc_ads_bits primary_address_path;
2066
2067         struct mlx5_ifc_ads_bits secondary_address_path;
2068
2069         u8         log_ack_req_freq[0x4];
2070         u8         reserved_at_384[0x4];
2071         u8         log_sra_max[0x3];
2072         u8         reserved_at_38b[0x2];
2073         u8         retry_count[0x3];
2074         u8         rnr_retry[0x3];
2075         u8         reserved_at_393[0x1];
2076         u8         fre[0x1];
2077         u8         cur_rnr_retry[0x3];
2078         u8         cur_retry_count[0x3];
2079         u8         reserved_at_39b[0x5];
2080
2081         u8         reserved_at_3a0[0x20];
2082
2083         u8         reserved_at_3c0[0x8];
2084         u8         next_send_psn[0x18];
2085
2086         u8         reserved_at_3e0[0x8];
2087         u8         cqn_snd[0x18];
2088
2089         u8         reserved_at_400[0x8];
2090         u8         deth_sqpn[0x18];
2091
2092         u8         reserved_at_420[0x20];
2093
2094         u8         reserved_at_440[0x8];
2095         u8         last_acked_psn[0x18];
2096
2097         u8         reserved_at_460[0x8];
2098         u8         ssn[0x18];
2099
2100         u8         reserved_at_480[0x8];
2101         u8         log_rra_max[0x3];
2102         u8         reserved_at_48b[0x1];
2103         u8         atomic_mode[0x4];
2104         u8         rre[0x1];
2105         u8         rwe[0x1];
2106         u8         rae[0x1];
2107         u8         reserved_at_493[0x1];
2108         u8         page_offset[0x6];
2109         u8         reserved_at_49a[0x3];
2110         u8         cd_slave_receive[0x1];
2111         u8         cd_slave_send[0x1];
2112         u8         cd_master[0x1];
2113
2114         u8         reserved_at_4a0[0x3];
2115         u8         min_rnr_nak[0x5];
2116         u8         next_rcv_psn[0x18];
2117
2118         u8         reserved_at_4c0[0x8];
2119         u8         xrcd[0x18];
2120
2121         u8         reserved_at_4e0[0x8];
2122         u8         cqn_rcv[0x18];
2123
2124         u8         dbr_addr[0x40];
2125
2126         u8         q_key[0x20];
2127
2128         u8         reserved_at_560[0x5];
2129         u8         rq_type[0x3];
2130         u8         srqn_rmpn_xrqn[0x18];
2131
2132         u8         reserved_at_580[0x8];
2133         u8         rmsn[0x18];
2134
2135         u8         hw_sq_wqebb_counter[0x10];
2136         u8         sw_sq_wqebb_counter[0x10];
2137
2138         u8         hw_rq_counter[0x20];
2139
2140         u8         sw_rq_counter[0x20];
2141
2142         u8         reserved_at_600[0x20];
2143
2144         u8         reserved_at_620[0xf];
2145         u8         cgs[0x1];
2146         u8         cs_req[0x8];
2147         u8         cs_res[0x8];
2148
2149         u8         dc_access_key[0x40];
2150
2151         u8         reserved_at_680[0xc0];
2152 };
2153
2154 struct mlx5_ifc_roce_addr_layout_bits {
2155         u8         source_l3_address[16][0x8];
2156
2157         u8         reserved_at_80[0x3];
2158         u8         vlan_valid[0x1];
2159         u8         vlan_id[0xc];
2160         u8         source_mac_47_32[0x10];
2161
2162         u8         source_mac_31_0[0x20];
2163
2164         u8         reserved_at_c0[0x14];
2165         u8         roce_l3_type[0x4];
2166         u8         roce_version[0x8];
2167
2168         u8         reserved_at_e0[0x20];
2169 };
2170
2171 union mlx5_ifc_hca_cap_union_bits {
2172         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2173         struct mlx5_ifc_odp_cap_bits odp_cap;
2174         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2175         struct mlx5_ifc_roce_cap_bits roce_cap;
2176         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2177         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2178         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2179         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2180         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2181         struct mlx5_ifc_qos_cap_bits qos_cap;
2182         u8         reserved_at_0[0x8000];
2183 };
2184
2185 enum {
2186         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2187         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2188         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2189         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2190         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2191         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2192 };
2193
2194 struct mlx5_ifc_flow_context_bits {
2195         u8         reserved_at_0[0x20];
2196
2197         u8         group_id[0x20];
2198
2199         u8         reserved_at_40[0x8];
2200         u8         flow_tag[0x18];
2201
2202         u8         reserved_at_60[0x10];
2203         u8         action[0x10];
2204
2205         u8         reserved_at_80[0x8];
2206         u8         destination_list_size[0x18];
2207
2208         u8         reserved_at_a0[0x8];
2209         u8         flow_counter_list_size[0x18];
2210
2211         u8         encap_id[0x20];
2212
2213         u8         reserved_at_e0[0x120];
2214
2215         struct mlx5_ifc_fte_match_param_bits match_value;
2216
2217         u8         reserved_at_1200[0x600];
2218
2219         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2220 };
2221
2222 enum {
2223         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2224         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2225 };
2226
2227 struct mlx5_ifc_xrc_srqc_bits {
2228         u8         state[0x4];
2229         u8         log_xrc_srq_size[0x4];
2230         u8         reserved_at_8[0x18];
2231
2232         u8         wq_signature[0x1];
2233         u8         cont_srq[0x1];
2234         u8         reserved_at_22[0x1];
2235         u8         rlky[0x1];
2236         u8         basic_cyclic_rcv_wqe[0x1];
2237         u8         log_rq_stride[0x3];
2238         u8         xrcd[0x18];
2239
2240         u8         page_offset[0x6];
2241         u8         reserved_at_46[0x2];
2242         u8         cqn[0x18];
2243
2244         u8         reserved_at_60[0x20];
2245
2246         u8         user_index_equal_xrc_srqn[0x1];
2247         u8         reserved_at_81[0x1];
2248         u8         log_page_size[0x6];
2249         u8         user_index[0x18];
2250
2251         u8         reserved_at_a0[0x20];
2252
2253         u8         reserved_at_c0[0x8];
2254         u8         pd[0x18];
2255
2256         u8         lwm[0x10];
2257         u8         wqe_cnt[0x10];
2258
2259         u8         reserved_at_100[0x40];
2260
2261         u8         db_record_addr_h[0x20];
2262
2263         u8         db_record_addr_l[0x1e];
2264         u8         reserved_at_17e[0x2];
2265
2266         u8         reserved_at_180[0x80];
2267 };
2268
2269 struct mlx5_ifc_traffic_counter_bits {
2270         u8         packets[0x40];
2271
2272         u8         octets[0x40];
2273 };
2274
2275 struct mlx5_ifc_tisc_bits {
2276         u8         strict_lag_tx_port_affinity[0x1];
2277         u8         reserved_at_1[0x3];
2278         u8         lag_tx_port_affinity[0x04];
2279
2280         u8         reserved_at_8[0x4];
2281         u8         prio[0x4];
2282         u8         reserved_at_10[0x10];
2283
2284         u8         reserved_at_20[0x100];
2285
2286         u8         reserved_at_120[0x8];
2287         u8         transport_domain[0x18];
2288
2289         u8         reserved_at_140[0x3c0];
2290 };
2291
2292 enum {
2293         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2294         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2295 };
2296
2297 enum {
2298         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2299         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2300 };
2301
2302 enum {
2303         MLX5_RX_HASH_FN_NONE           = 0x0,
2304         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2305         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2306 };
2307
2308 enum {
2309         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2310         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2311 };
2312
2313 struct mlx5_ifc_tirc_bits {
2314         u8         reserved_at_0[0x20];
2315
2316         u8         disp_type[0x4];
2317         u8         reserved_at_24[0x1c];
2318
2319         u8         reserved_at_40[0x40];
2320
2321         u8         reserved_at_80[0x4];
2322         u8         lro_timeout_period_usecs[0x10];
2323         u8         lro_enable_mask[0x4];
2324         u8         lro_max_ip_payload_size[0x8];
2325
2326         u8         reserved_at_a0[0x40];
2327
2328         u8         reserved_at_e0[0x8];
2329         u8         inline_rqn[0x18];
2330
2331         u8         rx_hash_symmetric[0x1];
2332         u8         reserved_at_101[0x1];
2333         u8         tunneled_offload_en[0x1];
2334         u8         reserved_at_103[0x5];
2335         u8         indirect_table[0x18];
2336
2337         u8         rx_hash_fn[0x4];
2338         u8         reserved_at_124[0x2];
2339         u8         self_lb_block[0x2];
2340         u8         transport_domain[0x18];
2341
2342         u8         rx_hash_toeplitz_key[10][0x20];
2343
2344         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2345
2346         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2347
2348         u8         reserved_at_2c0[0x4c0];
2349 };
2350
2351 enum {
2352         MLX5_SRQC_STATE_GOOD   = 0x0,
2353         MLX5_SRQC_STATE_ERROR  = 0x1,
2354 };
2355
2356 struct mlx5_ifc_srqc_bits {
2357         u8         state[0x4];
2358         u8         log_srq_size[0x4];
2359         u8         reserved_at_8[0x18];
2360
2361         u8         wq_signature[0x1];
2362         u8         cont_srq[0x1];
2363         u8         reserved_at_22[0x1];
2364         u8         rlky[0x1];
2365         u8         reserved_at_24[0x1];
2366         u8         log_rq_stride[0x3];
2367         u8         xrcd[0x18];
2368
2369         u8         page_offset[0x6];
2370         u8         reserved_at_46[0x2];
2371         u8         cqn[0x18];
2372
2373         u8         reserved_at_60[0x20];
2374
2375         u8         reserved_at_80[0x2];
2376         u8         log_page_size[0x6];
2377         u8         reserved_at_88[0x18];
2378
2379         u8         reserved_at_a0[0x20];
2380
2381         u8         reserved_at_c0[0x8];
2382         u8         pd[0x18];
2383
2384         u8         lwm[0x10];
2385         u8         wqe_cnt[0x10];
2386
2387         u8         reserved_at_100[0x40];
2388
2389         u8         dbr_addr[0x40];
2390
2391         u8         reserved_at_180[0x80];
2392 };
2393
2394 enum {
2395         MLX5_SQC_STATE_RST  = 0x0,
2396         MLX5_SQC_STATE_RDY  = 0x1,
2397         MLX5_SQC_STATE_ERR  = 0x3,
2398 };
2399
2400 struct mlx5_ifc_sqc_bits {
2401         u8         rlky[0x1];
2402         u8         cd_master[0x1];
2403         u8         fre[0x1];
2404         u8         flush_in_error_en[0x1];
2405         u8         reserved_at_4[0x1];
2406         u8         min_wqe_inline_mode[0x3];
2407         u8         state[0x4];
2408         u8         reg_umr[0x1];
2409         u8         reserved_at_d[0x13];
2410
2411         u8         reserved_at_20[0x8];
2412         u8         user_index[0x18];
2413
2414         u8         reserved_at_40[0x8];
2415         u8         cqn[0x18];
2416
2417         u8         reserved_at_60[0x90];
2418
2419         u8         packet_pacing_rate_limit_index[0x10];
2420         u8         tis_lst_sz[0x10];
2421         u8         reserved_at_110[0x10];
2422
2423         u8         reserved_at_120[0x40];
2424
2425         u8         reserved_at_160[0x8];
2426         u8         tis_num_0[0x18];
2427
2428         struct mlx5_ifc_wq_bits wq;
2429 };
2430
2431 enum {
2432         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2433         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2434         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2435         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2436 };
2437
2438 struct mlx5_ifc_scheduling_context_bits {
2439         u8         element_type[0x8];
2440         u8         reserved_at_8[0x18];
2441
2442         u8         element_attributes[0x20];
2443
2444         u8         parent_element_id[0x20];
2445
2446         u8         reserved_at_60[0x40];
2447
2448         u8         bw_share[0x20];
2449
2450         u8         max_average_bw[0x20];
2451
2452         u8         reserved_at_e0[0x120];
2453 };
2454
2455 struct mlx5_ifc_rqtc_bits {
2456         u8         reserved_at_0[0xa0];
2457
2458         u8         reserved_at_a0[0x10];
2459         u8         rqt_max_size[0x10];
2460
2461         u8         reserved_at_c0[0x10];
2462         u8         rqt_actual_size[0x10];
2463
2464         u8         reserved_at_e0[0x6a0];
2465
2466         struct mlx5_ifc_rq_num_bits rq_num[0];
2467 };
2468
2469 enum {
2470         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2471         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2472 };
2473
2474 enum {
2475         MLX5_RQC_STATE_RST  = 0x0,
2476         MLX5_RQC_STATE_RDY  = 0x1,
2477         MLX5_RQC_STATE_ERR  = 0x3,
2478 };
2479
2480 struct mlx5_ifc_rqc_bits {
2481         u8         rlky[0x1];
2482         u8         reserved_at_1[0x1];
2483         u8         scatter_fcs[0x1];
2484         u8         vsd[0x1];
2485         u8         mem_rq_type[0x4];
2486         u8         state[0x4];
2487         u8         reserved_at_c[0x1];
2488         u8         flush_in_error_en[0x1];
2489         u8         reserved_at_e[0x12];
2490
2491         u8         reserved_at_20[0x8];
2492         u8         user_index[0x18];
2493
2494         u8         reserved_at_40[0x8];
2495         u8         cqn[0x18];
2496
2497         u8         counter_set_id[0x8];
2498         u8         reserved_at_68[0x18];
2499
2500         u8         reserved_at_80[0x8];
2501         u8         rmpn[0x18];
2502
2503         u8         reserved_at_a0[0xe0];
2504
2505         struct mlx5_ifc_wq_bits wq;
2506 };
2507
2508 enum {
2509         MLX5_RMPC_STATE_RDY  = 0x1,
2510         MLX5_RMPC_STATE_ERR  = 0x3,
2511 };
2512
2513 struct mlx5_ifc_rmpc_bits {
2514         u8         reserved_at_0[0x8];
2515         u8         state[0x4];
2516         u8         reserved_at_c[0x14];
2517
2518         u8         basic_cyclic_rcv_wqe[0x1];
2519         u8         reserved_at_21[0x1f];
2520
2521         u8         reserved_at_40[0x140];
2522
2523         struct mlx5_ifc_wq_bits wq;
2524 };
2525
2526 struct mlx5_ifc_nic_vport_context_bits {
2527         u8         reserved_at_0[0x5];
2528         u8         min_wqe_inline_mode[0x3];
2529         u8         reserved_at_8[0x17];
2530         u8         roce_en[0x1];
2531
2532         u8         arm_change_event[0x1];
2533         u8         reserved_at_21[0x1a];
2534         u8         event_on_mtu[0x1];
2535         u8         event_on_promisc_change[0x1];
2536         u8         event_on_vlan_change[0x1];
2537         u8         event_on_mc_address_change[0x1];
2538         u8         event_on_uc_address_change[0x1];
2539
2540         u8         reserved_at_40[0xf0];
2541
2542         u8         mtu[0x10];
2543
2544         u8         system_image_guid[0x40];
2545         u8         port_guid[0x40];
2546         u8         node_guid[0x40];
2547
2548         u8         reserved_at_200[0x140];
2549         u8         qkey_violation_counter[0x10];
2550         u8         reserved_at_350[0x430];
2551
2552         u8         promisc_uc[0x1];
2553         u8         promisc_mc[0x1];
2554         u8         promisc_all[0x1];
2555         u8         reserved_at_783[0x2];
2556         u8         allowed_list_type[0x3];
2557         u8         reserved_at_788[0xc];
2558         u8         allowed_list_size[0xc];
2559
2560         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2561
2562         u8         reserved_at_7e0[0x20];
2563
2564         u8         current_uc_mac_address[0][0x40];
2565 };
2566
2567 enum {
2568         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2569         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2570         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2571         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2572 };
2573
2574 struct mlx5_ifc_mkc_bits {
2575         u8         reserved_at_0[0x1];
2576         u8         free[0x1];
2577         u8         reserved_at_2[0xd];
2578         u8         small_fence_on_rdma_read_response[0x1];
2579         u8         umr_en[0x1];
2580         u8         a[0x1];
2581         u8         rw[0x1];
2582         u8         rr[0x1];
2583         u8         lw[0x1];
2584         u8         lr[0x1];
2585         u8         access_mode[0x2];
2586         u8         reserved_at_18[0x8];
2587
2588         u8         qpn[0x18];
2589         u8         mkey_7_0[0x8];
2590
2591         u8         reserved_at_40[0x20];
2592
2593         u8         length64[0x1];
2594         u8         bsf_en[0x1];
2595         u8         sync_umr[0x1];
2596         u8         reserved_at_63[0x2];
2597         u8         expected_sigerr_count[0x1];
2598         u8         reserved_at_66[0x1];
2599         u8         en_rinval[0x1];
2600         u8         pd[0x18];
2601
2602         u8         start_addr[0x40];
2603
2604         u8         len[0x40];
2605
2606         u8         bsf_octword_size[0x20];
2607
2608         u8         reserved_at_120[0x80];
2609
2610         u8         translations_octword_size[0x20];
2611
2612         u8         reserved_at_1c0[0x1b];
2613         u8         log_page_size[0x5];
2614
2615         u8         reserved_at_1e0[0x20];
2616 };
2617
2618 struct mlx5_ifc_pkey_bits {
2619         u8         reserved_at_0[0x10];
2620         u8         pkey[0x10];
2621 };
2622
2623 struct mlx5_ifc_array128_auto_bits {
2624         u8         array128_auto[16][0x8];
2625 };
2626
2627 struct mlx5_ifc_hca_vport_context_bits {
2628         u8         field_select[0x20];
2629
2630         u8         reserved_at_20[0xe0];
2631
2632         u8         sm_virt_aware[0x1];
2633         u8         has_smi[0x1];
2634         u8         has_raw[0x1];
2635         u8         grh_required[0x1];
2636         u8         reserved_at_104[0xc];
2637         u8         port_physical_state[0x4];
2638         u8         vport_state_policy[0x4];
2639         u8         port_state[0x4];
2640         u8         vport_state[0x4];
2641
2642         u8         reserved_at_120[0x20];
2643
2644         u8         system_image_guid[0x40];
2645
2646         u8         port_guid[0x40];
2647
2648         u8         node_guid[0x40];
2649
2650         u8         cap_mask1[0x20];
2651
2652         u8         cap_mask1_field_select[0x20];
2653
2654         u8         cap_mask2[0x20];
2655
2656         u8         cap_mask2_field_select[0x20];
2657
2658         u8         reserved_at_280[0x80];
2659
2660         u8         lid[0x10];
2661         u8         reserved_at_310[0x4];
2662         u8         init_type_reply[0x4];
2663         u8         lmc[0x3];
2664         u8         subnet_timeout[0x5];
2665
2666         u8         sm_lid[0x10];
2667         u8         sm_sl[0x4];
2668         u8         reserved_at_334[0xc];
2669
2670         u8         qkey_violation_counter[0x10];
2671         u8         pkey_violation_counter[0x10];
2672
2673         u8         reserved_at_360[0xca0];
2674 };
2675
2676 struct mlx5_ifc_esw_vport_context_bits {
2677         u8         reserved_at_0[0x3];
2678         u8         vport_svlan_strip[0x1];
2679         u8         vport_cvlan_strip[0x1];
2680         u8         vport_svlan_insert[0x1];
2681         u8         vport_cvlan_insert[0x2];
2682         u8         reserved_at_8[0x18];
2683
2684         u8         reserved_at_20[0x20];
2685
2686         u8         svlan_cfi[0x1];
2687         u8         svlan_pcp[0x3];
2688         u8         svlan_id[0xc];
2689         u8         cvlan_cfi[0x1];
2690         u8         cvlan_pcp[0x3];
2691         u8         cvlan_id[0xc];
2692
2693         u8         reserved_at_60[0x7a0];
2694 };
2695
2696 enum {
2697         MLX5_EQC_STATUS_OK                = 0x0,
2698         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2699 };
2700
2701 enum {
2702         MLX5_EQC_ST_ARMED  = 0x9,
2703         MLX5_EQC_ST_FIRED  = 0xa,
2704 };
2705
2706 struct mlx5_ifc_eqc_bits {
2707         u8         status[0x4];
2708         u8         reserved_at_4[0x9];
2709         u8         ec[0x1];
2710         u8         oi[0x1];
2711         u8         reserved_at_f[0x5];
2712         u8         st[0x4];
2713         u8         reserved_at_18[0x8];
2714
2715         u8         reserved_at_20[0x20];
2716
2717         u8         reserved_at_40[0x14];
2718         u8         page_offset[0x6];
2719         u8         reserved_at_5a[0x6];
2720
2721         u8         reserved_at_60[0x3];
2722         u8         log_eq_size[0x5];
2723         u8         uar_page[0x18];
2724
2725         u8         reserved_at_80[0x20];
2726
2727         u8         reserved_at_a0[0x18];
2728         u8         intr[0x8];
2729
2730         u8         reserved_at_c0[0x3];
2731         u8         log_page_size[0x5];
2732         u8         reserved_at_c8[0x18];
2733
2734         u8         reserved_at_e0[0x60];
2735
2736         u8         reserved_at_140[0x8];
2737         u8         consumer_counter[0x18];
2738
2739         u8         reserved_at_160[0x8];
2740         u8         producer_counter[0x18];
2741
2742         u8         reserved_at_180[0x80];
2743 };
2744
2745 enum {
2746         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2747         MLX5_DCTC_STATE_DRAINING  = 0x1,
2748         MLX5_DCTC_STATE_DRAINED   = 0x2,
2749 };
2750
2751 enum {
2752         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2753         MLX5_DCTC_CS_RES_NA         = 0x1,
2754         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2755 };
2756
2757 enum {
2758         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2759         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2760         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2761         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2762         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2763 };
2764
2765 struct mlx5_ifc_dctc_bits {
2766         u8         reserved_at_0[0x4];
2767         u8         state[0x4];
2768         u8         reserved_at_8[0x18];
2769
2770         u8         reserved_at_20[0x8];
2771         u8         user_index[0x18];
2772
2773         u8         reserved_at_40[0x8];
2774         u8         cqn[0x18];
2775
2776         u8         counter_set_id[0x8];
2777         u8         atomic_mode[0x4];
2778         u8         rre[0x1];
2779         u8         rwe[0x1];
2780         u8         rae[0x1];
2781         u8         atomic_like_write_en[0x1];
2782         u8         latency_sensitive[0x1];
2783         u8         rlky[0x1];
2784         u8         free_ar[0x1];
2785         u8         reserved_at_73[0xd];
2786
2787         u8         reserved_at_80[0x8];
2788         u8         cs_res[0x8];
2789         u8         reserved_at_90[0x3];
2790         u8         min_rnr_nak[0x5];
2791         u8         reserved_at_98[0x8];
2792
2793         u8         reserved_at_a0[0x8];
2794         u8         srqn_xrqn[0x18];
2795
2796         u8         reserved_at_c0[0x8];
2797         u8         pd[0x18];
2798
2799         u8         tclass[0x8];
2800         u8         reserved_at_e8[0x4];
2801         u8         flow_label[0x14];
2802
2803         u8         dc_access_key[0x40];
2804
2805         u8         reserved_at_140[0x5];
2806         u8         mtu[0x3];
2807         u8         port[0x8];
2808         u8         pkey_index[0x10];
2809
2810         u8         reserved_at_160[0x8];
2811         u8         my_addr_index[0x8];
2812         u8         reserved_at_170[0x8];
2813         u8         hop_limit[0x8];
2814
2815         u8         dc_access_key_violation_count[0x20];
2816
2817         u8         reserved_at_1a0[0x14];
2818         u8         dei_cfi[0x1];
2819         u8         eth_prio[0x3];
2820         u8         ecn[0x2];
2821         u8         dscp[0x6];
2822
2823         u8         reserved_at_1c0[0x40];
2824 };
2825
2826 enum {
2827         MLX5_CQC_STATUS_OK             = 0x0,
2828         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2829         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2830 };
2831
2832 enum {
2833         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2834         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2835 };
2836
2837 enum {
2838         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2839         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2840         MLX5_CQC_ST_FIRED                                 = 0xa,
2841 };
2842
2843 enum {
2844         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2845         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2846         MLX5_CQ_PERIOD_NUM_MODES
2847 };
2848
2849 struct mlx5_ifc_cqc_bits {
2850         u8         status[0x4];
2851         u8         reserved_at_4[0x4];
2852         u8         cqe_sz[0x3];
2853         u8         cc[0x1];
2854         u8         reserved_at_c[0x1];
2855         u8         scqe_break_moderation_en[0x1];
2856         u8         oi[0x1];
2857         u8         cq_period_mode[0x2];
2858         u8         cqe_comp_en[0x1];
2859         u8         mini_cqe_res_format[0x2];
2860         u8         st[0x4];
2861         u8         reserved_at_18[0x8];
2862
2863         u8         reserved_at_20[0x20];
2864
2865         u8         reserved_at_40[0x14];
2866         u8         page_offset[0x6];
2867         u8         reserved_at_5a[0x6];
2868
2869         u8         reserved_at_60[0x3];
2870         u8         log_cq_size[0x5];
2871         u8         uar_page[0x18];
2872
2873         u8         reserved_at_80[0x4];
2874         u8         cq_period[0xc];
2875         u8         cq_max_count[0x10];
2876
2877         u8         reserved_at_a0[0x18];
2878         u8         c_eqn[0x8];
2879
2880         u8         reserved_at_c0[0x3];
2881         u8         log_page_size[0x5];
2882         u8         reserved_at_c8[0x18];
2883
2884         u8         reserved_at_e0[0x20];
2885
2886         u8         reserved_at_100[0x8];
2887         u8         last_notified_index[0x18];
2888
2889         u8         reserved_at_120[0x8];
2890         u8         last_solicit_index[0x18];
2891
2892         u8         reserved_at_140[0x8];
2893         u8         consumer_counter[0x18];
2894
2895         u8         reserved_at_160[0x8];
2896         u8         producer_counter[0x18];
2897
2898         u8         reserved_at_180[0x40];
2899
2900         u8         dbr_addr[0x40];
2901 };
2902
2903 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2904         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2905         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2906         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2907         u8         reserved_at_0[0x800];
2908 };
2909
2910 struct mlx5_ifc_query_adapter_param_block_bits {
2911         u8         reserved_at_0[0xc0];
2912
2913         u8         reserved_at_c0[0x8];
2914         u8         ieee_vendor_id[0x18];
2915
2916         u8         reserved_at_e0[0x10];
2917         u8         vsd_vendor_id[0x10];
2918
2919         u8         vsd[208][0x8];
2920
2921         u8         vsd_contd_psid[16][0x8];
2922 };
2923
2924 enum {
2925         MLX5_XRQC_STATE_GOOD   = 0x0,
2926         MLX5_XRQC_STATE_ERROR  = 0x1,
2927 };
2928
2929 enum {
2930         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2931         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2932 };
2933
2934 enum {
2935         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2936 };
2937
2938 struct mlx5_ifc_tag_matching_topology_context_bits {
2939         u8         log_matching_list_sz[0x4];
2940         u8         reserved_at_4[0xc];
2941         u8         append_next_index[0x10];
2942
2943         u8         sw_phase_cnt[0x10];
2944         u8         hw_phase_cnt[0x10];
2945
2946         u8         reserved_at_40[0x40];
2947 };
2948
2949 struct mlx5_ifc_xrqc_bits {
2950         u8         state[0x4];
2951         u8         rlkey[0x1];
2952         u8         reserved_at_5[0xf];
2953         u8         topology[0x4];
2954         u8         reserved_at_18[0x4];
2955         u8         offload[0x4];
2956
2957         u8         reserved_at_20[0x8];
2958         u8         user_index[0x18];
2959
2960         u8         reserved_at_40[0x8];
2961         u8         cqn[0x18];
2962
2963         u8         reserved_at_60[0xa0];
2964
2965         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2966
2967         u8         reserved_at_180[0x880];
2968
2969         struct mlx5_ifc_wq_bits wq;
2970 };
2971
2972 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2973         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2974         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2975         u8         reserved_at_0[0x20];
2976 };
2977
2978 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2979         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2980         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2981         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2982         u8         reserved_at_0[0x20];
2983 };
2984
2985 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2986         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2987         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2988         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2989         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2990         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2991         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2992         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2993         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2994         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2995         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
2996         u8         reserved_at_0[0x7c0];
2997 };
2998
2999 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3000         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3001         u8         reserved_at_0[0x7c0];
3002 };
3003
3004 union mlx5_ifc_event_auto_bits {
3005         struct mlx5_ifc_comp_event_bits comp_event;
3006         struct mlx5_ifc_dct_events_bits dct_events;
3007         struct mlx5_ifc_qp_events_bits qp_events;
3008         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3009         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3010         struct mlx5_ifc_cq_error_bits cq_error;
3011         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3012         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3013         struct mlx5_ifc_gpio_event_bits gpio_event;
3014         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3015         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3016         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3017         u8         reserved_at_0[0xe0];
3018 };
3019
3020 struct mlx5_ifc_health_buffer_bits {
3021         u8         reserved_at_0[0x100];
3022
3023         u8         assert_existptr[0x20];
3024
3025         u8         assert_callra[0x20];
3026
3027         u8         reserved_at_140[0x40];
3028
3029         u8         fw_version[0x20];
3030
3031         u8         hw_id[0x20];
3032
3033         u8         reserved_at_1c0[0x20];
3034
3035         u8         irisc_index[0x8];
3036         u8         synd[0x8];
3037         u8         ext_synd[0x10];
3038 };
3039
3040 struct mlx5_ifc_register_loopback_control_bits {
3041         u8         no_lb[0x1];
3042         u8         reserved_at_1[0x7];
3043         u8         port[0x8];
3044         u8         reserved_at_10[0x10];
3045
3046         u8         reserved_at_20[0x60];
3047 };
3048
3049 struct mlx5_ifc_vport_tc_element_bits {
3050         u8         traffic_class[0x4];
3051         u8         reserved_at_4[0xc];
3052         u8         vport_number[0x10];
3053 };
3054
3055 struct mlx5_ifc_vport_element_bits {
3056         u8         reserved_at_0[0x10];
3057         u8         vport_number[0x10];
3058 };
3059
3060 enum {
3061         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3062         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3063         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3064 };
3065
3066 struct mlx5_ifc_tsar_element_bits {
3067         u8         reserved_at_0[0x8];
3068         u8         tsar_type[0x8];
3069         u8         reserved_at_10[0x10];
3070 };
3071
3072 struct mlx5_ifc_teardown_hca_out_bits {
3073         u8         status[0x8];
3074         u8         reserved_at_8[0x18];
3075
3076         u8         syndrome[0x20];
3077
3078         u8         reserved_at_40[0x40];
3079 };
3080
3081 enum {
3082         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3083         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
3084 };
3085
3086 struct mlx5_ifc_teardown_hca_in_bits {
3087         u8         opcode[0x10];
3088         u8         reserved_at_10[0x10];
3089
3090         u8         reserved_at_20[0x10];
3091         u8         op_mod[0x10];
3092
3093         u8         reserved_at_40[0x10];
3094         u8         profile[0x10];
3095
3096         u8         reserved_at_60[0x20];
3097 };
3098
3099 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3100         u8         status[0x8];
3101         u8         reserved_at_8[0x18];
3102
3103         u8         syndrome[0x20];
3104
3105         u8         reserved_at_40[0x40];
3106 };
3107
3108 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3109         u8         opcode[0x10];
3110         u8         reserved_at_10[0x10];
3111
3112         u8         reserved_at_20[0x10];
3113         u8         op_mod[0x10];
3114
3115         u8         reserved_at_40[0x8];
3116         u8         qpn[0x18];
3117
3118         u8         reserved_at_60[0x20];
3119
3120         u8         opt_param_mask[0x20];
3121
3122         u8         reserved_at_a0[0x20];
3123
3124         struct mlx5_ifc_qpc_bits qpc;
3125
3126         u8         reserved_at_800[0x80];
3127 };
3128
3129 struct mlx5_ifc_sqd2rts_qp_out_bits {
3130         u8         status[0x8];
3131         u8         reserved_at_8[0x18];
3132
3133         u8         syndrome[0x20];
3134
3135         u8         reserved_at_40[0x40];
3136 };
3137
3138 struct mlx5_ifc_sqd2rts_qp_in_bits {
3139         u8         opcode[0x10];
3140         u8         reserved_at_10[0x10];
3141
3142         u8         reserved_at_20[0x10];
3143         u8         op_mod[0x10];
3144
3145         u8         reserved_at_40[0x8];
3146         u8         qpn[0x18];
3147
3148         u8         reserved_at_60[0x20];
3149
3150         u8         opt_param_mask[0x20];
3151
3152         u8         reserved_at_a0[0x20];
3153
3154         struct mlx5_ifc_qpc_bits qpc;
3155
3156         u8         reserved_at_800[0x80];
3157 };
3158
3159 struct mlx5_ifc_set_roce_address_out_bits {
3160         u8         status[0x8];
3161         u8         reserved_at_8[0x18];
3162
3163         u8         syndrome[0x20];
3164
3165         u8         reserved_at_40[0x40];
3166 };
3167
3168 struct mlx5_ifc_set_roce_address_in_bits {
3169         u8         opcode[0x10];
3170         u8         reserved_at_10[0x10];
3171
3172         u8         reserved_at_20[0x10];
3173         u8         op_mod[0x10];
3174
3175         u8         roce_address_index[0x10];
3176         u8         reserved_at_50[0x10];
3177
3178         u8         reserved_at_60[0x20];
3179
3180         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3181 };
3182
3183 struct mlx5_ifc_set_mad_demux_out_bits {
3184         u8         status[0x8];
3185         u8         reserved_at_8[0x18];
3186
3187         u8         syndrome[0x20];
3188
3189         u8         reserved_at_40[0x40];
3190 };
3191
3192 enum {
3193         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3194         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3195 };
3196
3197 struct mlx5_ifc_set_mad_demux_in_bits {
3198         u8         opcode[0x10];
3199         u8         reserved_at_10[0x10];
3200
3201         u8         reserved_at_20[0x10];
3202         u8         op_mod[0x10];
3203
3204         u8         reserved_at_40[0x20];
3205
3206         u8         reserved_at_60[0x6];
3207         u8         demux_mode[0x2];
3208         u8         reserved_at_68[0x18];
3209 };
3210
3211 struct mlx5_ifc_set_l2_table_entry_out_bits {
3212         u8         status[0x8];
3213         u8         reserved_at_8[0x18];
3214
3215         u8         syndrome[0x20];
3216
3217         u8         reserved_at_40[0x40];
3218 };
3219
3220 struct mlx5_ifc_set_l2_table_entry_in_bits {
3221         u8         opcode[0x10];
3222         u8         reserved_at_10[0x10];
3223
3224         u8         reserved_at_20[0x10];
3225         u8         op_mod[0x10];
3226
3227         u8         reserved_at_40[0x60];
3228
3229         u8         reserved_at_a0[0x8];
3230         u8         table_index[0x18];
3231
3232         u8         reserved_at_c0[0x20];
3233
3234         u8         reserved_at_e0[0x13];
3235         u8         vlan_valid[0x1];
3236         u8         vlan[0xc];
3237
3238         struct mlx5_ifc_mac_address_layout_bits mac_address;
3239
3240         u8         reserved_at_140[0xc0];
3241 };
3242
3243 struct mlx5_ifc_set_issi_out_bits {
3244         u8         status[0x8];
3245         u8         reserved_at_8[0x18];
3246
3247         u8         syndrome[0x20];
3248
3249         u8         reserved_at_40[0x40];
3250 };
3251
3252 struct mlx5_ifc_set_issi_in_bits {
3253         u8         opcode[0x10];
3254         u8         reserved_at_10[0x10];
3255
3256         u8         reserved_at_20[0x10];
3257         u8         op_mod[0x10];
3258
3259         u8         reserved_at_40[0x10];
3260         u8         current_issi[0x10];
3261
3262         u8         reserved_at_60[0x20];
3263 };
3264
3265 struct mlx5_ifc_set_hca_cap_out_bits {
3266         u8         status[0x8];
3267         u8         reserved_at_8[0x18];
3268
3269         u8         syndrome[0x20];
3270
3271         u8         reserved_at_40[0x40];
3272 };
3273
3274 struct mlx5_ifc_set_hca_cap_in_bits {
3275         u8         opcode[0x10];
3276         u8         reserved_at_10[0x10];
3277
3278         u8         reserved_at_20[0x10];
3279         u8         op_mod[0x10];
3280
3281         u8         reserved_at_40[0x40];
3282
3283         union mlx5_ifc_hca_cap_union_bits capability;
3284 };
3285
3286 enum {
3287         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3288         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3289         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3290         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3291 };
3292
3293 struct mlx5_ifc_set_fte_out_bits {
3294         u8         status[0x8];
3295         u8         reserved_at_8[0x18];
3296
3297         u8         syndrome[0x20];
3298
3299         u8         reserved_at_40[0x40];
3300 };
3301
3302 struct mlx5_ifc_set_fte_in_bits {
3303         u8         opcode[0x10];
3304         u8         reserved_at_10[0x10];
3305
3306         u8         reserved_at_20[0x10];
3307         u8         op_mod[0x10];
3308
3309         u8         other_vport[0x1];
3310         u8         reserved_at_41[0xf];
3311         u8         vport_number[0x10];
3312
3313         u8         reserved_at_60[0x20];
3314
3315         u8         table_type[0x8];
3316         u8         reserved_at_88[0x18];
3317
3318         u8         reserved_at_a0[0x8];
3319         u8         table_id[0x18];
3320
3321         u8         reserved_at_c0[0x18];
3322         u8         modify_enable_mask[0x8];
3323
3324         u8         reserved_at_e0[0x20];
3325
3326         u8         flow_index[0x20];
3327
3328         u8         reserved_at_120[0xe0];
3329
3330         struct mlx5_ifc_flow_context_bits flow_context;
3331 };
3332
3333 struct mlx5_ifc_rts2rts_qp_out_bits {
3334         u8         status[0x8];
3335         u8         reserved_at_8[0x18];
3336
3337         u8         syndrome[0x20];
3338
3339         u8         reserved_at_40[0x40];
3340 };
3341
3342 struct mlx5_ifc_rts2rts_qp_in_bits {
3343         u8         opcode[0x10];
3344         u8         reserved_at_10[0x10];
3345
3346         u8         reserved_at_20[0x10];
3347         u8         op_mod[0x10];
3348
3349         u8         reserved_at_40[0x8];
3350         u8         qpn[0x18];
3351
3352         u8         reserved_at_60[0x20];
3353
3354         u8         opt_param_mask[0x20];
3355
3356         u8         reserved_at_a0[0x20];
3357
3358         struct mlx5_ifc_qpc_bits qpc;
3359
3360         u8         reserved_at_800[0x80];
3361 };
3362
3363 struct mlx5_ifc_rtr2rts_qp_out_bits {
3364         u8         status[0x8];
3365         u8         reserved_at_8[0x18];
3366
3367         u8         syndrome[0x20];
3368
3369         u8         reserved_at_40[0x40];
3370 };
3371
3372 struct mlx5_ifc_rtr2rts_qp_in_bits {
3373         u8         opcode[0x10];
3374         u8         reserved_at_10[0x10];
3375
3376         u8         reserved_at_20[0x10];
3377         u8         op_mod[0x10];
3378
3379         u8         reserved_at_40[0x8];
3380         u8         qpn[0x18];
3381
3382         u8         reserved_at_60[0x20];
3383
3384         u8         opt_param_mask[0x20];
3385
3386         u8         reserved_at_a0[0x20];
3387
3388         struct mlx5_ifc_qpc_bits qpc;
3389
3390         u8         reserved_at_800[0x80];
3391 };
3392
3393 struct mlx5_ifc_rst2init_qp_out_bits {
3394         u8         status[0x8];
3395         u8         reserved_at_8[0x18];
3396
3397         u8         syndrome[0x20];
3398
3399         u8         reserved_at_40[0x40];
3400 };
3401
3402 struct mlx5_ifc_rst2init_qp_in_bits {
3403         u8         opcode[0x10];
3404         u8         reserved_at_10[0x10];
3405
3406         u8         reserved_at_20[0x10];
3407         u8         op_mod[0x10];
3408
3409         u8         reserved_at_40[0x8];
3410         u8         qpn[0x18];
3411
3412         u8         reserved_at_60[0x20];
3413
3414         u8         opt_param_mask[0x20];
3415
3416         u8         reserved_at_a0[0x20];
3417
3418         struct mlx5_ifc_qpc_bits qpc;
3419
3420         u8         reserved_at_800[0x80];
3421 };
3422
3423 struct mlx5_ifc_query_xrq_out_bits {
3424         u8         status[0x8];
3425         u8         reserved_at_8[0x18];
3426
3427         u8         syndrome[0x20];
3428
3429         u8         reserved_at_40[0x40];
3430
3431         struct mlx5_ifc_xrqc_bits xrq_context;
3432 };
3433
3434 struct mlx5_ifc_query_xrq_in_bits {
3435         u8         opcode[0x10];
3436         u8         reserved_at_10[0x10];
3437
3438         u8         reserved_at_20[0x10];
3439         u8         op_mod[0x10];
3440
3441         u8         reserved_at_40[0x8];
3442         u8         xrqn[0x18];
3443
3444         u8         reserved_at_60[0x20];
3445 };
3446
3447 struct mlx5_ifc_query_xrc_srq_out_bits {
3448         u8         status[0x8];
3449         u8         reserved_at_8[0x18];
3450
3451         u8         syndrome[0x20];
3452
3453         u8         reserved_at_40[0x40];
3454
3455         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3456
3457         u8         reserved_at_280[0x600];
3458
3459         u8         pas[0][0x40];
3460 };
3461
3462 struct mlx5_ifc_query_xrc_srq_in_bits {
3463         u8         opcode[0x10];
3464         u8         reserved_at_10[0x10];
3465
3466         u8         reserved_at_20[0x10];
3467         u8         op_mod[0x10];
3468
3469         u8         reserved_at_40[0x8];
3470         u8         xrc_srqn[0x18];
3471
3472         u8         reserved_at_60[0x20];
3473 };
3474
3475 enum {
3476         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3477         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3478 };
3479
3480 struct mlx5_ifc_query_vport_state_out_bits {
3481         u8         status[0x8];
3482         u8         reserved_at_8[0x18];
3483
3484         u8         syndrome[0x20];
3485
3486         u8         reserved_at_40[0x20];
3487
3488         u8         reserved_at_60[0x18];
3489         u8         admin_state[0x4];
3490         u8         state[0x4];
3491 };
3492
3493 enum {
3494         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3495         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3496 };
3497
3498 struct mlx5_ifc_query_vport_state_in_bits {
3499         u8         opcode[0x10];
3500         u8         reserved_at_10[0x10];
3501
3502         u8         reserved_at_20[0x10];
3503         u8         op_mod[0x10];
3504
3505         u8         other_vport[0x1];
3506         u8         reserved_at_41[0xf];
3507         u8         vport_number[0x10];
3508
3509         u8         reserved_at_60[0x20];
3510 };
3511
3512 struct mlx5_ifc_query_vport_counter_out_bits {
3513         u8         status[0x8];
3514         u8         reserved_at_8[0x18];
3515
3516         u8         syndrome[0x20];
3517
3518         u8         reserved_at_40[0x40];
3519
3520         struct mlx5_ifc_traffic_counter_bits received_errors;
3521
3522         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3523
3524         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3525
3526         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3527
3528         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3529
3530         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3531
3532         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3533
3534         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3535
3536         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3537
3538         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3539
3540         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3541
3542         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3543
3544         u8         reserved_at_680[0xa00];
3545 };
3546
3547 enum {
3548         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3549 };
3550
3551 struct mlx5_ifc_query_vport_counter_in_bits {
3552         u8         opcode[0x10];
3553         u8         reserved_at_10[0x10];
3554
3555         u8         reserved_at_20[0x10];
3556         u8         op_mod[0x10];
3557
3558         u8         other_vport[0x1];
3559         u8         reserved_at_41[0xb];
3560         u8         port_num[0x4];
3561         u8         vport_number[0x10];
3562
3563         u8         reserved_at_60[0x60];
3564
3565         u8         clear[0x1];
3566         u8         reserved_at_c1[0x1f];
3567
3568         u8         reserved_at_e0[0x20];
3569 };
3570
3571 struct mlx5_ifc_query_tis_out_bits {
3572         u8         status[0x8];
3573         u8         reserved_at_8[0x18];
3574
3575         u8         syndrome[0x20];
3576
3577         u8         reserved_at_40[0x40];
3578
3579         struct mlx5_ifc_tisc_bits tis_context;
3580 };
3581
3582 struct mlx5_ifc_query_tis_in_bits {
3583         u8         opcode[0x10];
3584         u8         reserved_at_10[0x10];
3585
3586         u8         reserved_at_20[0x10];
3587         u8         op_mod[0x10];
3588
3589         u8         reserved_at_40[0x8];
3590         u8         tisn[0x18];
3591
3592         u8         reserved_at_60[0x20];
3593 };
3594
3595 struct mlx5_ifc_query_tir_out_bits {
3596         u8         status[0x8];
3597         u8         reserved_at_8[0x18];
3598
3599         u8         syndrome[0x20];
3600
3601         u8         reserved_at_40[0xc0];
3602
3603         struct mlx5_ifc_tirc_bits tir_context;
3604 };
3605
3606 struct mlx5_ifc_query_tir_in_bits {
3607         u8         opcode[0x10];
3608         u8         reserved_at_10[0x10];
3609
3610         u8         reserved_at_20[0x10];
3611         u8         op_mod[0x10];
3612
3613         u8         reserved_at_40[0x8];
3614         u8         tirn[0x18];
3615
3616         u8         reserved_at_60[0x20];
3617 };
3618
3619 struct mlx5_ifc_query_srq_out_bits {
3620         u8         status[0x8];
3621         u8         reserved_at_8[0x18];
3622
3623         u8         syndrome[0x20];
3624
3625         u8         reserved_at_40[0x40];
3626
3627         struct mlx5_ifc_srqc_bits srq_context_entry;
3628
3629         u8         reserved_at_280[0x600];
3630
3631         u8         pas[0][0x40];
3632 };
3633
3634 struct mlx5_ifc_query_srq_in_bits {
3635         u8         opcode[0x10];
3636         u8         reserved_at_10[0x10];
3637
3638         u8         reserved_at_20[0x10];
3639         u8         op_mod[0x10];
3640
3641         u8         reserved_at_40[0x8];
3642         u8         srqn[0x18];
3643
3644         u8         reserved_at_60[0x20];
3645 };
3646
3647 struct mlx5_ifc_query_sq_out_bits {
3648         u8         status[0x8];
3649         u8         reserved_at_8[0x18];
3650
3651         u8         syndrome[0x20];
3652
3653         u8         reserved_at_40[0xc0];
3654
3655         struct mlx5_ifc_sqc_bits sq_context;
3656 };
3657
3658 struct mlx5_ifc_query_sq_in_bits {
3659         u8         opcode[0x10];
3660         u8         reserved_at_10[0x10];
3661
3662         u8         reserved_at_20[0x10];
3663         u8         op_mod[0x10];
3664
3665         u8         reserved_at_40[0x8];
3666         u8         sqn[0x18];
3667
3668         u8         reserved_at_60[0x20];
3669 };
3670
3671 struct mlx5_ifc_query_special_contexts_out_bits {
3672         u8         status[0x8];
3673         u8         reserved_at_8[0x18];
3674
3675         u8         syndrome[0x20];
3676
3677         u8         dump_fill_mkey[0x20];
3678
3679         u8         resd_lkey[0x20];
3680
3681         u8         null_mkey[0x20];
3682
3683         u8         reserved_at_a0[0x60];
3684 };
3685
3686 struct mlx5_ifc_query_special_contexts_in_bits {
3687         u8         opcode[0x10];
3688         u8         reserved_at_10[0x10];
3689
3690         u8         reserved_at_20[0x10];
3691         u8         op_mod[0x10];
3692
3693         u8         reserved_at_40[0x40];
3694 };
3695
3696 struct mlx5_ifc_query_scheduling_element_out_bits {
3697         u8         opcode[0x10];
3698         u8         reserved_at_10[0x10];
3699
3700         u8         reserved_at_20[0x10];
3701         u8         op_mod[0x10];
3702
3703         u8         reserved_at_40[0xc0];
3704
3705         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3706
3707         u8         reserved_at_300[0x100];
3708 };
3709
3710 enum {
3711         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3712 };
3713
3714 struct mlx5_ifc_query_scheduling_element_in_bits {
3715         u8         opcode[0x10];
3716         u8         reserved_at_10[0x10];
3717
3718         u8         reserved_at_20[0x10];
3719         u8         op_mod[0x10];
3720
3721         u8         scheduling_hierarchy[0x8];
3722         u8         reserved_at_48[0x18];
3723
3724         u8         scheduling_element_id[0x20];
3725
3726         u8         reserved_at_80[0x180];
3727 };
3728
3729 struct mlx5_ifc_query_rqt_out_bits {
3730         u8         status[0x8];
3731         u8         reserved_at_8[0x18];
3732
3733         u8         syndrome[0x20];
3734
3735         u8         reserved_at_40[0xc0];
3736
3737         struct mlx5_ifc_rqtc_bits rqt_context;
3738 };
3739
3740 struct mlx5_ifc_query_rqt_in_bits {
3741         u8         opcode[0x10];
3742         u8         reserved_at_10[0x10];
3743
3744         u8         reserved_at_20[0x10];
3745         u8         op_mod[0x10];
3746
3747         u8         reserved_at_40[0x8];
3748         u8         rqtn[0x18];
3749
3750         u8         reserved_at_60[0x20];
3751 };
3752
3753 struct mlx5_ifc_query_rq_out_bits {
3754         u8         status[0x8];
3755         u8         reserved_at_8[0x18];
3756
3757         u8         syndrome[0x20];
3758
3759         u8         reserved_at_40[0xc0];
3760
3761         struct mlx5_ifc_rqc_bits rq_context;
3762 };
3763
3764 struct mlx5_ifc_query_rq_in_bits {
3765         u8         opcode[0x10];
3766         u8         reserved_at_10[0x10];
3767
3768         u8         reserved_at_20[0x10];
3769         u8         op_mod[0x10];
3770
3771         u8         reserved_at_40[0x8];
3772         u8         rqn[0x18];
3773
3774         u8         reserved_at_60[0x20];
3775 };
3776
3777 struct mlx5_ifc_query_roce_address_out_bits {
3778         u8         status[0x8];
3779         u8         reserved_at_8[0x18];
3780
3781         u8         syndrome[0x20];
3782
3783         u8         reserved_at_40[0x40];
3784
3785         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3786 };
3787
3788 struct mlx5_ifc_query_roce_address_in_bits {
3789         u8         opcode[0x10];
3790         u8         reserved_at_10[0x10];
3791
3792         u8         reserved_at_20[0x10];
3793         u8         op_mod[0x10];
3794
3795         u8         roce_address_index[0x10];
3796         u8         reserved_at_50[0x10];
3797
3798         u8         reserved_at_60[0x20];
3799 };
3800
3801 struct mlx5_ifc_query_rmp_out_bits {
3802         u8         status[0x8];
3803         u8         reserved_at_8[0x18];
3804
3805         u8         syndrome[0x20];
3806
3807         u8         reserved_at_40[0xc0];
3808
3809         struct mlx5_ifc_rmpc_bits rmp_context;
3810 };
3811
3812 struct mlx5_ifc_query_rmp_in_bits {
3813         u8         opcode[0x10];
3814         u8         reserved_at_10[0x10];
3815
3816         u8         reserved_at_20[0x10];
3817         u8         op_mod[0x10];
3818
3819         u8         reserved_at_40[0x8];
3820         u8         rmpn[0x18];
3821
3822         u8         reserved_at_60[0x20];
3823 };
3824
3825 struct mlx5_ifc_query_qp_out_bits {
3826         u8         status[0x8];
3827         u8         reserved_at_8[0x18];
3828
3829         u8         syndrome[0x20];
3830
3831         u8         reserved_at_40[0x40];
3832
3833         u8         opt_param_mask[0x20];
3834
3835         u8         reserved_at_a0[0x20];
3836
3837         struct mlx5_ifc_qpc_bits qpc;
3838
3839         u8         reserved_at_800[0x80];
3840
3841         u8         pas[0][0x40];
3842 };
3843
3844 struct mlx5_ifc_query_qp_in_bits {
3845         u8         opcode[0x10];
3846         u8         reserved_at_10[0x10];
3847
3848         u8         reserved_at_20[0x10];
3849         u8         op_mod[0x10];
3850
3851         u8         reserved_at_40[0x8];
3852         u8         qpn[0x18];
3853
3854         u8         reserved_at_60[0x20];
3855 };
3856
3857 struct mlx5_ifc_query_q_counter_out_bits {
3858         u8         status[0x8];
3859         u8         reserved_at_8[0x18];
3860
3861         u8         syndrome[0x20];
3862
3863         u8         reserved_at_40[0x40];
3864
3865         u8         rx_write_requests[0x20];
3866
3867         u8         reserved_at_a0[0x20];
3868
3869         u8         rx_read_requests[0x20];
3870
3871         u8         reserved_at_e0[0x20];
3872
3873         u8         rx_atomic_requests[0x20];
3874
3875         u8         reserved_at_120[0x20];
3876
3877         u8         rx_dct_connect[0x20];
3878
3879         u8         reserved_at_160[0x20];
3880
3881         u8         out_of_buffer[0x20];
3882
3883         u8         reserved_at_1a0[0x20];
3884
3885         u8         out_of_sequence[0x20];
3886
3887         u8         reserved_at_1e0[0x20];
3888
3889         u8         duplicate_request[0x20];
3890
3891         u8         reserved_at_220[0x20];
3892
3893         u8         rnr_nak_retry_err[0x20];
3894
3895         u8         reserved_at_260[0x20];
3896
3897         u8         packet_seq_err[0x20];
3898
3899         u8         reserved_at_2a0[0x20];
3900
3901         u8         implied_nak_seq_err[0x20];
3902
3903         u8         reserved_at_2e0[0x20];
3904
3905         u8         local_ack_timeout_err[0x20];
3906
3907         u8         reserved_at_320[0x4e0];
3908 };
3909
3910 struct mlx5_ifc_query_q_counter_in_bits {
3911         u8         opcode[0x10];
3912         u8         reserved_at_10[0x10];
3913
3914         u8         reserved_at_20[0x10];
3915         u8         op_mod[0x10];
3916
3917         u8         reserved_at_40[0x80];
3918
3919         u8         clear[0x1];
3920         u8         reserved_at_c1[0x1f];
3921
3922         u8         reserved_at_e0[0x18];
3923         u8         counter_set_id[0x8];
3924 };
3925
3926 struct mlx5_ifc_query_pages_out_bits {
3927         u8         status[0x8];
3928         u8         reserved_at_8[0x18];
3929
3930         u8         syndrome[0x20];
3931
3932         u8         reserved_at_40[0x10];
3933         u8         function_id[0x10];
3934
3935         u8         num_pages[0x20];
3936 };
3937
3938 enum {
3939         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3940         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3941         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3942 };
3943
3944 struct mlx5_ifc_query_pages_in_bits {
3945         u8         opcode[0x10];
3946         u8         reserved_at_10[0x10];
3947
3948         u8         reserved_at_20[0x10];
3949         u8         op_mod[0x10];
3950
3951         u8         reserved_at_40[0x10];
3952         u8         function_id[0x10];
3953
3954         u8         reserved_at_60[0x20];
3955 };
3956
3957 struct mlx5_ifc_query_nic_vport_context_out_bits {
3958         u8         status[0x8];
3959         u8         reserved_at_8[0x18];
3960
3961         u8         syndrome[0x20];
3962
3963         u8         reserved_at_40[0x40];
3964
3965         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3966 };
3967
3968 struct mlx5_ifc_query_nic_vport_context_in_bits {
3969         u8         opcode[0x10];
3970         u8         reserved_at_10[0x10];
3971
3972         u8         reserved_at_20[0x10];
3973         u8         op_mod[0x10];
3974
3975         u8         other_vport[0x1];
3976         u8         reserved_at_41[0xf];
3977         u8         vport_number[0x10];
3978
3979         u8         reserved_at_60[0x5];
3980         u8         allowed_list_type[0x3];
3981         u8         reserved_at_68[0x18];
3982 };
3983
3984 struct mlx5_ifc_query_mkey_out_bits {
3985         u8         status[0x8];
3986         u8         reserved_at_8[0x18];
3987
3988         u8         syndrome[0x20];
3989
3990         u8         reserved_at_40[0x40];
3991
3992         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3993
3994         u8         reserved_at_280[0x600];
3995
3996         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3997
3998         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3999 };
4000
4001 struct mlx5_ifc_query_mkey_in_bits {
4002         u8         opcode[0x10];
4003         u8         reserved_at_10[0x10];
4004
4005         u8         reserved_at_20[0x10];
4006         u8         op_mod[0x10];
4007
4008         u8         reserved_at_40[0x8];
4009         u8         mkey_index[0x18];
4010
4011         u8         pg_access[0x1];
4012         u8         reserved_at_61[0x1f];
4013 };
4014
4015 struct mlx5_ifc_query_mad_demux_out_bits {
4016         u8         status[0x8];
4017         u8         reserved_at_8[0x18];
4018
4019         u8         syndrome[0x20];
4020
4021         u8         reserved_at_40[0x40];
4022
4023         u8         mad_dumux_parameters_block[0x20];
4024 };
4025
4026 struct mlx5_ifc_query_mad_demux_in_bits {
4027         u8         opcode[0x10];
4028         u8         reserved_at_10[0x10];
4029
4030         u8         reserved_at_20[0x10];
4031         u8         op_mod[0x10];
4032
4033         u8         reserved_at_40[0x40];
4034 };
4035
4036 struct mlx5_ifc_query_l2_table_entry_out_bits {
4037         u8         status[0x8];
4038         u8         reserved_at_8[0x18];
4039
4040         u8         syndrome[0x20];
4041
4042         u8         reserved_at_40[0xa0];
4043
4044         u8         reserved_at_e0[0x13];
4045         u8         vlan_valid[0x1];
4046         u8         vlan[0xc];
4047
4048         struct mlx5_ifc_mac_address_layout_bits mac_address;
4049
4050         u8         reserved_at_140[0xc0];
4051 };
4052
4053 struct mlx5_ifc_query_l2_table_entry_in_bits {
4054         u8         opcode[0x10];
4055         u8         reserved_at_10[0x10];
4056
4057         u8         reserved_at_20[0x10];
4058         u8         op_mod[0x10];
4059
4060         u8         reserved_at_40[0x60];
4061
4062         u8         reserved_at_a0[0x8];
4063         u8         table_index[0x18];
4064
4065         u8         reserved_at_c0[0x140];
4066 };
4067
4068 struct mlx5_ifc_query_issi_out_bits {
4069         u8         status[0x8];
4070         u8         reserved_at_8[0x18];
4071
4072         u8         syndrome[0x20];
4073
4074         u8         reserved_at_40[0x10];
4075         u8         current_issi[0x10];
4076
4077         u8         reserved_at_60[0xa0];
4078
4079         u8         reserved_at_100[76][0x8];
4080         u8         supported_issi_dw0[0x20];
4081 };
4082
4083 struct mlx5_ifc_query_issi_in_bits {
4084         u8         opcode[0x10];
4085         u8         reserved_at_10[0x10];
4086
4087         u8         reserved_at_20[0x10];
4088         u8         op_mod[0x10];
4089
4090         u8         reserved_at_40[0x40];
4091 };
4092
4093 struct mlx5_ifc_set_driver_version_out_bits {
4094         u8         status[0x8];
4095         u8         reserved_0[0x18];
4096
4097         u8         syndrome[0x20];
4098         u8         reserved_1[0x40];
4099 };
4100
4101 struct mlx5_ifc_set_driver_version_in_bits {
4102         u8         opcode[0x10];
4103         u8         reserved_0[0x10];
4104
4105         u8         reserved_1[0x10];
4106         u8         op_mod[0x10];
4107
4108         u8         reserved_2[0x40];
4109         u8         driver_version[64][0x8];
4110 };
4111
4112 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4113         u8         status[0x8];
4114         u8         reserved_at_8[0x18];
4115
4116         u8         syndrome[0x20];
4117
4118         u8         reserved_at_40[0x40];
4119
4120         struct mlx5_ifc_pkey_bits pkey[0];
4121 };
4122
4123 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4124         u8         opcode[0x10];
4125         u8         reserved_at_10[0x10];
4126
4127         u8         reserved_at_20[0x10];
4128         u8         op_mod[0x10];
4129
4130         u8         other_vport[0x1];
4131         u8         reserved_at_41[0xb];
4132         u8         port_num[0x4];
4133         u8         vport_number[0x10];
4134
4135         u8         reserved_at_60[0x10];
4136         u8         pkey_index[0x10];
4137 };
4138
4139 enum {
4140         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4141         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4142         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4143 };
4144
4145 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4146         u8         status[0x8];
4147         u8         reserved_at_8[0x18];
4148
4149         u8         syndrome[0x20];
4150
4151         u8         reserved_at_40[0x20];
4152
4153         u8         gids_num[0x10];
4154         u8         reserved_at_70[0x10];
4155
4156         struct mlx5_ifc_array128_auto_bits gid[0];
4157 };
4158
4159 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4160         u8         opcode[0x10];
4161         u8         reserved_at_10[0x10];
4162
4163         u8         reserved_at_20[0x10];
4164         u8         op_mod[0x10];
4165
4166         u8         other_vport[0x1];
4167         u8         reserved_at_41[0xb];
4168         u8         port_num[0x4];
4169         u8         vport_number[0x10];
4170
4171         u8         reserved_at_60[0x10];
4172         u8         gid_index[0x10];
4173 };
4174
4175 struct mlx5_ifc_query_hca_vport_context_out_bits {
4176         u8         status[0x8];
4177         u8         reserved_at_8[0x18];
4178
4179         u8         syndrome[0x20];
4180
4181         u8         reserved_at_40[0x40];
4182
4183         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4184 };
4185
4186 struct mlx5_ifc_query_hca_vport_context_in_bits {
4187         u8         opcode[0x10];
4188         u8         reserved_at_10[0x10];
4189
4190         u8         reserved_at_20[0x10];
4191         u8         op_mod[0x10];
4192
4193         u8         other_vport[0x1];
4194         u8         reserved_at_41[0xb];
4195         u8         port_num[0x4];
4196         u8         vport_number[0x10];
4197
4198         u8         reserved_at_60[0x20];
4199 };
4200
4201 struct mlx5_ifc_query_hca_cap_out_bits {
4202         u8         status[0x8];
4203         u8         reserved_at_8[0x18];
4204
4205         u8         syndrome[0x20];
4206
4207         u8         reserved_at_40[0x40];
4208
4209         union mlx5_ifc_hca_cap_union_bits capability;
4210 };
4211
4212 struct mlx5_ifc_query_hca_cap_in_bits {
4213         u8         opcode[0x10];
4214         u8         reserved_at_10[0x10];
4215
4216         u8         reserved_at_20[0x10];
4217         u8         op_mod[0x10];
4218
4219         u8         reserved_at_40[0x40];
4220 };
4221
4222 struct mlx5_ifc_query_flow_table_out_bits {
4223         u8         status[0x8];
4224         u8         reserved_at_8[0x18];
4225
4226         u8         syndrome[0x20];
4227
4228         u8         reserved_at_40[0x80];
4229
4230         u8         reserved_at_c0[0x8];
4231         u8         level[0x8];
4232         u8         reserved_at_d0[0x8];
4233         u8         log_size[0x8];
4234
4235         u8         reserved_at_e0[0x120];
4236 };
4237
4238 struct mlx5_ifc_query_flow_table_in_bits {
4239         u8         opcode[0x10];
4240         u8         reserved_at_10[0x10];
4241
4242         u8         reserved_at_20[0x10];
4243         u8         op_mod[0x10];
4244
4245         u8         reserved_at_40[0x40];
4246
4247         u8         table_type[0x8];
4248         u8         reserved_at_88[0x18];
4249
4250         u8         reserved_at_a0[0x8];
4251         u8         table_id[0x18];
4252
4253         u8         reserved_at_c0[0x140];
4254 };
4255
4256 struct mlx5_ifc_query_fte_out_bits {
4257         u8         status[0x8];
4258         u8         reserved_at_8[0x18];
4259
4260         u8         syndrome[0x20];
4261
4262         u8         reserved_at_40[0x1c0];
4263
4264         struct mlx5_ifc_flow_context_bits flow_context;
4265 };
4266
4267 struct mlx5_ifc_query_fte_in_bits {
4268         u8         opcode[0x10];
4269         u8         reserved_at_10[0x10];
4270
4271         u8         reserved_at_20[0x10];
4272         u8         op_mod[0x10];
4273
4274         u8         reserved_at_40[0x40];
4275
4276         u8         table_type[0x8];
4277         u8         reserved_at_88[0x18];
4278
4279         u8         reserved_at_a0[0x8];
4280         u8         table_id[0x18];
4281
4282         u8         reserved_at_c0[0x40];
4283
4284         u8         flow_index[0x20];
4285
4286         u8         reserved_at_120[0xe0];
4287 };
4288
4289 enum {
4290         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4291         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4292         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4293 };
4294
4295 struct mlx5_ifc_query_flow_group_out_bits {
4296         u8         status[0x8];
4297         u8         reserved_at_8[0x18];
4298
4299         u8         syndrome[0x20];
4300
4301         u8         reserved_at_40[0xa0];
4302
4303         u8         start_flow_index[0x20];
4304
4305         u8         reserved_at_100[0x20];
4306
4307         u8         end_flow_index[0x20];
4308
4309         u8         reserved_at_140[0xa0];
4310
4311         u8         reserved_at_1e0[0x18];
4312         u8         match_criteria_enable[0x8];
4313
4314         struct mlx5_ifc_fte_match_param_bits match_criteria;
4315
4316         u8         reserved_at_1200[0xe00];
4317 };
4318
4319 struct mlx5_ifc_query_flow_group_in_bits {
4320         u8         opcode[0x10];
4321         u8         reserved_at_10[0x10];
4322
4323         u8         reserved_at_20[0x10];
4324         u8         op_mod[0x10];
4325
4326         u8         reserved_at_40[0x40];
4327
4328         u8         table_type[0x8];
4329         u8         reserved_at_88[0x18];
4330
4331         u8         reserved_at_a0[0x8];
4332         u8         table_id[0x18];
4333
4334         u8         group_id[0x20];
4335
4336         u8         reserved_at_e0[0x120];
4337 };
4338
4339 struct mlx5_ifc_query_flow_counter_out_bits {
4340         u8         status[0x8];
4341         u8         reserved_at_8[0x18];
4342
4343         u8         syndrome[0x20];
4344
4345         u8         reserved_at_40[0x40];
4346
4347         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4348 };
4349
4350 struct mlx5_ifc_query_flow_counter_in_bits {
4351         u8         opcode[0x10];
4352         u8         reserved_at_10[0x10];
4353
4354         u8         reserved_at_20[0x10];
4355         u8         op_mod[0x10];
4356
4357         u8         reserved_at_40[0x80];
4358
4359         u8         clear[0x1];
4360         u8         reserved_at_c1[0xf];
4361         u8         num_of_counters[0x10];
4362
4363         u8         reserved_at_e0[0x10];
4364         u8         flow_counter_id[0x10];
4365 };
4366
4367 struct mlx5_ifc_query_esw_vport_context_out_bits {
4368         u8         status[0x8];
4369         u8         reserved_at_8[0x18];
4370
4371         u8         syndrome[0x20];
4372
4373         u8         reserved_at_40[0x40];
4374
4375         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4376 };
4377
4378 struct mlx5_ifc_query_esw_vport_context_in_bits {
4379         u8         opcode[0x10];
4380         u8         reserved_at_10[0x10];
4381
4382         u8         reserved_at_20[0x10];
4383         u8         op_mod[0x10];
4384
4385         u8         other_vport[0x1];
4386         u8         reserved_at_41[0xf];
4387         u8         vport_number[0x10];
4388
4389         u8         reserved_at_60[0x20];
4390 };
4391
4392 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4393         u8         status[0x8];
4394         u8         reserved_at_8[0x18];
4395
4396         u8         syndrome[0x20];
4397
4398         u8         reserved_at_40[0x40];
4399 };
4400
4401 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4402         u8         reserved_at_0[0x1c];
4403         u8         vport_cvlan_insert[0x1];
4404         u8         vport_svlan_insert[0x1];
4405         u8         vport_cvlan_strip[0x1];
4406         u8         vport_svlan_strip[0x1];
4407 };
4408
4409 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4410         u8         opcode[0x10];
4411         u8         reserved_at_10[0x10];
4412
4413         u8         reserved_at_20[0x10];
4414         u8         op_mod[0x10];
4415
4416         u8         other_vport[0x1];
4417         u8         reserved_at_41[0xf];
4418         u8         vport_number[0x10];
4419
4420         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4421
4422         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4423 };
4424
4425 struct mlx5_ifc_query_eq_out_bits {
4426         u8         status[0x8];
4427         u8         reserved_at_8[0x18];
4428
4429         u8         syndrome[0x20];
4430
4431         u8         reserved_at_40[0x40];
4432
4433         struct mlx5_ifc_eqc_bits eq_context_entry;
4434
4435         u8         reserved_at_280[0x40];
4436
4437         u8         event_bitmask[0x40];
4438
4439         u8         reserved_at_300[0x580];
4440
4441         u8         pas[0][0x40];
4442 };
4443
4444 struct mlx5_ifc_query_eq_in_bits {
4445         u8         opcode[0x10];
4446         u8         reserved_at_10[0x10];
4447
4448         u8         reserved_at_20[0x10];
4449         u8         op_mod[0x10];
4450
4451         u8         reserved_at_40[0x18];
4452         u8         eq_number[0x8];
4453
4454         u8         reserved_at_60[0x20];
4455 };
4456
4457 struct mlx5_ifc_encap_header_in_bits {
4458         u8         reserved_at_0[0x5];
4459         u8         header_type[0x3];
4460         u8         reserved_at_8[0xe];
4461         u8         encap_header_size[0xa];
4462
4463         u8         reserved_at_20[0x10];
4464         u8         encap_header[2][0x8];
4465
4466         u8         more_encap_header[0][0x8];
4467 };
4468
4469 struct mlx5_ifc_query_encap_header_out_bits {
4470         u8         status[0x8];
4471         u8         reserved_at_8[0x18];
4472
4473         u8         syndrome[0x20];
4474
4475         u8         reserved_at_40[0xa0];
4476
4477         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4478 };
4479
4480 struct mlx5_ifc_query_encap_header_in_bits {
4481         u8         opcode[0x10];
4482         u8         reserved_at_10[0x10];
4483
4484         u8         reserved_at_20[0x10];
4485         u8         op_mod[0x10];
4486
4487         u8         encap_id[0x20];
4488
4489         u8         reserved_at_60[0xa0];
4490 };
4491
4492 struct mlx5_ifc_alloc_encap_header_out_bits {
4493         u8         status[0x8];
4494         u8         reserved_at_8[0x18];
4495
4496         u8         syndrome[0x20];
4497
4498         u8         encap_id[0x20];
4499
4500         u8         reserved_at_60[0x20];
4501 };
4502
4503 struct mlx5_ifc_alloc_encap_header_in_bits {
4504         u8         opcode[0x10];
4505         u8         reserved_at_10[0x10];
4506
4507         u8         reserved_at_20[0x10];
4508         u8         op_mod[0x10];
4509
4510         u8         reserved_at_40[0xa0];
4511
4512         struct mlx5_ifc_encap_header_in_bits encap_header;
4513 };
4514
4515 struct mlx5_ifc_dealloc_encap_header_out_bits {
4516         u8         status[0x8];
4517         u8         reserved_at_8[0x18];
4518
4519         u8         syndrome[0x20];
4520
4521         u8         reserved_at_40[0x40];
4522 };
4523
4524 struct mlx5_ifc_dealloc_encap_header_in_bits {
4525         u8         opcode[0x10];
4526         u8         reserved_at_10[0x10];
4527
4528         u8         reserved_20[0x10];
4529         u8         op_mod[0x10];
4530
4531         u8         encap_id[0x20];
4532
4533         u8         reserved_60[0x20];
4534 };
4535
4536 struct mlx5_ifc_query_dct_out_bits {
4537         u8         status[0x8];
4538         u8         reserved_at_8[0x18];
4539
4540         u8         syndrome[0x20];
4541
4542         u8         reserved_at_40[0x40];
4543
4544         struct mlx5_ifc_dctc_bits dct_context_entry;
4545
4546         u8         reserved_at_280[0x180];
4547 };
4548
4549 struct mlx5_ifc_query_dct_in_bits {
4550         u8         opcode[0x10];
4551         u8         reserved_at_10[0x10];
4552
4553         u8         reserved_at_20[0x10];
4554         u8         op_mod[0x10];
4555
4556         u8         reserved_at_40[0x8];
4557         u8         dctn[0x18];
4558
4559         u8         reserved_at_60[0x20];
4560 };
4561
4562 struct mlx5_ifc_query_cq_out_bits {
4563         u8         status[0x8];
4564         u8         reserved_at_8[0x18];
4565
4566         u8         syndrome[0x20];
4567
4568         u8         reserved_at_40[0x40];
4569
4570         struct mlx5_ifc_cqc_bits cq_context;
4571
4572         u8         reserved_at_280[0x600];
4573
4574         u8         pas[0][0x40];
4575 };
4576
4577 struct mlx5_ifc_query_cq_in_bits {
4578         u8         opcode[0x10];
4579         u8         reserved_at_10[0x10];
4580
4581         u8         reserved_at_20[0x10];
4582         u8         op_mod[0x10];
4583
4584         u8         reserved_at_40[0x8];
4585         u8         cqn[0x18];
4586
4587         u8         reserved_at_60[0x20];
4588 };
4589
4590 struct mlx5_ifc_query_cong_status_out_bits {
4591         u8         status[0x8];
4592         u8         reserved_at_8[0x18];
4593
4594         u8         syndrome[0x20];
4595
4596         u8         reserved_at_40[0x20];
4597
4598         u8         enable[0x1];
4599         u8         tag_enable[0x1];
4600         u8         reserved_at_62[0x1e];
4601 };
4602
4603 struct mlx5_ifc_query_cong_status_in_bits {
4604         u8         opcode[0x10];
4605         u8         reserved_at_10[0x10];
4606
4607         u8         reserved_at_20[0x10];
4608         u8         op_mod[0x10];
4609
4610         u8         reserved_at_40[0x18];
4611         u8         priority[0x4];
4612         u8         cong_protocol[0x4];
4613
4614         u8         reserved_at_60[0x20];
4615 };
4616
4617 struct mlx5_ifc_query_cong_statistics_out_bits {
4618         u8         status[0x8];
4619         u8         reserved_at_8[0x18];
4620
4621         u8         syndrome[0x20];
4622
4623         u8         reserved_at_40[0x40];
4624
4625         u8         cur_flows[0x20];
4626
4627         u8         sum_flows[0x20];
4628
4629         u8         cnp_ignored_high[0x20];
4630
4631         u8         cnp_ignored_low[0x20];
4632
4633         u8         cnp_handled_high[0x20];
4634
4635         u8         cnp_handled_low[0x20];
4636
4637         u8         reserved_at_140[0x100];
4638
4639         u8         time_stamp_high[0x20];
4640
4641         u8         time_stamp_low[0x20];
4642
4643         u8         accumulators_period[0x20];
4644
4645         u8         ecn_marked_roce_packets_high[0x20];
4646
4647         u8         ecn_marked_roce_packets_low[0x20];
4648
4649         u8         cnps_sent_high[0x20];
4650
4651         u8         cnps_sent_low[0x20];
4652
4653         u8         reserved_at_320[0x560];
4654 };
4655
4656 struct mlx5_ifc_query_cong_statistics_in_bits {
4657         u8         opcode[0x10];
4658         u8         reserved_at_10[0x10];
4659
4660         u8         reserved_at_20[0x10];
4661         u8         op_mod[0x10];
4662
4663         u8         clear[0x1];
4664         u8         reserved_at_41[0x1f];
4665
4666         u8         reserved_at_60[0x20];
4667 };
4668
4669 struct mlx5_ifc_query_cong_params_out_bits {
4670         u8         status[0x8];
4671         u8         reserved_at_8[0x18];
4672
4673         u8         syndrome[0x20];
4674
4675         u8         reserved_at_40[0x40];
4676
4677         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4678 };
4679
4680 struct mlx5_ifc_query_cong_params_in_bits {
4681         u8         opcode[0x10];
4682         u8         reserved_at_10[0x10];
4683
4684         u8         reserved_at_20[0x10];
4685         u8         op_mod[0x10];
4686
4687         u8         reserved_at_40[0x1c];
4688         u8         cong_protocol[0x4];
4689
4690         u8         reserved_at_60[0x20];
4691 };
4692
4693 struct mlx5_ifc_query_adapter_out_bits {
4694         u8         status[0x8];
4695         u8         reserved_at_8[0x18];
4696
4697         u8         syndrome[0x20];
4698
4699         u8         reserved_at_40[0x40];
4700
4701         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4702 };
4703
4704 struct mlx5_ifc_query_adapter_in_bits {
4705         u8         opcode[0x10];
4706         u8         reserved_at_10[0x10];
4707
4708         u8         reserved_at_20[0x10];
4709         u8         op_mod[0x10];
4710
4711         u8         reserved_at_40[0x40];
4712 };
4713
4714 struct mlx5_ifc_qp_2rst_out_bits {
4715         u8         status[0x8];
4716         u8         reserved_at_8[0x18];
4717
4718         u8         syndrome[0x20];
4719
4720         u8         reserved_at_40[0x40];
4721 };
4722
4723 struct mlx5_ifc_qp_2rst_in_bits {
4724         u8         opcode[0x10];
4725         u8         reserved_at_10[0x10];
4726
4727         u8         reserved_at_20[0x10];
4728         u8         op_mod[0x10];
4729
4730         u8         reserved_at_40[0x8];
4731         u8         qpn[0x18];
4732
4733         u8         reserved_at_60[0x20];
4734 };
4735
4736 struct mlx5_ifc_qp_2err_out_bits {
4737         u8         status[0x8];
4738         u8         reserved_at_8[0x18];
4739
4740         u8         syndrome[0x20];
4741
4742         u8         reserved_at_40[0x40];
4743 };
4744
4745 struct mlx5_ifc_qp_2err_in_bits {
4746         u8         opcode[0x10];
4747         u8         reserved_at_10[0x10];
4748
4749         u8         reserved_at_20[0x10];
4750         u8         op_mod[0x10];
4751
4752         u8         reserved_at_40[0x8];
4753         u8         qpn[0x18];
4754
4755         u8         reserved_at_60[0x20];
4756 };
4757
4758 struct mlx5_ifc_page_fault_resume_out_bits {
4759         u8         status[0x8];
4760         u8         reserved_at_8[0x18];
4761
4762         u8         syndrome[0x20];
4763
4764         u8         reserved_at_40[0x40];
4765 };
4766
4767 struct mlx5_ifc_page_fault_resume_in_bits {
4768         u8         opcode[0x10];
4769         u8         reserved_at_10[0x10];
4770
4771         u8         reserved_at_20[0x10];
4772         u8         op_mod[0x10];
4773
4774         u8         error[0x1];
4775         u8         reserved_at_41[0x4];
4776         u8         page_fault_type[0x3];
4777         u8         wq_number[0x18];
4778
4779         u8         reserved_at_60[0x8];
4780         u8         token[0x18];
4781 };
4782
4783 struct mlx5_ifc_nop_out_bits {
4784         u8         status[0x8];
4785         u8         reserved_at_8[0x18];
4786
4787         u8         syndrome[0x20];
4788
4789         u8         reserved_at_40[0x40];
4790 };
4791
4792 struct mlx5_ifc_nop_in_bits {
4793         u8         opcode[0x10];
4794         u8         reserved_at_10[0x10];
4795
4796         u8         reserved_at_20[0x10];
4797         u8         op_mod[0x10];
4798
4799         u8         reserved_at_40[0x40];
4800 };
4801
4802 struct mlx5_ifc_modify_vport_state_out_bits {
4803         u8         status[0x8];
4804         u8         reserved_at_8[0x18];
4805
4806         u8         syndrome[0x20];
4807
4808         u8         reserved_at_40[0x40];
4809 };
4810
4811 struct mlx5_ifc_modify_vport_state_in_bits {
4812         u8         opcode[0x10];
4813         u8         reserved_at_10[0x10];
4814
4815         u8         reserved_at_20[0x10];
4816         u8         op_mod[0x10];
4817
4818         u8         other_vport[0x1];
4819         u8         reserved_at_41[0xf];
4820         u8         vport_number[0x10];
4821
4822         u8         reserved_at_60[0x18];
4823         u8         admin_state[0x4];
4824         u8         reserved_at_7c[0x4];
4825 };
4826
4827 struct mlx5_ifc_modify_tis_out_bits {
4828         u8         status[0x8];
4829         u8         reserved_at_8[0x18];
4830
4831         u8         syndrome[0x20];
4832
4833         u8         reserved_at_40[0x40];
4834 };
4835
4836 struct mlx5_ifc_modify_tis_bitmask_bits {
4837         u8         reserved_at_0[0x20];
4838
4839         u8         reserved_at_20[0x1d];
4840         u8         lag_tx_port_affinity[0x1];
4841         u8         strict_lag_tx_port_affinity[0x1];
4842         u8         prio[0x1];
4843 };
4844
4845 struct mlx5_ifc_modify_tis_in_bits {
4846         u8         opcode[0x10];
4847         u8         reserved_at_10[0x10];
4848
4849         u8         reserved_at_20[0x10];
4850         u8         op_mod[0x10];
4851
4852         u8         reserved_at_40[0x8];
4853         u8         tisn[0x18];
4854
4855         u8         reserved_at_60[0x20];
4856
4857         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4858
4859         u8         reserved_at_c0[0x40];
4860
4861         struct mlx5_ifc_tisc_bits ctx;
4862 };
4863
4864 struct mlx5_ifc_modify_tir_bitmask_bits {
4865         u8         reserved_at_0[0x20];
4866
4867         u8         reserved_at_20[0x1b];
4868         u8         self_lb_en[0x1];
4869         u8         reserved_at_3c[0x1];
4870         u8         hash[0x1];
4871         u8         reserved_at_3e[0x1];
4872         u8         lro[0x1];
4873 };
4874
4875 struct mlx5_ifc_modify_tir_out_bits {
4876         u8         status[0x8];
4877         u8         reserved_at_8[0x18];
4878
4879         u8         syndrome[0x20];
4880
4881         u8         reserved_at_40[0x40];
4882 };
4883
4884 struct mlx5_ifc_modify_tir_in_bits {
4885         u8         opcode[0x10];
4886         u8         reserved_at_10[0x10];
4887
4888         u8         reserved_at_20[0x10];
4889         u8         op_mod[0x10];
4890
4891         u8         reserved_at_40[0x8];
4892         u8         tirn[0x18];
4893
4894         u8         reserved_at_60[0x20];
4895
4896         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4897
4898         u8         reserved_at_c0[0x40];
4899
4900         struct mlx5_ifc_tirc_bits ctx;
4901 };
4902
4903 struct mlx5_ifc_modify_sq_out_bits {
4904         u8         status[0x8];
4905         u8         reserved_at_8[0x18];
4906
4907         u8         syndrome[0x20];
4908
4909         u8         reserved_at_40[0x40];
4910 };
4911
4912 struct mlx5_ifc_modify_sq_in_bits {
4913         u8         opcode[0x10];
4914         u8         reserved_at_10[0x10];
4915
4916         u8         reserved_at_20[0x10];
4917         u8         op_mod[0x10];
4918
4919         u8         sq_state[0x4];
4920         u8         reserved_at_44[0x4];
4921         u8         sqn[0x18];
4922
4923         u8         reserved_at_60[0x20];
4924
4925         u8         modify_bitmask[0x40];
4926
4927         u8         reserved_at_c0[0x40];
4928
4929         struct mlx5_ifc_sqc_bits ctx;
4930 };
4931
4932 struct mlx5_ifc_modify_scheduling_element_out_bits {
4933         u8         status[0x8];
4934         u8         reserved_at_8[0x18];
4935
4936         u8         syndrome[0x20];
4937
4938         u8         reserved_at_40[0x1c0];
4939 };
4940
4941 enum {
4942         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4943         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4944 };
4945
4946 struct mlx5_ifc_modify_scheduling_element_in_bits {
4947         u8         opcode[0x10];
4948         u8         reserved_at_10[0x10];
4949
4950         u8         reserved_at_20[0x10];
4951         u8         op_mod[0x10];
4952
4953         u8         scheduling_hierarchy[0x8];
4954         u8         reserved_at_48[0x18];
4955
4956         u8         scheduling_element_id[0x20];
4957
4958         u8         reserved_at_80[0x20];
4959
4960         u8         modify_bitmask[0x20];
4961
4962         u8         reserved_at_c0[0x40];
4963
4964         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4965
4966         u8         reserved_at_300[0x100];
4967 };
4968
4969 struct mlx5_ifc_modify_rqt_out_bits {
4970         u8         status[0x8];
4971         u8         reserved_at_8[0x18];
4972
4973         u8         syndrome[0x20];
4974
4975         u8         reserved_at_40[0x40];
4976 };
4977
4978 struct mlx5_ifc_rqt_bitmask_bits {
4979         u8         reserved_at_0[0x20];
4980
4981         u8         reserved_at_20[0x1f];
4982         u8         rqn_list[0x1];
4983 };
4984
4985 struct mlx5_ifc_modify_rqt_in_bits {
4986         u8         opcode[0x10];
4987         u8         reserved_at_10[0x10];
4988
4989         u8         reserved_at_20[0x10];
4990         u8         op_mod[0x10];
4991
4992         u8         reserved_at_40[0x8];
4993         u8         rqtn[0x18];
4994
4995         u8         reserved_at_60[0x20];
4996
4997         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4998
4999         u8         reserved_at_c0[0x40];
5000
5001         struct mlx5_ifc_rqtc_bits ctx;
5002 };
5003
5004 struct mlx5_ifc_modify_rq_out_bits {
5005         u8         status[0x8];
5006         u8         reserved_at_8[0x18];
5007
5008         u8         syndrome[0x20];
5009
5010         u8         reserved_at_40[0x40];
5011 };
5012
5013 enum {
5014         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5015         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5016 };
5017
5018 struct mlx5_ifc_modify_rq_in_bits {
5019         u8         opcode[0x10];
5020         u8         reserved_at_10[0x10];
5021
5022         u8         reserved_at_20[0x10];
5023         u8         op_mod[0x10];
5024
5025         u8         rq_state[0x4];
5026         u8         reserved_at_44[0x4];
5027         u8         rqn[0x18];
5028
5029         u8         reserved_at_60[0x20];
5030
5031         u8         modify_bitmask[0x40];
5032
5033         u8         reserved_at_c0[0x40];
5034
5035         struct mlx5_ifc_rqc_bits ctx;
5036 };
5037
5038 struct mlx5_ifc_modify_rmp_out_bits {
5039         u8         status[0x8];
5040         u8         reserved_at_8[0x18];
5041
5042         u8         syndrome[0x20];
5043
5044         u8         reserved_at_40[0x40];
5045 };
5046
5047 struct mlx5_ifc_rmp_bitmask_bits {
5048         u8         reserved_at_0[0x20];
5049
5050         u8         reserved_at_20[0x1f];
5051         u8         lwm[0x1];
5052 };
5053
5054 struct mlx5_ifc_modify_rmp_in_bits {
5055         u8         opcode[0x10];
5056         u8         reserved_at_10[0x10];
5057
5058         u8         reserved_at_20[0x10];
5059         u8         op_mod[0x10];
5060
5061         u8         rmp_state[0x4];
5062         u8         reserved_at_44[0x4];
5063         u8         rmpn[0x18];
5064
5065         u8         reserved_at_60[0x20];
5066
5067         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5068
5069         u8         reserved_at_c0[0x40];
5070
5071         struct mlx5_ifc_rmpc_bits ctx;
5072 };
5073
5074 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5075         u8         status[0x8];
5076         u8         reserved_at_8[0x18];
5077
5078         u8         syndrome[0x20];
5079
5080         u8         reserved_at_40[0x40];
5081 };
5082
5083 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5084         u8         reserved_at_0[0x16];
5085         u8         node_guid[0x1];
5086         u8         port_guid[0x1];
5087         u8         min_inline[0x1];
5088         u8         mtu[0x1];
5089         u8         change_event[0x1];
5090         u8         promisc[0x1];
5091         u8         permanent_address[0x1];
5092         u8         addresses_list[0x1];
5093         u8         roce_en[0x1];
5094         u8         reserved_at_1f[0x1];
5095 };
5096
5097 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5098         u8         opcode[0x10];
5099         u8         reserved_at_10[0x10];
5100
5101         u8         reserved_at_20[0x10];
5102         u8         op_mod[0x10];
5103
5104         u8         other_vport[0x1];
5105         u8         reserved_at_41[0xf];
5106         u8         vport_number[0x10];
5107
5108         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5109
5110         u8         reserved_at_80[0x780];
5111
5112         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5113 };
5114
5115 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5116         u8         status[0x8];
5117         u8         reserved_at_8[0x18];
5118
5119         u8         syndrome[0x20];
5120
5121         u8         reserved_at_40[0x40];
5122 };
5123
5124 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5125         u8         opcode[0x10];
5126         u8         reserved_at_10[0x10];
5127
5128         u8         reserved_at_20[0x10];
5129         u8         op_mod[0x10];
5130
5131         u8         other_vport[0x1];
5132         u8         reserved_at_41[0xb];
5133         u8         port_num[0x4];
5134         u8         vport_number[0x10];
5135
5136         u8         reserved_at_60[0x20];
5137
5138         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5139 };
5140
5141 struct mlx5_ifc_modify_cq_out_bits {
5142         u8         status[0x8];
5143         u8         reserved_at_8[0x18];
5144
5145         u8         syndrome[0x20];
5146
5147         u8         reserved_at_40[0x40];
5148 };
5149
5150 enum {
5151         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5152         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5153 };
5154
5155 struct mlx5_ifc_modify_cq_in_bits {
5156         u8         opcode[0x10];
5157         u8         reserved_at_10[0x10];
5158
5159         u8         reserved_at_20[0x10];
5160         u8         op_mod[0x10];
5161
5162         u8         reserved_at_40[0x8];
5163         u8         cqn[0x18];
5164
5165         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5166
5167         struct mlx5_ifc_cqc_bits cq_context;
5168
5169         u8         reserved_at_280[0x600];
5170
5171         u8         pas[0][0x40];
5172 };
5173
5174 struct mlx5_ifc_modify_cong_status_out_bits {
5175         u8         status[0x8];
5176         u8         reserved_at_8[0x18];
5177
5178         u8         syndrome[0x20];
5179
5180         u8         reserved_at_40[0x40];
5181 };
5182
5183 struct mlx5_ifc_modify_cong_status_in_bits {
5184         u8         opcode[0x10];
5185         u8         reserved_at_10[0x10];
5186
5187         u8         reserved_at_20[0x10];
5188         u8         op_mod[0x10];
5189
5190         u8         reserved_at_40[0x18];
5191         u8         priority[0x4];
5192         u8         cong_protocol[0x4];
5193
5194         u8         enable[0x1];
5195         u8         tag_enable[0x1];
5196         u8         reserved_at_62[0x1e];
5197 };
5198
5199 struct mlx5_ifc_modify_cong_params_out_bits {
5200         u8         status[0x8];
5201         u8         reserved_at_8[0x18];
5202
5203         u8         syndrome[0x20];
5204
5205         u8         reserved_at_40[0x40];
5206 };
5207
5208 struct mlx5_ifc_modify_cong_params_in_bits {
5209         u8         opcode[0x10];
5210         u8         reserved_at_10[0x10];
5211
5212         u8         reserved_at_20[0x10];
5213         u8         op_mod[0x10];
5214
5215         u8         reserved_at_40[0x1c];
5216         u8         cong_protocol[0x4];
5217
5218         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5219
5220         u8         reserved_at_80[0x80];
5221
5222         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5223 };
5224
5225 struct mlx5_ifc_manage_pages_out_bits {
5226         u8         status[0x8];
5227         u8         reserved_at_8[0x18];
5228
5229         u8         syndrome[0x20];
5230
5231         u8         output_num_entries[0x20];
5232
5233         u8         reserved_at_60[0x20];
5234
5235         u8         pas[0][0x40];
5236 };
5237
5238 enum {
5239         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5240         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5241         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5242 };
5243
5244 struct mlx5_ifc_manage_pages_in_bits {
5245         u8         opcode[0x10];
5246         u8         reserved_at_10[0x10];
5247
5248         u8         reserved_at_20[0x10];
5249         u8         op_mod[0x10];
5250
5251         u8         reserved_at_40[0x10];
5252         u8         function_id[0x10];
5253
5254         u8         input_num_entries[0x20];
5255
5256         u8         pas[0][0x40];
5257 };
5258
5259 struct mlx5_ifc_mad_ifc_out_bits {
5260         u8         status[0x8];
5261         u8         reserved_at_8[0x18];
5262
5263         u8         syndrome[0x20];
5264
5265         u8         reserved_at_40[0x40];
5266
5267         u8         response_mad_packet[256][0x8];
5268 };
5269
5270 struct mlx5_ifc_mad_ifc_in_bits {
5271         u8         opcode[0x10];
5272         u8         reserved_at_10[0x10];
5273
5274         u8         reserved_at_20[0x10];
5275         u8         op_mod[0x10];
5276
5277         u8         remote_lid[0x10];
5278         u8         reserved_at_50[0x8];
5279         u8         port[0x8];
5280
5281         u8         reserved_at_60[0x20];
5282
5283         u8         mad[256][0x8];
5284 };
5285
5286 struct mlx5_ifc_init_hca_out_bits {
5287         u8         status[0x8];
5288         u8         reserved_at_8[0x18];
5289
5290         u8         syndrome[0x20];
5291
5292         u8         reserved_at_40[0x40];
5293 };
5294
5295 struct mlx5_ifc_init_hca_in_bits {
5296         u8         opcode[0x10];
5297         u8         reserved_at_10[0x10];
5298
5299         u8         reserved_at_20[0x10];
5300         u8         op_mod[0x10];
5301
5302         u8         reserved_at_40[0x40];
5303 };
5304
5305 struct mlx5_ifc_init2rtr_qp_out_bits {
5306         u8         status[0x8];
5307         u8         reserved_at_8[0x18];
5308
5309         u8         syndrome[0x20];
5310
5311         u8         reserved_at_40[0x40];
5312 };
5313
5314 struct mlx5_ifc_init2rtr_qp_in_bits {
5315         u8         opcode[0x10];
5316         u8         reserved_at_10[0x10];
5317
5318         u8         reserved_at_20[0x10];
5319         u8         op_mod[0x10];
5320
5321         u8         reserved_at_40[0x8];
5322         u8         qpn[0x18];
5323
5324         u8         reserved_at_60[0x20];
5325
5326         u8         opt_param_mask[0x20];
5327
5328         u8         reserved_at_a0[0x20];
5329
5330         struct mlx5_ifc_qpc_bits qpc;
5331
5332         u8         reserved_at_800[0x80];
5333 };
5334
5335 struct mlx5_ifc_init2init_qp_out_bits {
5336         u8         status[0x8];
5337         u8         reserved_at_8[0x18];
5338
5339         u8         syndrome[0x20];
5340
5341         u8         reserved_at_40[0x40];
5342 };
5343
5344 struct mlx5_ifc_init2init_qp_in_bits {
5345         u8         opcode[0x10];
5346         u8         reserved_at_10[0x10];
5347
5348         u8         reserved_at_20[0x10];
5349         u8         op_mod[0x10];
5350
5351         u8         reserved_at_40[0x8];
5352         u8         qpn[0x18];
5353
5354         u8         reserved_at_60[0x20];
5355
5356         u8         opt_param_mask[0x20];
5357
5358         u8         reserved_at_a0[0x20];
5359
5360         struct mlx5_ifc_qpc_bits qpc;
5361
5362         u8         reserved_at_800[0x80];
5363 };
5364
5365 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5366         u8         status[0x8];
5367         u8         reserved_at_8[0x18];
5368
5369         u8         syndrome[0x20];
5370
5371         u8         reserved_at_40[0x40];
5372
5373         u8         packet_headers_log[128][0x8];
5374
5375         u8         packet_syndrome[64][0x8];
5376 };
5377
5378 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5379         u8         opcode[0x10];
5380         u8         reserved_at_10[0x10];
5381
5382         u8         reserved_at_20[0x10];
5383         u8         op_mod[0x10];
5384
5385         u8         reserved_at_40[0x40];
5386 };
5387
5388 struct mlx5_ifc_gen_eqe_in_bits {
5389         u8         opcode[0x10];
5390         u8         reserved_at_10[0x10];
5391
5392         u8         reserved_at_20[0x10];
5393         u8         op_mod[0x10];
5394
5395         u8         reserved_at_40[0x18];
5396         u8         eq_number[0x8];
5397
5398         u8         reserved_at_60[0x20];
5399
5400         u8         eqe[64][0x8];
5401 };
5402
5403 struct mlx5_ifc_gen_eq_out_bits {
5404         u8         status[0x8];
5405         u8         reserved_at_8[0x18];
5406
5407         u8         syndrome[0x20];
5408
5409         u8         reserved_at_40[0x40];
5410 };
5411
5412 struct mlx5_ifc_enable_hca_out_bits {
5413         u8         status[0x8];
5414         u8         reserved_at_8[0x18];
5415
5416         u8         syndrome[0x20];
5417
5418         u8         reserved_at_40[0x20];
5419 };
5420
5421 struct mlx5_ifc_enable_hca_in_bits {
5422         u8         opcode[0x10];
5423         u8         reserved_at_10[0x10];
5424
5425         u8         reserved_at_20[0x10];
5426         u8         op_mod[0x10];
5427
5428         u8         reserved_at_40[0x10];
5429         u8         function_id[0x10];
5430
5431         u8         reserved_at_60[0x20];
5432 };
5433
5434 struct mlx5_ifc_drain_dct_out_bits {
5435         u8         status[0x8];
5436         u8         reserved_at_8[0x18];
5437
5438         u8         syndrome[0x20];
5439
5440         u8         reserved_at_40[0x40];
5441 };
5442
5443 struct mlx5_ifc_drain_dct_in_bits {
5444         u8         opcode[0x10];
5445         u8         reserved_at_10[0x10];
5446
5447         u8         reserved_at_20[0x10];
5448         u8         op_mod[0x10];
5449
5450         u8         reserved_at_40[0x8];
5451         u8         dctn[0x18];
5452
5453         u8         reserved_at_60[0x20];
5454 };
5455
5456 struct mlx5_ifc_disable_hca_out_bits {
5457         u8         status[0x8];
5458         u8         reserved_at_8[0x18];
5459
5460         u8         syndrome[0x20];
5461
5462         u8         reserved_at_40[0x20];
5463 };
5464
5465 struct mlx5_ifc_disable_hca_in_bits {
5466         u8         opcode[0x10];
5467         u8         reserved_at_10[0x10];
5468
5469         u8         reserved_at_20[0x10];
5470         u8         op_mod[0x10];
5471
5472         u8         reserved_at_40[0x10];
5473         u8         function_id[0x10];
5474
5475         u8         reserved_at_60[0x20];
5476 };
5477
5478 struct mlx5_ifc_detach_from_mcg_out_bits {
5479         u8         status[0x8];
5480         u8         reserved_at_8[0x18];
5481
5482         u8         syndrome[0x20];
5483
5484         u8         reserved_at_40[0x40];
5485 };
5486
5487 struct mlx5_ifc_detach_from_mcg_in_bits {
5488         u8         opcode[0x10];
5489         u8         reserved_at_10[0x10];
5490
5491         u8         reserved_at_20[0x10];
5492         u8         op_mod[0x10];
5493
5494         u8         reserved_at_40[0x8];
5495         u8         qpn[0x18];
5496
5497         u8         reserved_at_60[0x20];
5498
5499         u8         multicast_gid[16][0x8];
5500 };
5501
5502 struct mlx5_ifc_destroy_xrq_out_bits {
5503         u8         status[0x8];
5504         u8         reserved_at_8[0x18];
5505
5506         u8         syndrome[0x20];
5507
5508         u8         reserved_at_40[0x40];
5509 };
5510
5511 struct mlx5_ifc_destroy_xrq_in_bits {
5512         u8         opcode[0x10];
5513         u8         reserved_at_10[0x10];
5514
5515         u8         reserved_at_20[0x10];
5516         u8         op_mod[0x10];
5517
5518         u8         reserved_at_40[0x8];
5519         u8         xrqn[0x18];
5520
5521         u8         reserved_at_60[0x20];
5522 };
5523
5524 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5525         u8         status[0x8];
5526         u8         reserved_at_8[0x18];
5527
5528         u8         syndrome[0x20];
5529
5530         u8         reserved_at_40[0x40];
5531 };
5532
5533 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5534         u8         opcode[0x10];
5535         u8         reserved_at_10[0x10];
5536
5537         u8         reserved_at_20[0x10];
5538         u8         op_mod[0x10];
5539
5540         u8         reserved_at_40[0x8];
5541         u8         xrc_srqn[0x18];
5542
5543         u8         reserved_at_60[0x20];
5544 };
5545
5546 struct mlx5_ifc_destroy_tis_out_bits {
5547         u8         status[0x8];
5548         u8         reserved_at_8[0x18];
5549
5550         u8         syndrome[0x20];
5551
5552         u8         reserved_at_40[0x40];
5553 };
5554
5555 struct mlx5_ifc_destroy_tis_in_bits {
5556         u8         opcode[0x10];
5557         u8         reserved_at_10[0x10];
5558
5559         u8         reserved_at_20[0x10];
5560         u8         op_mod[0x10];
5561
5562         u8         reserved_at_40[0x8];
5563         u8         tisn[0x18];
5564
5565         u8         reserved_at_60[0x20];
5566 };
5567
5568 struct mlx5_ifc_destroy_tir_out_bits {
5569         u8         status[0x8];
5570         u8         reserved_at_8[0x18];
5571
5572         u8         syndrome[0x20];
5573
5574         u8         reserved_at_40[0x40];
5575 };
5576
5577 struct mlx5_ifc_destroy_tir_in_bits {
5578         u8         opcode[0x10];
5579         u8         reserved_at_10[0x10];
5580
5581         u8         reserved_at_20[0x10];
5582         u8         op_mod[0x10];
5583
5584         u8         reserved_at_40[0x8];
5585         u8         tirn[0x18];
5586
5587         u8         reserved_at_60[0x20];
5588 };
5589
5590 struct mlx5_ifc_destroy_srq_out_bits {
5591         u8         status[0x8];
5592         u8         reserved_at_8[0x18];
5593
5594         u8         syndrome[0x20];
5595
5596         u8         reserved_at_40[0x40];
5597 };
5598
5599 struct mlx5_ifc_destroy_srq_in_bits {
5600         u8         opcode[0x10];
5601         u8         reserved_at_10[0x10];
5602
5603         u8         reserved_at_20[0x10];
5604         u8         op_mod[0x10];
5605
5606         u8         reserved_at_40[0x8];
5607         u8         srqn[0x18];
5608
5609         u8         reserved_at_60[0x20];
5610 };
5611
5612 struct mlx5_ifc_destroy_sq_out_bits {
5613         u8         status[0x8];
5614         u8         reserved_at_8[0x18];
5615
5616         u8         syndrome[0x20];
5617
5618         u8         reserved_at_40[0x40];
5619 };
5620
5621 struct mlx5_ifc_destroy_sq_in_bits {
5622         u8         opcode[0x10];
5623         u8         reserved_at_10[0x10];
5624
5625         u8         reserved_at_20[0x10];
5626         u8         op_mod[0x10];
5627
5628         u8         reserved_at_40[0x8];
5629         u8         sqn[0x18];
5630
5631         u8         reserved_at_60[0x20];
5632 };
5633
5634 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5635         u8         status[0x8];
5636         u8         reserved_at_8[0x18];
5637
5638         u8         syndrome[0x20];
5639
5640         u8         reserved_at_40[0x1c0];
5641 };
5642
5643 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5644         u8         opcode[0x10];
5645         u8         reserved_at_10[0x10];
5646
5647         u8         reserved_at_20[0x10];
5648         u8         op_mod[0x10];
5649
5650         u8         scheduling_hierarchy[0x8];
5651         u8         reserved_at_48[0x18];
5652
5653         u8         scheduling_element_id[0x20];
5654
5655         u8         reserved_at_80[0x180];
5656 };
5657
5658 struct mlx5_ifc_destroy_rqt_out_bits {
5659         u8         status[0x8];
5660         u8         reserved_at_8[0x18];
5661
5662         u8         syndrome[0x20];
5663
5664         u8         reserved_at_40[0x40];
5665 };
5666
5667 struct mlx5_ifc_destroy_rqt_in_bits {
5668         u8         opcode[0x10];
5669         u8         reserved_at_10[0x10];
5670
5671         u8         reserved_at_20[0x10];
5672         u8         op_mod[0x10];
5673
5674         u8         reserved_at_40[0x8];
5675         u8         rqtn[0x18];
5676
5677         u8         reserved_at_60[0x20];
5678 };
5679
5680 struct mlx5_ifc_destroy_rq_out_bits {
5681         u8         status[0x8];
5682         u8         reserved_at_8[0x18];
5683
5684         u8         syndrome[0x20];
5685
5686         u8         reserved_at_40[0x40];
5687 };
5688
5689 struct mlx5_ifc_destroy_rq_in_bits {
5690         u8         opcode[0x10];
5691         u8         reserved_at_10[0x10];
5692
5693         u8         reserved_at_20[0x10];
5694         u8         op_mod[0x10];
5695
5696         u8         reserved_at_40[0x8];
5697         u8         rqn[0x18];
5698
5699         u8         reserved_at_60[0x20];
5700 };
5701
5702 struct mlx5_ifc_destroy_rmp_out_bits {
5703         u8         status[0x8];
5704         u8         reserved_at_8[0x18];
5705
5706         u8         syndrome[0x20];
5707
5708         u8         reserved_at_40[0x40];
5709 };
5710
5711 struct mlx5_ifc_destroy_rmp_in_bits {
5712         u8         opcode[0x10];
5713         u8         reserved_at_10[0x10];
5714
5715         u8         reserved_at_20[0x10];
5716         u8         op_mod[0x10];
5717
5718         u8         reserved_at_40[0x8];
5719         u8         rmpn[0x18];
5720
5721         u8         reserved_at_60[0x20];
5722 };
5723
5724 struct mlx5_ifc_destroy_qp_out_bits {
5725         u8         status[0x8];
5726         u8         reserved_at_8[0x18];
5727
5728         u8         syndrome[0x20];
5729
5730         u8         reserved_at_40[0x40];
5731 };
5732
5733 struct mlx5_ifc_destroy_qp_in_bits {
5734         u8         opcode[0x10];
5735         u8         reserved_at_10[0x10];
5736
5737         u8         reserved_at_20[0x10];
5738         u8         op_mod[0x10];
5739
5740         u8         reserved_at_40[0x8];
5741         u8         qpn[0x18];
5742
5743         u8         reserved_at_60[0x20];
5744 };
5745
5746 struct mlx5_ifc_destroy_psv_out_bits {
5747         u8         status[0x8];
5748         u8         reserved_at_8[0x18];
5749
5750         u8         syndrome[0x20];
5751
5752         u8         reserved_at_40[0x40];
5753 };
5754
5755 struct mlx5_ifc_destroy_psv_in_bits {
5756         u8         opcode[0x10];
5757         u8         reserved_at_10[0x10];
5758
5759         u8         reserved_at_20[0x10];
5760         u8         op_mod[0x10];
5761
5762         u8         reserved_at_40[0x8];
5763         u8         psvn[0x18];
5764
5765         u8         reserved_at_60[0x20];
5766 };
5767
5768 struct mlx5_ifc_destroy_mkey_out_bits {
5769         u8         status[0x8];
5770         u8         reserved_at_8[0x18];
5771
5772         u8         syndrome[0x20];
5773
5774         u8         reserved_at_40[0x40];
5775 };
5776
5777 struct mlx5_ifc_destroy_mkey_in_bits {
5778         u8         opcode[0x10];
5779         u8         reserved_at_10[0x10];
5780
5781         u8         reserved_at_20[0x10];
5782         u8         op_mod[0x10];
5783
5784         u8         reserved_at_40[0x8];
5785         u8         mkey_index[0x18];
5786
5787         u8         reserved_at_60[0x20];
5788 };
5789
5790 struct mlx5_ifc_destroy_flow_table_out_bits {
5791         u8         status[0x8];
5792         u8         reserved_at_8[0x18];
5793
5794         u8         syndrome[0x20];
5795
5796         u8         reserved_at_40[0x40];
5797 };
5798
5799 struct mlx5_ifc_destroy_flow_table_in_bits {
5800         u8         opcode[0x10];
5801         u8         reserved_at_10[0x10];
5802
5803         u8         reserved_at_20[0x10];
5804         u8         op_mod[0x10];
5805
5806         u8         other_vport[0x1];
5807         u8         reserved_at_41[0xf];
5808         u8         vport_number[0x10];
5809
5810         u8         reserved_at_60[0x20];
5811
5812         u8         table_type[0x8];
5813         u8         reserved_at_88[0x18];
5814
5815         u8         reserved_at_a0[0x8];
5816         u8         table_id[0x18];
5817
5818         u8         reserved_at_c0[0x140];
5819 };
5820
5821 struct mlx5_ifc_destroy_flow_group_out_bits {
5822         u8         status[0x8];
5823         u8         reserved_at_8[0x18];
5824
5825         u8         syndrome[0x20];
5826
5827         u8         reserved_at_40[0x40];
5828 };
5829
5830 struct mlx5_ifc_destroy_flow_group_in_bits {
5831         u8         opcode[0x10];
5832         u8         reserved_at_10[0x10];
5833
5834         u8         reserved_at_20[0x10];
5835         u8         op_mod[0x10];
5836
5837         u8         other_vport[0x1];
5838         u8         reserved_at_41[0xf];
5839         u8         vport_number[0x10];
5840
5841         u8         reserved_at_60[0x20];
5842
5843         u8         table_type[0x8];
5844         u8         reserved_at_88[0x18];
5845
5846         u8         reserved_at_a0[0x8];
5847         u8         table_id[0x18];
5848
5849         u8         group_id[0x20];
5850
5851         u8         reserved_at_e0[0x120];
5852 };
5853
5854 struct mlx5_ifc_destroy_eq_out_bits {
5855         u8         status[0x8];
5856         u8         reserved_at_8[0x18];
5857
5858         u8         syndrome[0x20];
5859
5860         u8         reserved_at_40[0x40];
5861 };
5862
5863 struct mlx5_ifc_destroy_eq_in_bits {
5864         u8         opcode[0x10];
5865         u8         reserved_at_10[0x10];
5866
5867         u8         reserved_at_20[0x10];
5868         u8         op_mod[0x10];
5869
5870         u8         reserved_at_40[0x18];
5871         u8         eq_number[0x8];
5872
5873         u8         reserved_at_60[0x20];
5874 };
5875
5876 struct mlx5_ifc_destroy_dct_out_bits {
5877         u8         status[0x8];
5878         u8         reserved_at_8[0x18];
5879
5880         u8         syndrome[0x20];
5881
5882         u8         reserved_at_40[0x40];
5883 };
5884
5885 struct mlx5_ifc_destroy_dct_in_bits {
5886         u8         opcode[0x10];
5887         u8         reserved_at_10[0x10];
5888
5889         u8         reserved_at_20[0x10];
5890         u8         op_mod[0x10];
5891
5892         u8         reserved_at_40[0x8];
5893         u8         dctn[0x18];
5894
5895         u8         reserved_at_60[0x20];
5896 };
5897
5898 struct mlx5_ifc_destroy_cq_out_bits {
5899         u8         status[0x8];
5900         u8         reserved_at_8[0x18];
5901
5902         u8         syndrome[0x20];
5903
5904         u8         reserved_at_40[0x40];
5905 };
5906
5907 struct mlx5_ifc_destroy_cq_in_bits {
5908         u8         opcode[0x10];
5909         u8         reserved_at_10[0x10];
5910
5911         u8         reserved_at_20[0x10];
5912         u8         op_mod[0x10];
5913
5914         u8         reserved_at_40[0x8];
5915         u8         cqn[0x18];
5916
5917         u8         reserved_at_60[0x20];
5918 };
5919
5920 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5921         u8         status[0x8];
5922         u8         reserved_at_8[0x18];
5923
5924         u8         syndrome[0x20];
5925
5926         u8         reserved_at_40[0x40];
5927 };
5928
5929 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5930         u8         opcode[0x10];
5931         u8         reserved_at_10[0x10];
5932
5933         u8         reserved_at_20[0x10];
5934         u8         op_mod[0x10];
5935
5936         u8         reserved_at_40[0x20];
5937
5938         u8         reserved_at_60[0x10];
5939         u8         vxlan_udp_port[0x10];
5940 };
5941
5942 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5943         u8         status[0x8];
5944         u8         reserved_at_8[0x18];
5945
5946         u8         syndrome[0x20];
5947
5948         u8         reserved_at_40[0x40];
5949 };
5950
5951 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5952         u8         opcode[0x10];
5953         u8         reserved_at_10[0x10];
5954
5955         u8         reserved_at_20[0x10];
5956         u8         op_mod[0x10];
5957
5958         u8         reserved_at_40[0x60];
5959
5960         u8         reserved_at_a0[0x8];
5961         u8         table_index[0x18];
5962
5963         u8         reserved_at_c0[0x140];
5964 };
5965
5966 struct mlx5_ifc_delete_fte_out_bits {
5967         u8         status[0x8];
5968         u8         reserved_at_8[0x18];
5969
5970         u8         syndrome[0x20];
5971
5972         u8         reserved_at_40[0x40];
5973 };
5974
5975 struct mlx5_ifc_delete_fte_in_bits {
5976         u8         opcode[0x10];
5977         u8         reserved_at_10[0x10];
5978
5979         u8         reserved_at_20[0x10];
5980         u8         op_mod[0x10];
5981
5982         u8         other_vport[0x1];
5983         u8         reserved_at_41[0xf];
5984         u8         vport_number[0x10];
5985
5986         u8         reserved_at_60[0x20];
5987
5988         u8         table_type[0x8];
5989         u8         reserved_at_88[0x18];
5990
5991         u8         reserved_at_a0[0x8];
5992         u8         table_id[0x18];
5993
5994         u8         reserved_at_c0[0x40];
5995
5996         u8         flow_index[0x20];
5997
5998         u8         reserved_at_120[0xe0];
5999 };
6000
6001 struct mlx5_ifc_dealloc_xrcd_out_bits {
6002         u8         status[0x8];
6003         u8         reserved_at_8[0x18];
6004
6005         u8         syndrome[0x20];
6006
6007         u8         reserved_at_40[0x40];
6008 };
6009
6010 struct mlx5_ifc_dealloc_xrcd_in_bits {
6011         u8         opcode[0x10];
6012         u8         reserved_at_10[0x10];
6013
6014         u8         reserved_at_20[0x10];
6015         u8         op_mod[0x10];
6016
6017         u8         reserved_at_40[0x8];
6018         u8         xrcd[0x18];
6019
6020         u8         reserved_at_60[0x20];
6021 };
6022
6023 struct mlx5_ifc_dealloc_uar_out_bits {
6024         u8         status[0x8];
6025         u8         reserved_at_8[0x18];
6026
6027         u8         syndrome[0x20];
6028
6029         u8         reserved_at_40[0x40];
6030 };
6031
6032 struct mlx5_ifc_dealloc_uar_in_bits {
6033         u8         opcode[0x10];
6034         u8         reserved_at_10[0x10];
6035
6036         u8         reserved_at_20[0x10];
6037         u8         op_mod[0x10];
6038
6039         u8         reserved_at_40[0x8];
6040         u8         uar[0x18];
6041
6042         u8         reserved_at_60[0x20];
6043 };
6044
6045 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6046         u8         status[0x8];
6047         u8         reserved_at_8[0x18];
6048
6049         u8         syndrome[0x20];
6050
6051         u8         reserved_at_40[0x40];
6052 };
6053
6054 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6055         u8         opcode[0x10];
6056         u8         reserved_at_10[0x10];
6057
6058         u8         reserved_at_20[0x10];
6059         u8         op_mod[0x10];
6060
6061         u8         reserved_at_40[0x8];
6062         u8         transport_domain[0x18];
6063
6064         u8         reserved_at_60[0x20];
6065 };
6066
6067 struct mlx5_ifc_dealloc_q_counter_out_bits {
6068         u8         status[0x8];
6069         u8         reserved_at_8[0x18];
6070
6071         u8         syndrome[0x20];
6072
6073         u8         reserved_at_40[0x40];
6074 };
6075
6076 struct mlx5_ifc_dealloc_q_counter_in_bits {
6077         u8         opcode[0x10];
6078         u8         reserved_at_10[0x10];
6079
6080         u8         reserved_at_20[0x10];
6081         u8         op_mod[0x10];
6082
6083         u8         reserved_at_40[0x18];
6084         u8         counter_set_id[0x8];
6085
6086         u8         reserved_at_60[0x20];
6087 };
6088
6089 struct mlx5_ifc_dealloc_pd_out_bits {
6090         u8         status[0x8];
6091         u8         reserved_at_8[0x18];
6092
6093         u8         syndrome[0x20];
6094
6095         u8         reserved_at_40[0x40];
6096 };
6097
6098 struct mlx5_ifc_dealloc_pd_in_bits {
6099         u8         opcode[0x10];
6100         u8         reserved_at_10[0x10];
6101
6102         u8         reserved_at_20[0x10];
6103         u8         op_mod[0x10];
6104
6105         u8         reserved_at_40[0x8];
6106         u8         pd[0x18];
6107
6108         u8         reserved_at_60[0x20];
6109 };
6110
6111 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6112         u8         status[0x8];
6113         u8         reserved_at_8[0x18];
6114
6115         u8         syndrome[0x20];
6116
6117         u8         reserved_at_40[0x40];
6118 };
6119
6120 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6121         u8         opcode[0x10];
6122         u8         reserved_at_10[0x10];
6123
6124         u8         reserved_at_20[0x10];
6125         u8         op_mod[0x10];
6126
6127         u8         reserved_at_40[0x10];
6128         u8         flow_counter_id[0x10];
6129
6130         u8         reserved_at_60[0x20];
6131 };
6132
6133 struct mlx5_ifc_create_xrq_out_bits {
6134         u8         status[0x8];
6135         u8         reserved_at_8[0x18];
6136
6137         u8         syndrome[0x20];
6138
6139         u8         reserved_at_40[0x8];
6140         u8         xrqn[0x18];
6141
6142         u8         reserved_at_60[0x20];
6143 };
6144
6145 struct mlx5_ifc_create_xrq_in_bits {
6146         u8         opcode[0x10];
6147         u8         reserved_at_10[0x10];
6148
6149         u8         reserved_at_20[0x10];
6150         u8         op_mod[0x10];
6151
6152         u8         reserved_at_40[0x40];
6153
6154         struct mlx5_ifc_xrqc_bits xrq_context;
6155 };
6156
6157 struct mlx5_ifc_create_xrc_srq_out_bits {
6158         u8         status[0x8];
6159         u8         reserved_at_8[0x18];
6160
6161         u8         syndrome[0x20];
6162
6163         u8         reserved_at_40[0x8];
6164         u8         xrc_srqn[0x18];
6165
6166         u8         reserved_at_60[0x20];
6167 };
6168
6169 struct mlx5_ifc_create_xrc_srq_in_bits {
6170         u8         opcode[0x10];
6171         u8         reserved_at_10[0x10];
6172
6173         u8         reserved_at_20[0x10];
6174         u8         op_mod[0x10];
6175
6176         u8         reserved_at_40[0x40];
6177
6178         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6179
6180         u8         reserved_at_280[0x600];
6181
6182         u8         pas[0][0x40];
6183 };
6184
6185 struct mlx5_ifc_create_tis_out_bits {
6186         u8         status[0x8];
6187         u8         reserved_at_8[0x18];
6188
6189         u8         syndrome[0x20];
6190
6191         u8         reserved_at_40[0x8];
6192         u8         tisn[0x18];
6193
6194         u8         reserved_at_60[0x20];
6195 };
6196
6197 struct mlx5_ifc_create_tis_in_bits {
6198         u8         opcode[0x10];
6199         u8         reserved_at_10[0x10];
6200
6201         u8         reserved_at_20[0x10];
6202         u8         op_mod[0x10];
6203
6204         u8         reserved_at_40[0xc0];
6205
6206         struct mlx5_ifc_tisc_bits ctx;
6207 };
6208
6209 struct mlx5_ifc_create_tir_out_bits {
6210         u8         status[0x8];
6211         u8         reserved_at_8[0x18];
6212
6213         u8         syndrome[0x20];
6214
6215         u8         reserved_at_40[0x8];
6216         u8         tirn[0x18];
6217
6218         u8         reserved_at_60[0x20];
6219 };
6220
6221 struct mlx5_ifc_create_tir_in_bits {
6222         u8         opcode[0x10];
6223         u8         reserved_at_10[0x10];
6224
6225         u8         reserved_at_20[0x10];
6226         u8         op_mod[0x10];
6227
6228         u8         reserved_at_40[0xc0];
6229
6230         struct mlx5_ifc_tirc_bits ctx;
6231 };
6232
6233 struct mlx5_ifc_create_srq_out_bits {
6234         u8         status[0x8];
6235         u8         reserved_at_8[0x18];
6236
6237         u8         syndrome[0x20];
6238
6239         u8         reserved_at_40[0x8];
6240         u8         srqn[0x18];
6241
6242         u8         reserved_at_60[0x20];
6243 };
6244
6245 struct mlx5_ifc_create_srq_in_bits {
6246         u8         opcode[0x10];
6247         u8         reserved_at_10[0x10];
6248
6249         u8         reserved_at_20[0x10];
6250         u8         op_mod[0x10];
6251
6252         u8         reserved_at_40[0x40];
6253
6254         struct mlx5_ifc_srqc_bits srq_context_entry;
6255
6256         u8         reserved_at_280[0x600];
6257
6258         u8         pas[0][0x40];
6259 };
6260
6261 struct mlx5_ifc_create_sq_out_bits {
6262         u8         status[0x8];
6263         u8         reserved_at_8[0x18];
6264
6265         u8         syndrome[0x20];
6266
6267         u8         reserved_at_40[0x8];
6268         u8         sqn[0x18];
6269
6270         u8         reserved_at_60[0x20];
6271 };
6272
6273 struct mlx5_ifc_create_sq_in_bits {
6274         u8         opcode[0x10];
6275         u8         reserved_at_10[0x10];
6276
6277         u8         reserved_at_20[0x10];
6278         u8         op_mod[0x10];
6279
6280         u8         reserved_at_40[0xc0];
6281
6282         struct mlx5_ifc_sqc_bits ctx;
6283 };
6284
6285 struct mlx5_ifc_create_scheduling_element_out_bits {
6286         u8         status[0x8];
6287         u8         reserved_at_8[0x18];
6288
6289         u8         syndrome[0x20];
6290
6291         u8         reserved_at_40[0x40];
6292
6293         u8         scheduling_element_id[0x20];
6294
6295         u8         reserved_at_a0[0x160];
6296 };
6297
6298 struct mlx5_ifc_create_scheduling_element_in_bits {
6299         u8         opcode[0x10];
6300         u8         reserved_at_10[0x10];
6301
6302         u8         reserved_at_20[0x10];
6303         u8         op_mod[0x10];
6304
6305         u8         scheduling_hierarchy[0x8];
6306         u8         reserved_at_48[0x18];
6307
6308         u8         reserved_at_60[0xa0];
6309
6310         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6311
6312         u8         reserved_at_300[0x100];
6313 };
6314
6315 struct mlx5_ifc_create_rqt_out_bits {
6316         u8         status[0x8];
6317         u8         reserved_at_8[0x18];
6318
6319         u8         syndrome[0x20];
6320
6321         u8         reserved_at_40[0x8];
6322         u8         rqtn[0x18];
6323
6324         u8         reserved_at_60[0x20];
6325 };
6326
6327 struct mlx5_ifc_create_rqt_in_bits {
6328         u8         opcode[0x10];
6329         u8         reserved_at_10[0x10];
6330
6331         u8         reserved_at_20[0x10];
6332         u8         op_mod[0x10];
6333
6334         u8         reserved_at_40[0xc0];
6335
6336         struct mlx5_ifc_rqtc_bits rqt_context;
6337 };
6338
6339 struct mlx5_ifc_create_rq_out_bits {
6340         u8         status[0x8];
6341         u8         reserved_at_8[0x18];
6342
6343         u8         syndrome[0x20];
6344
6345         u8         reserved_at_40[0x8];
6346         u8         rqn[0x18];
6347
6348         u8         reserved_at_60[0x20];
6349 };
6350
6351 struct mlx5_ifc_create_rq_in_bits {
6352         u8         opcode[0x10];
6353         u8         reserved_at_10[0x10];
6354
6355         u8         reserved_at_20[0x10];
6356         u8         op_mod[0x10];
6357
6358         u8         reserved_at_40[0xc0];
6359
6360         struct mlx5_ifc_rqc_bits ctx;
6361 };
6362
6363 struct mlx5_ifc_create_rmp_out_bits {
6364         u8         status[0x8];
6365         u8         reserved_at_8[0x18];
6366
6367         u8         syndrome[0x20];
6368
6369         u8         reserved_at_40[0x8];
6370         u8         rmpn[0x18];
6371
6372         u8         reserved_at_60[0x20];
6373 };
6374
6375 struct mlx5_ifc_create_rmp_in_bits {
6376         u8         opcode[0x10];
6377         u8         reserved_at_10[0x10];
6378
6379         u8         reserved_at_20[0x10];
6380         u8         op_mod[0x10];
6381
6382         u8         reserved_at_40[0xc0];
6383
6384         struct mlx5_ifc_rmpc_bits ctx;
6385 };
6386
6387 struct mlx5_ifc_create_qp_out_bits {
6388         u8         status[0x8];
6389         u8         reserved_at_8[0x18];
6390
6391         u8         syndrome[0x20];
6392
6393         u8         reserved_at_40[0x8];
6394         u8         qpn[0x18];
6395
6396         u8         reserved_at_60[0x20];
6397 };
6398
6399 struct mlx5_ifc_create_qp_in_bits {
6400         u8         opcode[0x10];
6401         u8         reserved_at_10[0x10];
6402
6403         u8         reserved_at_20[0x10];
6404         u8         op_mod[0x10];
6405
6406         u8         reserved_at_40[0x40];
6407
6408         u8         opt_param_mask[0x20];
6409
6410         u8         reserved_at_a0[0x20];
6411
6412         struct mlx5_ifc_qpc_bits qpc;
6413
6414         u8         reserved_at_800[0x80];
6415
6416         u8         pas[0][0x40];
6417 };
6418
6419 struct mlx5_ifc_create_psv_out_bits {
6420         u8         status[0x8];
6421         u8         reserved_at_8[0x18];
6422
6423         u8         syndrome[0x20];
6424
6425         u8         reserved_at_40[0x40];
6426
6427         u8         reserved_at_80[0x8];
6428         u8         psv0_index[0x18];
6429
6430         u8         reserved_at_a0[0x8];
6431         u8         psv1_index[0x18];
6432
6433         u8         reserved_at_c0[0x8];
6434         u8         psv2_index[0x18];
6435
6436         u8         reserved_at_e0[0x8];
6437         u8         psv3_index[0x18];
6438 };
6439
6440 struct mlx5_ifc_create_psv_in_bits {
6441         u8         opcode[0x10];
6442         u8         reserved_at_10[0x10];
6443
6444         u8         reserved_at_20[0x10];
6445         u8         op_mod[0x10];
6446
6447         u8         num_psv[0x4];
6448         u8         reserved_at_44[0x4];
6449         u8         pd[0x18];
6450
6451         u8         reserved_at_60[0x20];
6452 };
6453
6454 struct mlx5_ifc_create_mkey_out_bits {
6455         u8         status[0x8];
6456         u8         reserved_at_8[0x18];
6457
6458         u8         syndrome[0x20];
6459
6460         u8         reserved_at_40[0x8];
6461         u8         mkey_index[0x18];
6462
6463         u8         reserved_at_60[0x20];
6464 };
6465
6466 struct mlx5_ifc_create_mkey_in_bits {
6467         u8         opcode[0x10];
6468         u8         reserved_at_10[0x10];
6469
6470         u8         reserved_at_20[0x10];
6471         u8         op_mod[0x10];
6472
6473         u8         reserved_at_40[0x20];
6474
6475         u8         pg_access[0x1];
6476         u8         reserved_at_61[0x1f];
6477
6478         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6479
6480         u8         reserved_at_280[0x80];
6481
6482         u8         translations_octword_actual_size[0x20];
6483
6484         u8         reserved_at_320[0x560];
6485
6486         u8         klm_pas_mtt[0][0x20];
6487 };
6488
6489 struct mlx5_ifc_create_flow_table_out_bits {
6490         u8         status[0x8];
6491         u8         reserved_at_8[0x18];
6492
6493         u8         syndrome[0x20];
6494
6495         u8         reserved_at_40[0x8];
6496         u8         table_id[0x18];
6497
6498         u8         reserved_at_60[0x20];
6499 };
6500
6501 struct mlx5_ifc_create_flow_table_in_bits {
6502         u8         opcode[0x10];
6503         u8         reserved_at_10[0x10];
6504
6505         u8         reserved_at_20[0x10];
6506         u8         op_mod[0x10];
6507
6508         u8         other_vport[0x1];
6509         u8         reserved_at_41[0xf];
6510         u8         vport_number[0x10];
6511
6512         u8         reserved_at_60[0x20];
6513
6514         u8         table_type[0x8];
6515         u8         reserved_at_88[0x18];
6516
6517         u8         reserved_at_a0[0x20];
6518
6519         u8         encap_en[0x1];
6520         u8         decap_en[0x1];
6521         u8         reserved_at_c2[0x2];
6522         u8         table_miss_mode[0x4];
6523         u8         level[0x8];
6524         u8         reserved_at_d0[0x8];
6525         u8         log_size[0x8];
6526
6527         u8         reserved_at_e0[0x8];
6528         u8         table_miss_id[0x18];
6529
6530         u8         reserved_at_100[0x8];
6531         u8         lag_master_next_table_id[0x18];
6532
6533         u8         reserved_at_120[0x80];
6534 };
6535
6536 struct mlx5_ifc_create_flow_group_out_bits {
6537         u8         status[0x8];
6538         u8         reserved_at_8[0x18];
6539
6540         u8         syndrome[0x20];
6541
6542         u8         reserved_at_40[0x8];
6543         u8         group_id[0x18];
6544
6545         u8         reserved_at_60[0x20];
6546 };
6547
6548 enum {
6549         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6550         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6551         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6552 };
6553
6554 struct mlx5_ifc_create_flow_group_in_bits {
6555         u8         opcode[0x10];
6556         u8         reserved_at_10[0x10];
6557
6558         u8         reserved_at_20[0x10];
6559         u8         op_mod[0x10];
6560
6561         u8         other_vport[0x1];
6562         u8         reserved_at_41[0xf];
6563         u8         vport_number[0x10];
6564
6565         u8         reserved_at_60[0x20];
6566
6567         u8         table_type[0x8];
6568         u8         reserved_at_88[0x18];
6569
6570         u8         reserved_at_a0[0x8];
6571         u8         table_id[0x18];
6572
6573         u8         reserved_at_c0[0x20];
6574
6575         u8         start_flow_index[0x20];
6576
6577         u8         reserved_at_100[0x20];
6578
6579         u8         end_flow_index[0x20];
6580
6581         u8         reserved_at_140[0xa0];
6582
6583         u8         reserved_at_1e0[0x18];
6584         u8         match_criteria_enable[0x8];
6585
6586         struct mlx5_ifc_fte_match_param_bits match_criteria;
6587
6588         u8         reserved_at_1200[0xe00];
6589 };
6590
6591 struct mlx5_ifc_create_eq_out_bits {
6592         u8         status[0x8];
6593         u8         reserved_at_8[0x18];
6594
6595         u8         syndrome[0x20];
6596
6597         u8         reserved_at_40[0x18];
6598         u8         eq_number[0x8];
6599
6600         u8         reserved_at_60[0x20];
6601 };
6602
6603 struct mlx5_ifc_create_eq_in_bits {
6604         u8         opcode[0x10];
6605         u8         reserved_at_10[0x10];
6606
6607         u8         reserved_at_20[0x10];
6608         u8         op_mod[0x10];
6609
6610         u8         reserved_at_40[0x40];
6611
6612         struct mlx5_ifc_eqc_bits eq_context_entry;
6613
6614         u8         reserved_at_280[0x40];
6615
6616         u8         event_bitmask[0x40];
6617
6618         u8         reserved_at_300[0x580];
6619
6620         u8         pas[0][0x40];
6621 };
6622
6623 struct mlx5_ifc_create_dct_out_bits {
6624         u8         status[0x8];
6625         u8         reserved_at_8[0x18];
6626
6627         u8         syndrome[0x20];
6628
6629         u8         reserved_at_40[0x8];
6630         u8         dctn[0x18];
6631
6632         u8         reserved_at_60[0x20];
6633 };
6634
6635 struct mlx5_ifc_create_dct_in_bits {
6636         u8         opcode[0x10];
6637         u8         reserved_at_10[0x10];
6638
6639         u8         reserved_at_20[0x10];
6640         u8         op_mod[0x10];
6641
6642         u8         reserved_at_40[0x40];
6643
6644         struct mlx5_ifc_dctc_bits dct_context_entry;
6645
6646         u8         reserved_at_280[0x180];
6647 };
6648
6649 struct mlx5_ifc_create_cq_out_bits {
6650         u8         status[0x8];
6651         u8         reserved_at_8[0x18];
6652
6653         u8         syndrome[0x20];
6654
6655         u8         reserved_at_40[0x8];
6656         u8         cqn[0x18];
6657
6658         u8         reserved_at_60[0x20];
6659 };
6660
6661 struct mlx5_ifc_create_cq_in_bits {
6662         u8         opcode[0x10];
6663         u8         reserved_at_10[0x10];
6664
6665         u8         reserved_at_20[0x10];
6666         u8         op_mod[0x10];
6667
6668         u8         reserved_at_40[0x40];
6669
6670         struct mlx5_ifc_cqc_bits cq_context;
6671
6672         u8         reserved_at_280[0x600];
6673
6674         u8         pas[0][0x40];
6675 };
6676
6677 struct mlx5_ifc_config_int_moderation_out_bits {
6678         u8         status[0x8];
6679         u8         reserved_at_8[0x18];
6680
6681         u8         syndrome[0x20];
6682
6683         u8         reserved_at_40[0x4];
6684         u8         min_delay[0xc];
6685         u8         int_vector[0x10];
6686
6687         u8         reserved_at_60[0x20];
6688 };
6689
6690 enum {
6691         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6692         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6693 };
6694
6695 struct mlx5_ifc_config_int_moderation_in_bits {
6696         u8         opcode[0x10];
6697         u8         reserved_at_10[0x10];
6698
6699         u8         reserved_at_20[0x10];
6700         u8         op_mod[0x10];
6701
6702         u8         reserved_at_40[0x4];
6703         u8         min_delay[0xc];
6704         u8         int_vector[0x10];
6705
6706         u8         reserved_at_60[0x20];
6707 };
6708
6709 struct mlx5_ifc_attach_to_mcg_out_bits {
6710         u8         status[0x8];
6711         u8         reserved_at_8[0x18];
6712
6713         u8         syndrome[0x20];
6714
6715         u8         reserved_at_40[0x40];
6716 };
6717
6718 struct mlx5_ifc_attach_to_mcg_in_bits {
6719         u8         opcode[0x10];
6720         u8         reserved_at_10[0x10];
6721
6722         u8         reserved_at_20[0x10];
6723         u8         op_mod[0x10];
6724
6725         u8         reserved_at_40[0x8];
6726         u8         qpn[0x18];
6727
6728         u8         reserved_at_60[0x20];
6729
6730         u8         multicast_gid[16][0x8];
6731 };
6732
6733 struct mlx5_ifc_arm_xrq_out_bits {
6734         u8         status[0x8];
6735         u8         reserved_at_8[0x18];
6736
6737         u8         syndrome[0x20];
6738
6739         u8         reserved_at_40[0x40];
6740 };
6741
6742 struct mlx5_ifc_arm_xrq_in_bits {
6743         u8         opcode[0x10];
6744         u8         reserved_at_10[0x10];
6745
6746         u8         reserved_at_20[0x10];
6747         u8         op_mod[0x10];
6748
6749         u8         reserved_at_40[0x8];
6750         u8         xrqn[0x18];
6751
6752         u8         reserved_at_60[0x10];
6753         u8         lwm[0x10];
6754 };
6755
6756 struct mlx5_ifc_arm_xrc_srq_out_bits {
6757         u8         status[0x8];
6758         u8         reserved_at_8[0x18];
6759
6760         u8         syndrome[0x20];
6761
6762         u8         reserved_at_40[0x40];
6763 };
6764
6765 enum {
6766         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6767 };
6768
6769 struct mlx5_ifc_arm_xrc_srq_in_bits {
6770         u8         opcode[0x10];
6771         u8         reserved_at_10[0x10];
6772
6773         u8         reserved_at_20[0x10];
6774         u8         op_mod[0x10];
6775
6776         u8         reserved_at_40[0x8];
6777         u8         xrc_srqn[0x18];
6778
6779         u8         reserved_at_60[0x10];
6780         u8         lwm[0x10];
6781 };
6782
6783 struct mlx5_ifc_arm_rq_out_bits {
6784         u8         status[0x8];
6785         u8         reserved_at_8[0x18];
6786
6787         u8         syndrome[0x20];
6788
6789         u8         reserved_at_40[0x40];
6790 };
6791
6792 enum {
6793         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6794         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6795 };
6796
6797 struct mlx5_ifc_arm_rq_in_bits {
6798         u8         opcode[0x10];
6799         u8         reserved_at_10[0x10];
6800
6801         u8         reserved_at_20[0x10];
6802         u8         op_mod[0x10];
6803
6804         u8         reserved_at_40[0x8];
6805         u8         srq_number[0x18];
6806
6807         u8         reserved_at_60[0x10];
6808         u8         lwm[0x10];
6809 };
6810
6811 struct mlx5_ifc_arm_dct_out_bits {
6812         u8         status[0x8];
6813         u8         reserved_at_8[0x18];
6814
6815         u8         syndrome[0x20];
6816
6817         u8         reserved_at_40[0x40];
6818 };
6819
6820 struct mlx5_ifc_arm_dct_in_bits {
6821         u8         opcode[0x10];
6822         u8         reserved_at_10[0x10];
6823
6824         u8         reserved_at_20[0x10];
6825         u8         op_mod[0x10];
6826
6827         u8         reserved_at_40[0x8];
6828         u8         dct_number[0x18];
6829
6830         u8         reserved_at_60[0x20];
6831 };
6832
6833 struct mlx5_ifc_alloc_xrcd_out_bits {
6834         u8         status[0x8];
6835         u8         reserved_at_8[0x18];
6836
6837         u8         syndrome[0x20];
6838
6839         u8         reserved_at_40[0x8];
6840         u8         xrcd[0x18];
6841
6842         u8         reserved_at_60[0x20];
6843 };
6844
6845 struct mlx5_ifc_alloc_xrcd_in_bits {
6846         u8         opcode[0x10];
6847         u8         reserved_at_10[0x10];
6848
6849         u8         reserved_at_20[0x10];
6850         u8         op_mod[0x10];
6851
6852         u8         reserved_at_40[0x40];
6853 };
6854
6855 struct mlx5_ifc_alloc_uar_out_bits {
6856         u8         status[0x8];
6857         u8         reserved_at_8[0x18];
6858
6859         u8         syndrome[0x20];
6860
6861         u8         reserved_at_40[0x8];
6862         u8         uar[0x18];
6863
6864         u8         reserved_at_60[0x20];
6865 };
6866
6867 struct mlx5_ifc_alloc_uar_in_bits {
6868         u8         opcode[0x10];
6869         u8         reserved_at_10[0x10];
6870
6871         u8         reserved_at_20[0x10];
6872         u8         op_mod[0x10];
6873
6874         u8         reserved_at_40[0x40];
6875 };
6876
6877 struct mlx5_ifc_alloc_transport_domain_out_bits {
6878         u8         status[0x8];
6879         u8         reserved_at_8[0x18];
6880
6881         u8         syndrome[0x20];
6882
6883         u8         reserved_at_40[0x8];
6884         u8         transport_domain[0x18];
6885
6886         u8         reserved_at_60[0x20];
6887 };
6888
6889 struct mlx5_ifc_alloc_transport_domain_in_bits {
6890         u8         opcode[0x10];
6891         u8         reserved_at_10[0x10];
6892
6893         u8         reserved_at_20[0x10];
6894         u8         op_mod[0x10];
6895
6896         u8         reserved_at_40[0x40];
6897 };
6898
6899 struct mlx5_ifc_alloc_q_counter_out_bits {
6900         u8         status[0x8];
6901         u8         reserved_at_8[0x18];
6902
6903         u8         syndrome[0x20];
6904
6905         u8         reserved_at_40[0x18];
6906         u8         counter_set_id[0x8];
6907
6908         u8         reserved_at_60[0x20];
6909 };
6910
6911 struct mlx5_ifc_alloc_q_counter_in_bits {
6912         u8         opcode[0x10];
6913         u8         reserved_at_10[0x10];
6914
6915         u8         reserved_at_20[0x10];
6916         u8         op_mod[0x10];
6917
6918         u8         reserved_at_40[0x40];
6919 };
6920
6921 struct mlx5_ifc_alloc_pd_out_bits {
6922         u8         status[0x8];
6923         u8         reserved_at_8[0x18];
6924
6925         u8         syndrome[0x20];
6926
6927         u8         reserved_at_40[0x8];
6928         u8         pd[0x18];
6929
6930         u8         reserved_at_60[0x20];
6931 };
6932
6933 struct mlx5_ifc_alloc_pd_in_bits {
6934         u8         opcode[0x10];
6935         u8         reserved_at_10[0x10];
6936
6937         u8         reserved_at_20[0x10];
6938         u8         op_mod[0x10];
6939
6940         u8         reserved_at_40[0x40];
6941 };
6942
6943 struct mlx5_ifc_alloc_flow_counter_out_bits {
6944         u8         status[0x8];
6945         u8         reserved_at_8[0x18];
6946
6947         u8         syndrome[0x20];
6948
6949         u8         reserved_at_40[0x10];
6950         u8         flow_counter_id[0x10];
6951
6952         u8         reserved_at_60[0x20];
6953 };
6954
6955 struct mlx5_ifc_alloc_flow_counter_in_bits {
6956         u8         opcode[0x10];
6957         u8         reserved_at_10[0x10];
6958
6959         u8         reserved_at_20[0x10];
6960         u8         op_mod[0x10];
6961
6962         u8         reserved_at_40[0x40];
6963 };
6964
6965 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6966         u8         status[0x8];
6967         u8         reserved_at_8[0x18];
6968
6969         u8         syndrome[0x20];
6970
6971         u8         reserved_at_40[0x40];
6972 };
6973
6974 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6975         u8         opcode[0x10];
6976         u8         reserved_at_10[0x10];
6977
6978         u8         reserved_at_20[0x10];
6979         u8         op_mod[0x10];
6980
6981         u8         reserved_at_40[0x20];
6982
6983         u8         reserved_at_60[0x10];
6984         u8         vxlan_udp_port[0x10];
6985 };
6986
6987 struct mlx5_ifc_set_rate_limit_out_bits {
6988         u8         status[0x8];
6989         u8         reserved_at_8[0x18];
6990
6991         u8         syndrome[0x20];
6992
6993         u8         reserved_at_40[0x40];
6994 };
6995
6996 struct mlx5_ifc_set_rate_limit_in_bits {
6997         u8         opcode[0x10];
6998         u8         reserved_at_10[0x10];
6999
7000         u8         reserved_at_20[0x10];
7001         u8         op_mod[0x10];
7002
7003         u8         reserved_at_40[0x10];
7004         u8         rate_limit_index[0x10];
7005
7006         u8         reserved_at_60[0x20];
7007
7008         u8         rate_limit[0x20];
7009 };
7010
7011 struct mlx5_ifc_access_register_out_bits {
7012         u8         status[0x8];
7013         u8         reserved_at_8[0x18];
7014
7015         u8         syndrome[0x20];
7016
7017         u8         reserved_at_40[0x40];
7018
7019         u8         register_data[0][0x20];
7020 };
7021
7022 enum {
7023         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7024         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7025 };
7026
7027 struct mlx5_ifc_access_register_in_bits {
7028         u8         opcode[0x10];
7029         u8         reserved_at_10[0x10];
7030
7031         u8         reserved_at_20[0x10];
7032         u8         op_mod[0x10];
7033
7034         u8         reserved_at_40[0x10];
7035         u8         register_id[0x10];
7036
7037         u8         argument[0x20];
7038
7039         u8         register_data[0][0x20];
7040 };
7041
7042 struct mlx5_ifc_sltp_reg_bits {
7043         u8         status[0x4];
7044         u8         version[0x4];
7045         u8         local_port[0x8];
7046         u8         pnat[0x2];
7047         u8         reserved_at_12[0x2];
7048         u8         lane[0x4];
7049         u8         reserved_at_18[0x8];
7050
7051         u8         reserved_at_20[0x20];
7052
7053         u8         reserved_at_40[0x7];
7054         u8         polarity[0x1];
7055         u8         ob_tap0[0x8];
7056         u8         ob_tap1[0x8];
7057         u8         ob_tap2[0x8];
7058
7059         u8         reserved_at_60[0xc];
7060         u8         ob_preemp_mode[0x4];
7061         u8         ob_reg[0x8];
7062         u8         ob_bias[0x8];
7063
7064         u8         reserved_at_80[0x20];
7065 };
7066
7067 struct mlx5_ifc_slrg_reg_bits {
7068         u8         status[0x4];
7069         u8         version[0x4];
7070         u8         local_port[0x8];
7071         u8         pnat[0x2];
7072         u8         reserved_at_12[0x2];
7073         u8         lane[0x4];
7074         u8         reserved_at_18[0x8];
7075
7076         u8         time_to_link_up[0x10];
7077         u8         reserved_at_30[0xc];
7078         u8         grade_lane_speed[0x4];
7079
7080         u8         grade_version[0x8];
7081         u8         grade[0x18];
7082
7083         u8         reserved_at_60[0x4];
7084         u8         height_grade_type[0x4];
7085         u8         height_grade[0x18];
7086
7087         u8         height_dz[0x10];
7088         u8         height_dv[0x10];
7089
7090         u8         reserved_at_a0[0x10];
7091         u8         height_sigma[0x10];
7092
7093         u8         reserved_at_c0[0x20];
7094
7095         u8         reserved_at_e0[0x4];
7096         u8         phase_grade_type[0x4];
7097         u8         phase_grade[0x18];
7098
7099         u8         reserved_at_100[0x8];
7100         u8         phase_eo_pos[0x8];
7101         u8         reserved_at_110[0x8];
7102         u8         phase_eo_neg[0x8];
7103
7104         u8         ffe_set_tested[0x10];
7105         u8         test_errors_per_lane[0x10];
7106 };
7107
7108 struct mlx5_ifc_pvlc_reg_bits {
7109         u8         reserved_at_0[0x8];
7110         u8         local_port[0x8];
7111         u8         reserved_at_10[0x10];
7112
7113         u8         reserved_at_20[0x1c];
7114         u8         vl_hw_cap[0x4];
7115
7116         u8         reserved_at_40[0x1c];
7117         u8         vl_admin[0x4];
7118
7119         u8         reserved_at_60[0x1c];
7120         u8         vl_operational[0x4];
7121 };
7122
7123 struct mlx5_ifc_pude_reg_bits {
7124         u8         swid[0x8];
7125         u8         local_port[0x8];
7126         u8         reserved_at_10[0x4];
7127         u8         admin_status[0x4];
7128         u8         reserved_at_18[0x4];
7129         u8         oper_status[0x4];
7130
7131         u8         reserved_at_20[0x60];
7132 };
7133
7134 struct mlx5_ifc_ptys_reg_bits {
7135         u8         reserved_at_0[0x1];
7136         u8         an_disable_admin[0x1];
7137         u8         an_disable_cap[0x1];
7138         u8         reserved_at_3[0x5];
7139         u8         local_port[0x8];
7140         u8         reserved_at_10[0xd];
7141         u8         proto_mask[0x3];
7142
7143         u8         an_status[0x4];
7144         u8         reserved_at_24[0x3c];
7145
7146         u8         eth_proto_capability[0x20];
7147
7148         u8         ib_link_width_capability[0x10];
7149         u8         ib_proto_capability[0x10];
7150
7151         u8         reserved_at_a0[0x20];
7152
7153         u8         eth_proto_admin[0x20];
7154
7155         u8         ib_link_width_admin[0x10];
7156         u8         ib_proto_admin[0x10];
7157
7158         u8         reserved_at_100[0x20];
7159
7160         u8         eth_proto_oper[0x20];
7161
7162         u8         ib_link_width_oper[0x10];
7163         u8         ib_proto_oper[0x10];
7164
7165         u8         reserved_at_160[0x20];
7166
7167         u8         eth_proto_lp_advertise[0x20];
7168
7169         u8         reserved_at_1a0[0x60];
7170 };
7171
7172 struct mlx5_ifc_mlcr_reg_bits {
7173         u8         reserved_at_0[0x8];
7174         u8         local_port[0x8];
7175         u8         reserved_at_10[0x20];
7176
7177         u8         beacon_duration[0x10];
7178         u8         reserved_at_40[0x10];
7179
7180         u8         beacon_remain[0x10];
7181 };
7182
7183 struct mlx5_ifc_ptas_reg_bits {
7184         u8         reserved_at_0[0x20];
7185
7186         u8         algorithm_options[0x10];
7187         u8         reserved_at_30[0x4];
7188         u8         repetitions_mode[0x4];
7189         u8         num_of_repetitions[0x8];
7190
7191         u8         grade_version[0x8];
7192         u8         height_grade_type[0x4];
7193         u8         phase_grade_type[0x4];
7194         u8         height_grade_weight[0x8];
7195         u8         phase_grade_weight[0x8];
7196
7197         u8         gisim_measure_bits[0x10];
7198         u8         adaptive_tap_measure_bits[0x10];
7199
7200         u8         ber_bath_high_error_threshold[0x10];
7201         u8         ber_bath_mid_error_threshold[0x10];
7202
7203         u8         ber_bath_low_error_threshold[0x10];
7204         u8         one_ratio_high_threshold[0x10];
7205
7206         u8         one_ratio_high_mid_threshold[0x10];
7207         u8         one_ratio_low_mid_threshold[0x10];
7208
7209         u8         one_ratio_low_threshold[0x10];
7210         u8         ndeo_error_threshold[0x10];
7211
7212         u8         mixer_offset_step_size[0x10];
7213         u8         reserved_at_110[0x8];
7214         u8         mix90_phase_for_voltage_bath[0x8];
7215
7216         u8         mixer_offset_start[0x10];
7217         u8         mixer_offset_end[0x10];
7218
7219         u8         reserved_at_140[0x15];
7220         u8         ber_test_time[0xb];
7221 };
7222
7223 struct mlx5_ifc_pspa_reg_bits {
7224         u8         swid[0x8];
7225         u8         local_port[0x8];
7226         u8         sub_port[0x8];
7227         u8         reserved_at_18[0x8];
7228
7229         u8         reserved_at_20[0x20];
7230 };
7231
7232 struct mlx5_ifc_pqdr_reg_bits {
7233         u8         reserved_at_0[0x8];
7234         u8         local_port[0x8];
7235         u8         reserved_at_10[0x5];
7236         u8         prio[0x3];
7237         u8         reserved_at_18[0x6];
7238         u8         mode[0x2];
7239
7240         u8         reserved_at_20[0x20];
7241
7242         u8         reserved_at_40[0x10];
7243         u8         min_threshold[0x10];
7244
7245         u8         reserved_at_60[0x10];
7246         u8         max_threshold[0x10];
7247
7248         u8         reserved_at_80[0x10];
7249         u8         mark_probability_denominator[0x10];
7250
7251         u8         reserved_at_a0[0x60];
7252 };
7253
7254 struct mlx5_ifc_ppsc_reg_bits {
7255         u8         reserved_at_0[0x8];
7256         u8         local_port[0x8];
7257         u8         reserved_at_10[0x10];
7258
7259         u8         reserved_at_20[0x60];
7260
7261         u8         reserved_at_80[0x1c];
7262         u8         wrps_admin[0x4];
7263
7264         u8         reserved_at_a0[0x1c];
7265         u8         wrps_status[0x4];
7266
7267         u8         reserved_at_c0[0x8];
7268         u8         up_threshold[0x8];
7269         u8         reserved_at_d0[0x8];
7270         u8         down_threshold[0x8];
7271
7272         u8         reserved_at_e0[0x20];
7273
7274         u8         reserved_at_100[0x1c];
7275         u8         srps_admin[0x4];
7276
7277         u8         reserved_at_120[0x1c];
7278         u8         srps_status[0x4];
7279
7280         u8         reserved_at_140[0x40];
7281 };
7282
7283 struct mlx5_ifc_pplr_reg_bits {
7284         u8         reserved_at_0[0x8];
7285         u8         local_port[0x8];
7286         u8         reserved_at_10[0x10];
7287
7288         u8         reserved_at_20[0x8];
7289         u8         lb_cap[0x8];
7290         u8         reserved_at_30[0x8];
7291         u8         lb_en[0x8];
7292 };
7293
7294 struct mlx5_ifc_pplm_reg_bits {
7295         u8         reserved_at_0[0x8];
7296         u8         local_port[0x8];
7297         u8         reserved_at_10[0x10];
7298
7299         u8         reserved_at_20[0x20];
7300
7301         u8         port_profile_mode[0x8];
7302         u8         static_port_profile[0x8];
7303         u8         active_port_profile[0x8];
7304         u8         reserved_at_58[0x8];
7305
7306         u8         retransmission_active[0x8];
7307         u8         fec_mode_active[0x18];
7308
7309         u8         reserved_at_80[0x20];
7310 };
7311
7312 struct mlx5_ifc_ppcnt_reg_bits {
7313         u8         swid[0x8];
7314         u8         local_port[0x8];
7315         u8         pnat[0x2];
7316         u8         reserved_at_12[0x8];
7317         u8         grp[0x6];
7318
7319         u8         clr[0x1];
7320         u8         reserved_at_21[0x1c];
7321         u8         prio_tc[0x3];
7322
7323         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7324 };
7325
7326 struct mlx5_ifc_mpcnt_reg_bits {
7327         u8         reserved_at_0[0x8];
7328         u8         pcie_index[0x8];
7329         u8         reserved_at_10[0xa];
7330         u8         grp[0x6];
7331
7332         u8         clr[0x1];
7333         u8         reserved_at_21[0x1f];
7334
7335         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7336 };
7337
7338 struct mlx5_ifc_ppad_reg_bits {
7339         u8         reserved_at_0[0x3];
7340         u8         single_mac[0x1];
7341         u8         reserved_at_4[0x4];
7342         u8         local_port[0x8];
7343         u8         mac_47_32[0x10];
7344
7345         u8         mac_31_0[0x20];
7346
7347         u8         reserved_at_40[0x40];
7348 };
7349
7350 struct mlx5_ifc_pmtu_reg_bits {
7351         u8         reserved_at_0[0x8];
7352         u8         local_port[0x8];
7353         u8         reserved_at_10[0x10];
7354
7355         u8         max_mtu[0x10];
7356         u8         reserved_at_30[0x10];
7357
7358         u8         admin_mtu[0x10];
7359         u8         reserved_at_50[0x10];
7360
7361         u8         oper_mtu[0x10];
7362         u8         reserved_at_70[0x10];
7363 };
7364
7365 struct mlx5_ifc_pmpr_reg_bits {
7366         u8         reserved_at_0[0x8];
7367         u8         module[0x8];
7368         u8         reserved_at_10[0x10];
7369
7370         u8         reserved_at_20[0x18];
7371         u8         attenuation_5g[0x8];
7372
7373         u8         reserved_at_40[0x18];
7374         u8         attenuation_7g[0x8];
7375
7376         u8         reserved_at_60[0x18];
7377         u8         attenuation_12g[0x8];
7378 };
7379
7380 struct mlx5_ifc_pmpe_reg_bits {
7381         u8         reserved_at_0[0x8];
7382         u8         module[0x8];
7383         u8         reserved_at_10[0xc];
7384         u8         module_status[0x4];
7385
7386         u8         reserved_at_20[0x60];
7387 };
7388
7389 struct mlx5_ifc_pmpc_reg_bits {
7390         u8         module_state_updated[32][0x8];
7391 };
7392
7393 struct mlx5_ifc_pmlpn_reg_bits {
7394         u8         reserved_at_0[0x4];
7395         u8         mlpn_status[0x4];
7396         u8         local_port[0x8];
7397         u8         reserved_at_10[0x10];
7398
7399         u8         e[0x1];
7400         u8         reserved_at_21[0x1f];
7401 };
7402
7403 struct mlx5_ifc_pmlp_reg_bits {
7404         u8         rxtx[0x1];
7405         u8         reserved_at_1[0x7];
7406         u8         local_port[0x8];
7407         u8         reserved_at_10[0x8];
7408         u8         width[0x8];
7409
7410         u8         lane0_module_mapping[0x20];
7411
7412         u8         lane1_module_mapping[0x20];
7413
7414         u8         lane2_module_mapping[0x20];
7415
7416         u8         lane3_module_mapping[0x20];
7417
7418         u8         reserved_at_a0[0x160];
7419 };
7420
7421 struct mlx5_ifc_pmaos_reg_bits {
7422         u8         reserved_at_0[0x8];
7423         u8         module[0x8];
7424         u8         reserved_at_10[0x4];
7425         u8         admin_status[0x4];
7426         u8         reserved_at_18[0x4];
7427         u8         oper_status[0x4];
7428
7429         u8         ase[0x1];
7430         u8         ee[0x1];
7431         u8         reserved_at_22[0x1c];
7432         u8         e[0x2];
7433
7434         u8         reserved_at_40[0x40];
7435 };
7436
7437 struct mlx5_ifc_plpc_reg_bits {
7438         u8         reserved_at_0[0x4];
7439         u8         profile_id[0xc];
7440         u8         reserved_at_10[0x4];
7441         u8         proto_mask[0x4];
7442         u8         reserved_at_18[0x8];
7443
7444         u8         reserved_at_20[0x10];
7445         u8         lane_speed[0x10];
7446
7447         u8         reserved_at_40[0x17];
7448         u8         lpbf[0x1];
7449         u8         fec_mode_policy[0x8];
7450
7451         u8         retransmission_capability[0x8];
7452         u8         fec_mode_capability[0x18];
7453
7454         u8         retransmission_support_admin[0x8];
7455         u8         fec_mode_support_admin[0x18];
7456
7457         u8         retransmission_request_admin[0x8];
7458         u8         fec_mode_request_admin[0x18];
7459
7460         u8         reserved_at_c0[0x80];
7461 };
7462
7463 struct mlx5_ifc_plib_reg_bits {
7464         u8         reserved_at_0[0x8];
7465         u8         local_port[0x8];
7466         u8         reserved_at_10[0x8];
7467         u8         ib_port[0x8];
7468
7469         u8         reserved_at_20[0x60];
7470 };
7471
7472 struct mlx5_ifc_plbf_reg_bits {
7473         u8         reserved_at_0[0x8];
7474         u8         local_port[0x8];
7475         u8         reserved_at_10[0xd];
7476         u8         lbf_mode[0x3];
7477
7478         u8         reserved_at_20[0x20];
7479 };
7480
7481 struct mlx5_ifc_pipg_reg_bits {
7482         u8         reserved_at_0[0x8];
7483         u8         local_port[0x8];
7484         u8         reserved_at_10[0x10];
7485
7486         u8         dic[0x1];
7487         u8         reserved_at_21[0x19];
7488         u8         ipg[0x4];
7489         u8         reserved_at_3e[0x2];
7490 };
7491
7492 struct mlx5_ifc_pifr_reg_bits {
7493         u8         reserved_at_0[0x8];
7494         u8         local_port[0x8];
7495         u8         reserved_at_10[0x10];
7496
7497         u8         reserved_at_20[0xe0];
7498
7499         u8         port_filter[8][0x20];
7500
7501         u8         port_filter_update_en[8][0x20];
7502 };
7503
7504 struct mlx5_ifc_pfcc_reg_bits {
7505         u8         reserved_at_0[0x8];
7506         u8         local_port[0x8];
7507         u8         reserved_at_10[0x10];
7508
7509         u8         ppan[0x4];
7510         u8         reserved_at_24[0x4];
7511         u8         prio_mask_tx[0x8];
7512         u8         reserved_at_30[0x8];
7513         u8         prio_mask_rx[0x8];
7514
7515         u8         pptx[0x1];
7516         u8         aptx[0x1];
7517         u8         reserved_at_42[0x6];
7518         u8         pfctx[0x8];
7519         u8         reserved_at_50[0x10];
7520
7521         u8         pprx[0x1];
7522         u8         aprx[0x1];
7523         u8         reserved_at_62[0x6];
7524         u8         pfcrx[0x8];
7525         u8         reserved_at_70[0x10];
7526
7527         u8         reserved_at_80[0x80];
7528 };
7529
7530 struct mlx5_ifc_pelc_reg_bits {
7531         u8         op[0x4];
7532         u8         reserved_at_4[0x4];
7533         u8         local_port[0x8];
7534         u8         reserved_at_10[0x10];
7535
7536         u8         op_admin[0x8];
7537         u8         op_capability[0x8];
7538         u8         op_request[0x8];
7539         u8         op_active[0x8];
7540
7541         u8         admin[0x40];
7542
7543         u8         capability[0x40];
7544
7545         u8         request[0x40];
7546
7547         u8         active[0x40];
7548
7549         u8         reserved_at_140[0x80];
7550 };
7551
7552 struct mlx5_ifc_peir_reg_bits {
7553         u8         reserved_at_0[0x8];
7554         u8         local_port[0x8];
7555         u8         reserved_at_10[0x10];
7556
7557         u8         reserved_at_20[0xc];
7558         u8         error_count[0x4];
7559         u8         reserved_at_30[0x10];
7560
7561         u8         reserved_at_40[0xc];
7562         u8         lane[0x4];
7563         u8         reserved_at_50[0x8];
7564         u8         error_type[0x8];
7565 };
7566
7567 struct mlx5_ifc_pcam_enhanced_features_bits {
7568         u8         reserved_at_0[0x7e];
7569
7570         u8         ppcnt_discard_group[0x1];
7571         u8         ppcnt_statistical_group[0x1];
7572 };
7573
7574 struct mlx5_ifc_pcam_reg_bits {
7575         u8         reserved_at_0[0x8];
7576         u8         feature_group[0x8];
7577         u8         reserved_at_10[0x8];
7578         u8         access_reg_group[0x8];
7579
7580         u8         reserved_at_20[0x20];
7581
7582         union {
7583                 u8         reserved_at_0[0x80];
7584         } port_access_reg_cap_mask;
7585
7586         u8         reserved_at_c0[0x80];
7587
7588         union {
7589                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7590                 u8         reserved_at_0[0x80];
7591         } feature_cap_mask;
7592
7593         u8         reserved_at_1c0[0xc0];
7594 };
7595
7596 struct mlx5_ifc_mcam_enhanced_features_bits {
7597         u8         reserved_at_0[0x7f];
7598
7599         u8         pcie_performance_group[0x1];
7600 };
7601
7602 struct mlx5_ifc_mcam_reg_bits {
7603         u8         reserved_at_0[0x8];
7604         u8         feature_group[0x8];
7605         u8         reserved_at_10[0x8];
7606         u8         access_reg_group[0x8];
7607
7608         u8         reserved_at_20[0x20];
7609
7610         union {
7611                 u8         reserved_at_0[0x80];
7612         } mng_access_reg_cap_mask;
7613
7614         u8         reserved_at_c0[0x80];
7615
7616         union {
7617                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7618                 u8         reserved_at_0[0x80];
7619         } mng_feature_cap_mask;
7620
7621         u8         reserved_at_1c0[0x80];
7622 };
7623
7624 struct mlx5_ifc_pcap_reg_bits {
7625         u8         reserved_at_0[0x8];
7626         u8         local_port[0x8];
7627         u8         reserved_at_10[0x10];
7628
7629         u8         port_capability_mask[4][0x20];
7630 };
7631
7632 struct mlx5_ifc_paos_reg_bits {
7633         u8         swid[0x8];
7634         u8         local_port[0x8];
7635         u8         reserved_at_10[0x4];
7636         u8         admin_status[0x4];
7637         u8         reserved_at_18[0x4];
7638         u8         oper_status[0x4];
7639
7640         u8         ase[0x1];
7641         u8         ee[0x1];
7642         u8         reserved_at_22[0x1c];
7643         u8         e[0x2];
7644
7645         u8         reserved_at_40[0x40];
7646 };
7647
7648 struct mlx5_ifc_pamp_reg_bits {
7649         u8         reserved_at_0[0x8];
7650         u8         opamp_group[0x8];
7651         u8         reserved_at_10[0xc];
7652         u8         opamp_group_type[0x4];
7653
7654         u8         start_index[0x10];
7655         u8         reserved_at_30[0x4];
7656         u8         num_of_indices[0xc];
7657
7658         u8         index_data[18][0x10];
7659 };
7660
7661 struct mlx5_ifc_pcmr_reg_bits {
7662         u8         reserved_at_0[0x8];
7663         u8         local_port[0x8];
7664         u8         reserved_at_10[0x2e];
7665         u8         fcs_cap[0x1];
7666         u8         reserved_at_3f[0x1f];
7667         u8         fcs_chk[0x1];
7668         u8         reserved_at_5f[0x1];
7669 };
7670
7671 struct mlx5_ifc_lane_2_module_mapping_bits {
7672         u8         reserved_at_0[0x6];
7673         u8         rx_lane[0x2];
7674         u8         reserved_at_8[0x6];
7675         u8         tx_lane[0x2];
7676         u8         reserved_at_10[0x8];
7677         u8         module[0x8];
7678 };
7679
7680 struct mlx5_ifc_bufferx_reg_bits {
7681         u8         reserved_at_0[0x6];
7682         u8         lossy[0x1];
7683         u8         epsb[0x1];
7684         u8         reserved_at_8[0xc];
7685         u8         size[0xc];
7686
7687         u8         xoff_threshold[0x10];
7688         u8         xon_threshold[0x10];
7689 };
7690
7691 struct mlx5_ifc_set_node_in_bits {
7692         u8         node_description[64][0x8];
7693 };
7694
7695 struct mlx5_ifc_register_power_settings_bits {
7696         u8         reserved_at_0[0x18];
7697         u8         power_settings_level[0x8];
7698
7699         u8         reserved_at_20[0x60];
7700 };
7701
7702 struct mlx5_ifc_register_host_endianness_bits {
7703         u8         he[0x1];
7704         u8         reserved_at_1[0x1f];
7705
7706         u8         reserved_at_20[0x60];
7707 };
7708
7709 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7710         u8         reserved_at_0[0x20];
7711
7712         u8         mkey[0x20];
7713
7714         u8         addressh_63_32[0x20];
7715
7716         u8         addressl_31_0[0x20];
7717 };
7718
7719 struct mlx5_ifc_ud_adrs_vector_bits {
7720         u8         dc_key[0x40];
7721
7722         u8         ext[0x1];
7723         u8         reserved_at_41[0x7];
7724         u8         destination_qp_dct[0x18];
7725
7726         u8         static_rate[0x4];
7727         u8         sl_eth_prio[0x4];
7728         u8         fl[0x1];
7729         u8         mlid[0x7];
7730         u8         rlid_udp_sport[0x10];
7731
7732         u8         reserved_at_80[0x20];
7733
7734         u8         rmac_47_16[0x20];
7735
7736         u8         rmac_15_0[0x10];
7737         u8         tclass[0x8];
7738         u8         hop_limit[0x8];
7739
7740         u8         reserved_at_e0[0x1];
7741         u8         grh[0x1];
7742         u8         reserved_at_e2[0x2];
7743         u8         src_addr_index[0x8];
7744         u8         flow_label[0x14];
7745
7746         u8         rgid_rip[16][0x8];
7747 };
7748
7749 struct mlx5_ifc_pages_req_event_bits {
7750         u8         reserved_at_0[0x10];
7751         u8         function_id[0x10];
7752
7753         u8         num_pages[0x20];
7754
7755         u8         reserved_at_40[0xa0];
7756 };
7757
7758 struct mlx5_ifc_eqe_bits {
7759         u8         reserved_at_0[0x8];
7760         u8         event_type[0x8];
7761         u8         reserved_at_10[0x8];
7762         u8         event_sub_type[0x8];
7763
7764         u8         reserved_at_20[0xe0];
7765
7766         union mlx5_ifc_event_auto_bits event_data;
7767
7768         u8         reserved_at_1e0[0x10];
7769         u8         signature[0x8];
7770         u8         reserved_at_1f8[0x7];
7771         u8         owner[0x1];
7772 };
7773
7774 enum {
7775         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7776 };
7777
7778 struct mlx5_ifc_cmd_queue_entry_bits {
7779         u8         type[0x8];
7780         u8         reserved_at_8[0x18];
7781
7782         u8         input_length[0x20];
7783
7784         u8         input_mailbox_pointer_63_32[0x20];
7785
7786         u8         input_mailbox_pointer_31_9[0x17];
7787         u8         reserved_at_77[0x9];
7788
7789         u8         command_input_inline_data[16][0x8];
7790
7791         u8         command_output_inline_data[16][0x8];
7792
7793         u8         output_mailbox_pointer_63_32[0x20];
7794
7795         u8         output_mailbox_pointer_31_9[0x17];
7796         u8         reserved_at_1b7[0x9];
7797
7798         u8         output_length[0x20];
7799
7800         u8         token[0x8];
7801         u8         signature[0x8];
7802         u8         reserved_at_1f0[0x8];
7803         u8         status[0x7];
7804         u8         ownership[0x1];
7805 };
7806
7807 struct mlx5_ifc_cmd_out_bits {
7808         u8         status[0x8];
7809         u8         reserved_at_8[0x18];
7810
7811         u8         syndrome[0x20];
7812
7813         u8         command_output[0x20];
7814 };
7815
7816 struct mlx5_ifc_cmd_in_bits {
7817         u8         opcode[0x10];
7818         u8         reserved_at_10[0x10];
7819
7820         u8         reserved_at_20[0x10];
7821         u8         op_mod[0x10];
7822
7823         u8         command[0][0x20];
7824 };
7825
7826 struct mlx5_ifc_cmd_if_box_bits {
7827         u8         mailbox_data[512][0x8];
7828
7829         u8         reserved_at_1000[0x180];
7830
7831         u8         next_pointer_63_32[0x20];
7832
7833         u8         next_pointer_31_10[0x16];
7834         u8         reserved_at_11b6[0xa];
7835
7836         u8         block_number[0x20];
7837
7838         u8         reserved_at_11e0[0x8];
7839         u8         token[0x8];
7840         u8         ctrl_signature[0x8];
7841         u8         signature[0x8];
7842 };
7843
7844 struct mlx5_ifc_mtt_bits {
7845         u8         ptag_63_32[0x20];
7846
7847         u8         ptag_31_8[0x18];
7848         u8         reserved_at_38[0x6];
7849         u8         wr_en[0x1];
7850         u8         rd_en[0x1];
7851 };
7852
7853 struct mlx5_ifc_query_wol_rol_out_bits {
7854         u8         status[0x8];
7855         u8         reserved_at_8[0x18];
7856
7857         u8         syndrome[0x20];
7858
7859         u8         reserved_at_40[0x10];
7860         u8         rol_mode[0x8];
7861         u8         wol_mode[0x8];
7862
7863         u8         reserved_at_60[0x20];
7864 };
7865
7866 struct mlx5_ifc_query_wol_rol_in_bits {
7867         u8         opcode[0x10];
7868         u8         reserved_at_10[0x10];
7869
7870         u8         reserved_at_20[0x10];
7871         u8         op_mod[0x10];
7872
7873         u8         reserved_at_40[0x40];
7874 };
7875
7876 struct mlx5_ifc_set_wol_rol_out_bits {
7877         u8         status[0x8];
7878         u8         reserved_at_8[0x18];
7879
7880         u8         syndrome[0x20];
7881
7882         u8         reserved_at_40[0x40];
7883 };
7884
7885 struct mlx5_ifc_set_wol_rol_in_bits {
7886         u8         opcode[0x10];
7887         u8         reserved_at_10[0x10];
7888
7889         u8         reserved_at_20[0x10];
7890         u8         op_mod[0x10];
7891
7892         u8         rol_mode_valid[0x1];
7893         u8         wol_mode_valid[0x1];
7894         u8         reserved_at_42[0xe];
7895         u8         rol_mode[0x8];
7896         u8         wol_mode[0x8];
7897
7898         u8         reserved_at_60[0x20];
7899 };
7900
7901 enum {
7902         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
7903         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
7904         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
7905 };
7906
7907 enum {
7908         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
7909         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
7910         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
7911 };
7912
7913 enum {
7914         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
7915         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
7916         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
7917         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
7918         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
7919         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
7920         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
7921         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
7922         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
7923         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
7924         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
7925 };
7926
7927 struct mlx5_ifc_initial_seg_bits {
7928         u8         fw_rev_minor[0x10];
7929         u8         fw_rev_major[0x10];
7930
7931         u8         cmd_interface_rev[0x10];
7932         u8         fw_rev_subminor[0x10];
7933
7934         u8         reserved_at_40[0x40];
7935
7936         u8         cmdq_phy_addr_63_32[0x20];
7937
7938         u8         cmdq_phy_addr_31_12[0x14];
7939         u8         reserved_at_b4[0x2];
7940         u8         nic_interface[0x2];
7941         u8         log_cmdq_size[0x4];
7942         u8         log_cmdq_stride[0x4];
7943
7944         u8         command_doorbell_vector[0x20];
7945
7946         u8         reserved_at_e0[0xf00];
7947
7948         u8         initializing[0x1];
7949         u8         reserved_at_fe1[0x4];
7950         u8         nic_interface_supported[0x3];
7951         u8         reserved_at_fe8[0x18];
7952
7953         struct mlx5_ifc_health_buffer_bits health_buffer;
7954
7955         u8         no_dram_nic_offset[0x20];
7956
7957         u8         reserved_at_1220[0x6e40];
7958
7959         u8         reserved_at_8060[0x1f];
7960         u8         clear_int[0x1];
7961
7962         u8         health_syndrome[0x8];
7963         u8         health_counter[0x18];
7964
7965         u8         reserved_at_80a0[0x17fc0];
7966 };
7967
7968 struct mlx5_ifc_mtpps_reg_bits {
7969         u8         reserved_at_0[0xc];
7970         u8         cap_number_of_pps_pins[0x4];
7971         u8         reserved_at_10[0x4];
7972         u8         cap_max_num_of_pps_in_pins[0x4];
7973         u8         reserved_at_18[0x4];
7974         u8         cap_max_num_of_pps_out_pins[0x4];
7975
7976         u8         reserved_at_20[0x24];
7977         u8         cap_pin_3_mode[0x4];
7978         u8         reserved_at_48[0x4];
7979         u8         cap_pin_2_mode[0x4];
7980         u8         reserved_at_50[0x4];
7981         u8         cap_pin_1_mode[0x4];
7982         u8         reserved_at_58[0x4];
7983         u8         cap_pin_0_mode[0x4];
7984
7985         u8         reserved_at_60[0x4];
7986         u8         cap_pin_7_mode[0x4];
7987         u8         reserved_at_68[0x4];
7988         u8         cap_pin_6_mode[0x4];
7989         u8         reserved_at_70[0x4];
7990         u8         cap_pin_5_mode[0x4];
7991         u8         reserved_at_78[0x4];
7992         u8         cap_pin_4_mode[0x4];
7993
7994         u8         reserved_at_80[0x80];
7995
7996         u8         enable[0x1];
7997         u8         reserved_at_101[0xb];
7998         u8         pattern[0x4];
7999         u8         reserved_at_110[0x4];
8000         u8         pin_mode[0x4];
8001         u8         pin[0x8];
8002
8003         u8         reserved_at_120[0x20];
8004
8005         u8         time_stamp[0x40];
8006
8007         u8         out_pulse_duration[0x10];
8008         u8         out_periodic_adjustment[0x10];
8009
8010         u8         reserved_at_1a0[0x60];
8011 };
8012
8013 struct mlx5_ifc_mtppse_reg_bits {
8014         u8         reserved_at_0[0x18];
8015         u8         pin[0x8];
8016         u8         event_arm[0x1];
8017         u8         reserved_at_21[0x1b];
8018         u8         event_generation_mode[0x4];
8019         u8         reserved_at_40[0x40];
8020 };
8021
8022 union mlx5_ifc_ports_control_registers_document_bits {
8023         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8024         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8025         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8026         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8027         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8028         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8029         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8030         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8031         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8032         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8033         struct mlx5_ifc_paos_reg_bits paos_reg;
8034         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8035         struct mlx5_ifc_peir_reg_bits peir_reg;
8036         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8037         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8038         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8039         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8040         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8041         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8042         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8043         struct mlx5_ifc_plib_reg_bits plib_reg;
8044         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8045         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8046         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8047         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8048         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8049         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8050         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8051         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8052         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8053         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8054         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8055         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8056         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8057         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8058         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8059         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8060         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8061         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8062         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8063         struct mlx5_ifc_pude_reg_bits pude_reg;
8064         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8065         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8066         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8067         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8068         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8069         u8         reserved_at_0[0x60e0];
8070 };
8071
8072 union mlx5_ifc_debug_enhancements_document_bits {
8073         struct mlx5_ifc_health_buffer_bits health_buffer;
8074         u8         reserved_at_0[0x200];
8075 };
8076
8077 union mlx5_ifc_uplink_pci_interface_document_bits {
8078         struct mlx5_ifc_initial_seg_bits initial_seg;
8079         u8         reserved_at_0[0x20060];
8080 };
8081
8082 struct mlx5_ifc_set_flow_table_root_out_bits {
8083         u8         status[0x8];
8084         u8         reserved_at_8[0x18];
8085
8086         u8         syndrome[0x20];
8087
8088         u8         reserved_at_40[0x40];
8089 };
8090
8091 struct mlx5_ifc_set_flow_table_root_in_bits {
8092         u8         opcode[0x10];
8093         u8         reserved_at_10[0x10];
8094
8095         u8         reserved_at_20[0x10];
8096         u8         op_mod[0x10];
8097
8098         u8         other_vport[0x1];
8099         u8         reserved_at_41[0xf];
8100         u8         vport_number[0x10];
8101
8102         u8         reserved_at_60[0x20];
8103
8104         u8         table_type[0x8];
8105         u8         reserved_at_88[0x18];
8106
8107         u8         reserved_at_a0[0x8];
8108         u8         table_id[0x18];
8109
8110         u8         reserved_at_c0[0x140];
8111 };
8112
8113 enum {
8114         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8115         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8116 };
8117
8118 struct mlx5_ifc_modify_flow_table_out_bits {
8119         u8         status[0x8];
8120         u8         reserved_at_8[0x18];
8121
8122         u8         syndrome[0x20];
8123
8124         u8         reserved_at_40[0x40];
8125 };
8126
8127 struct mlx5_ifc_modify_flow_table_in_bits {
8128         u8         opcode[0x10];
8129         u8         reserved_at_10[0x10];
8130
8131         u8         reserved_at_20[0x10];
8132         u8         op_mod[0x10];
8133
8134         u8         other_vport[0x1];
8135         u8         reserved_at_41[0xf];
8136         u8         vport_number[0x10];
8137
8138         u8         reserved_at_60[0x10];
8139         u8         modify_field_select[0x10];
8140
8141         u8         table_type[0x8];
8142         u8         reserved_at_88[0x18];
8143
8144         u8         reserved_at_a0[0x8];
8145         u8         table_id[0x18];
8146
8147         u8         reserved_at_c0[0x4];
8148         u8         table_miss_mode[0x4];
8149         u8         reserved_at_c8[0x18];
8150
8151         u8         reserved_at_e0[0x8];
8152         u8         table_miss_id[0x18];
8153
8154         u8         reserved_at_100[0x8];
8155         u8         lag_master_next_table_id[0x18];
8156
8157         u8         reserved_at_120[0x80];
8158 };
8159
8160 struct mlx5_ifc_ets_tcn_config_reg_bits {
8161         u8         g[0x1];
8162         u8         b[0x1];
8163         u8         r[0x1];
8164         u8         reserved_at_3[0x9];
8165         u8         group[0x4];
8166         u8         reserved_at_10[0x9];
8167         u8         bw_allocation[0x7];
8168
8169         u8         reserved_at_20[0xc];
8170         u8         max_bw_units[0x4];
8171         u8         reserved_at_30[0x8];
8172         u8         max_bw_value[0x8];
8173 };
8174
8175 struct mlx5_ifc_ets_global_config_reg_bits {
8176         u8         reserved_at_0[0x2];
8177         u8         r[0x1];
8178         u8         reserved_at_3[0x1d];
8179
8180         u8         reserved_at_20[0xc];
8181         u8         max_bw_units[0x4];
8182         u8         reserved_at_30[0x8];
8183         u8         max_bw_value[0x8];
8184 };
8185
8186 struct mlx5_ifc_qetc_reg_bits {
8187         u8                                         reserved_at_0[0x8];
8188         u8                                         port_number[0x8];
8189         u8                                         reserved_at_10[0x30];
8190
8191         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8192         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8193 };
8194
8195 struct mlx5_ifc_qtct_reg_bits {
8196         u8         reserved_at_0[0x8];
8197         u8         port_number[0x8];
8198         u8         reserved_at_10[0xd];
8199         u8         prio[0x3];
8200
8201         u8         reserved_at_20[0x1d];
8202         u8         tclass[0x3];
8203 };
8204
8205 struct mlx5_ifc_mcia_reg_bits {
8206         u8         l[0x1];
8207         u8         reserved_at_1[0x7];
8208         u8         module[0x8];
8209         u8         reserved_at_10[0x8];
8210         u8         status[0x8];
8211
8212         u8         i2c_device_address[0x8];
8213         u8         page_number[0x8];
8214         u8         device_address[0x10];
8215
8216         u8         reserved_at_40[0x10];
8217         u8         size[0x10];
8218
8219         u8         reserved_at_60[0x20];
8220
8221         u8         dword_0[0x20];
8222         u8         dword_1[0x20];
8223         u8         dword_2[0x20];
8224         u8         dword_3[0x20];
8225         u8         dword_4[0x20];
8226         u8         dword_5[0x20];
8227         u8         dword_6[0x20];
8228         u8         dword_7[0x20];
8229         u8         dword_8[0x20];
8230         u8         dword_9[0x20];
8231         u8         dword_10[0x20];
8232         u8         dword_11[0x20];
8233 };
8234
8235 struct mlx5_ifc_dcbx_param_bits {
8236         u8         dcbx_cee_cap[0x1];
8237         u8         dcbx_ieee_cap[0x1];
8238         u8         dcbx_standby_cap[0x1];
8239         u8         reserved_at_0[0x5];
8240         u8         port_number[0x8];
8241         u8         reserved_at_10[0xa];
8242         u8         max_application_table_size[6];
8243         u8         reserved_at_20[0x15];
8244         u8         version_oper[0x3];
8245         u8         reserved_at_38[5];
8246         u8         version_admin[0x3];
8247         u8         willing_admin[0x1];
8248         u8         reserved_at_41[0x3];
8249         u8         pfc_cap_oper[0x4];
8250         u8         reserved_at_48[0x4];
8251         u8         pfc_cap_admin[0x4];
8252         u8         reserved_at_50[0x4];
8253         u8         num_of_tc_oper[0x4];
8254         u8         reserved_at_58[0x4];
8255         u8         num_of_tc_admin[0x4];
8256         u8         remote_willing[0x1];
8257         u8         reserved_at_61[3];
8258         u8         remote_pfc_cap[4];
8259         u8         reserved_at_68[0x14];
8260         u8         remote_num_of_tc[0x4];
8261         u8         reserved_at_80[0x18];
8262         u8         error[0x8];
8263         u8         reserved_at_a0[0x160];
8264 };
8265
8266 struct mlx5_ifc_lagc_bits {
8267         u8         reserved_at_0[0x1d];
8268         u8         lag_state[0x3];
8269
8270         u8         reserved_at_20[0x14];
8271         u8         tx_remap_affinity_2[0x4];
8272         u8         reserved_at_38[0x4];
8273         u8         tx_remap_affinity_1[0x4];
8274 };
8275
8276 struct mlx5_ifc_create_lag_out_bits {
8277         u8         status[0x8];
8278         u8         reserved_at_8[0x18];
8279
8280         u8         syndrome[0x20];
8281
8282         u8         reserved_at_40[0x40];
8283 };
8284
8285 struct mlx5_ifc_create_lag_in_bits {
8286         u8         opcode[0x10];
8287         u8         reserved_at_10[0x10];
8288
8289         u8         reserved_at_20[0x10];
8290         u8         op_mod[0x10];
8291
8292         struct mlx5_ifc_lagc_bits ctx;
8293 };
8294
8295 struct mlx5_ifc_modify_lag_out_bits {
8296         u8         status[0x8];
8297         u8         reserved_at_8[0x18];
8298
8299         u8         syndrome[0x20];
8300
8301         u8         reserved_at_40[0x40];
8302 };
8303
8304 struct mlx5_ifc_modify_lag_in_bits {
8305         u8         opcode[0x10];
8306         u8         reserved_at_10[0x10];
8307
8308         u8         reserved_at_20[0x10];
8309         u8         op_mod[0x10];
8310
8311         u8         reserved_at_40[0x20];
8312         u8         field_select[0x20];
8313
8314         struct mlx5_ifc_lagc_bits ctx;
8315 };
8316
8317 struct mlx5_ifc_query_lag_out_bits {
8318         u8         status[0x8];
8319         u8         reserved_at_8[0x18];
8320
8321         u8         syndrome[0x20];
8322
8323         u8         reserved_at_40[0x40];
8324
8325         struct mlx5_ifc_lagc_bits ctx;
8326 };
8327
8328 struct mlx5_ifc_query_lag_in_bits {
8329         u8         opcode[0x10];
8330         u8         reserved_at_10[0x10];
8331
8332         u8         reserved_at_20[0x10];
8333         u8         op_mod[0x10];
8334
8335         u8         reserved_at_40[0x40];
8336 };
8337
8338 struct mlx5_ifc_destroy_lag_out_bits {
8339         u8         status[0x8];
8340         u8         reserved_at_8[0x18];
8341
8342         u8         syndrome[0x20];
8343
8344         u8         reserved_at_40[0x40];
8345 };
8346
8347 struct mlx5_ifc_destroy_lag_in_bits {
8348         u8         opcode[0x10];
8349         u8         reserved_at_10[0x10];
8350
8351         u8         reserved_at_20[0x10];
8352         u8         op_mod[0x10];
8353
8354         u8         reserved_at_40[0x40];
8355 };
8356
8357 struct mlx5_ifc_create_vport_lag_out_bits {
8358         u8         status[0x8];
8359         u8         reserved_at_8[0x18];
8360
8361         u8         syndrome[0x20];
8362
8363         u8         reserved_at_40[0x40];
8364 };
8365
8366 struct mlx5_ifc_create_vport_lag_in_bits {
8367         u8         opcode[0x10];
8368         u8         reserved_at_10[0x10];
8369
8370         u8         reserved_at_20[0x10];
8371         u8         op_mod[0x10];
8372
8373         u8         reserved_at_40[0x40];
8374 };
8375
8376 struct mlx5_ifc_destroy_vport_lag_out_bits {
8377         u8         status[0x8];
8378         u8         reserved_at_8[0x18];
8379
8380         u8         syndrome[0x20];
8381
8382         u8         reserved_at_40[0x40];
8383 };
8384
8385 struct mlx5_ifc_destroy_vport_lag_in_bits {
8386         u8         opcode[0x10];
8387         u8         reserved_at_10[0x10];
8388
8389         u8         reserved_at_20[0x10];
8390         u8         op_mod[0x10];
8391
8392         u8         reserved_at_40[0x40];
8393 };
8394
8395 #endif /* MLX5_IFC_H */