2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> et al.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <linux/delay.h>
24 #include <linux/types.h>
25 #include <linux/interrupt.h>
26 #include <linux/mtd/flashchip.h>
27 #include <linux/mtd/map.h>
28 #include <linux/mtd/cfi_endian.h>
29 #include <linux/mtd/xip.h>
31 #ifdef CONFIG_MTD_CFI_I1
32 #define cfi_interleave(cfi) 1
33 #define cfi_interleave_is_1(cfi) (cfi_interleave(cfi) == 1)
35 #define cfi_interleave_is_1(cfi) (0)
38 #ifdef CONFIG_MTD_CFI_I2
39 # ifdef cfi_interleave
40 # undef cfi_interleave
41 # define cfi_interleave(cfi) ((cfi)->interleave)
43 # define cfi_interleave(cfi) 2
45 #define cfi_interleave_is_2(cfi) (cfi_interleave(cfi) == 2)
47 #define cfi_interleave_is_2(cfi) (0)
50 #ifdef CONFIG_MTD_CFI_I4
51 # ifdef cfi_interleave
52 # undef cfi_interleave
53 # define cfi_interleave(cfi) ((cfi)->interleave)
55 # define cfi_interleave(cfi) 4
57 #define cfi_interleave_is_4(cfi) (cfi_interleave(cfi) == 4)
59 #define cfi_interleave_is_4(cfi) (0)
62 #ifdef CONFIG_MTD_CFI_I8
63 # ifdef cfi_interleave
64 # undef cfi_interleave
65 # define cfi_interleave(cfi) ((cfi)->interleave)
67 # define cfi_interleave(cfi) 8
69 #define cfi_interleave_is_8(cfi) (cfi_interleave(cfi) == 8)
71 #define cfi_interleave_is_8(cfi) (0)
74 #ifndef cfi_interleave
75 #warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work.
76 static inline int cfi_interleave(void *cfi)
83 static inline int cfi_interleave_supported(int i)
86 #ifdef CONFIG_MTD_CFI_I1
89 #ifdef CONFIG_MTD_CFI_I2
92 #ifdef CONFIG_MTD_CFI_I4
95 #ifdef CONFIG_MTD_CFI_I8
106 /* NB: these values must represents the number of bytes needed to meet the
107 * device type (x8, x16, x32). Eg. a 32 bit device is 4 x 8 bytes.
108 * These numbers are used in calculations.
110 #define CFI_DEVICETYPE_X8 (8 / 8)
111 #define CFI_DEVICETYPE_X16 (16 / 8)
112 #define CFI_DEVICETYPE_X32 (32 / 8)
113 #define CFI_DEVICETYPE_X64 (64 / 8)
116 /* Device Interface Code Assignments from the "Common Flash Memory Interface
117 * Publication 100" dated December 1, 2001.
119 #define CFI_INTERFACE_X8_ASYNC 0x0000
120 #define CFI_INTERFACE_X16_ASYNC 0x0001
121 #define CFI_INTERFACE_X8_BY_X16_ASYNC 0x0002
122 #define CFI_INTERFACE_X32_ASYNC 0x0003
123 #define CFI_INTERFACE_X16_BY_X32_ASYNC 0x0005
124 #define CFI_INTERFACE_NOT_ALLOWED 0xffff
127 /* NB: We keep these structures in memory in HOST byteorder, except
128 * where individually noted.
131 /* Basic Query Structure */
142 uint8_t WordWriteTimeoutTyp;
143 uint8_t BufWriteTimeoutTyp;
144 uint8_t BlockEraseTimeoutTyp;
145 uint8_t ChipEraseTimeoutTyp;
146 uint8_t WordWriteTimeoutMax;
147 uint8_t BufWriteTimeoutMax;
148 uint8_t BlockEraseTimeoutMax;
149 uint8_t ChipEraseTimeoutMax;
151 uint16_t InterfaceDesc;
152 uint16_t MaxBufWriteSize;
153 uint8_t NumEraseRegions;
154 uint32_t EraseRegionInfo[0]; /* Not host ordered */
155 } __attribute__((packed));
157 /* Extended Query Structure for both PRI and ALT */
159 struct cfi_extquery {
161 uint8_t MajorVersion;
162 uint8_t MinorVersion;
163 } __attribute__((packed));
165 /* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */
167 struct cfi_pri_intelext {
169 uint8_t MajorVersion;
170 uint8_t MinorVersion;
171 uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature
172 block follows - FIXME - not currently supported */
173 uint8_t SuspendCmdSupport;
174 uint16_t BlkStatusRegMask;
177 uint8_t NumProtectionFields;
178 uint16_t ProtRegAddr;
179 uint8_t FactProtRegSize;
180 uint8_t UserProtRegSize;
182 } __attribute__((packed));
184 struct cfi_intelext_otpinfo {
185 uint32_t ProtRegAddr;
187 uint8_t FactProtRegSize;
189 uint8_t UserProtRegSize;
190 } __attribute__((packed));
192 struct cfi_intelext_blockinfo {
193 uint16_t NumIdentBlocks;
195 uint16_t MinBlockEraseCycles;
198 } __attribute__((packed));
200 struct cfi_intelext_regioninfo {
201 uint16_t NumIdentPartitions;
202 uint8_t NumOpAllowed;
203 uint8_t NumOpAllowedSimProgMode;
204 uint8_t NumOpAllowedSimEraMode;
205 uint8_t NumBlockTypes;
206 struct cfi_intelext_blockinfo BlockTypes[1];
207 } __attribute__((packed));
209 struct cfi_intelext_programming_regioninfo {
210 uint8_t ProgRegShift;
212 uint8_t ControlValid;
214 uint8_t ControlInvalid;
216 } __attribute__((packed));
218 /* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */
220 struct cfi_pri_amdstd {
222 uint8_t MajorVersion;
223 uint8_t MinorVersion;
224 uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
225 uint8_t EraseSuspend;
227 uint8_t TmpBlkUnprotect;
228 uint8_t BlkProtUnprot;
229 uint8_t SimultaneousOps;
235 } __attribute__((packed));
237 /* Vendor-Specific PRI for Atmel chips (command set 0x0002) */
239 struct cfi_pri_atmel {
241 uint8_t MajorVersion;
242 uint8_t MinorVersion;
247 } __attribute__((packed));
249 struct cfi_pri_query {
251 uint32_t ProtField[1]; /* Not host ordered */
252 } __attribute__((packed));
254 struct cfi_bri_query {
255 uint8_t PageModeReadCap;
257 uint32_t ConfField[1]; /* Not host ordered */
258 } __attribute__((packed));
260 #define P_ID_NONE 0x0000
261 #define P_ID_INTEL_EXT 0x0001
262 #define P_ID_AMD_STD 0x0002
263 #define P_ID_INTEL_STD 0x0003
264 #define P_ID_AMD_EXT 0x0004
265 #define P_ID_WINBOND 0x0006
266 #define P_ID_ST_ADV 0x0020
267 #define P_ID_MITSUBISHI_STD 0x0100
268 #define P_ID_MITSUBISHI_EXT 0x0101
269 #define P_ID_SST_PAGE 0x0102
270 #define P_ID_SST_OLD 0x0701
271 #define P_ID_INTEL_PERFORMANCE 0x0200
272 #define P_ID_INTEL_DATA 0x0210
273 #define P_ID_RESERVED 0xffff
276 #define CFI_MODE_CFI 1
277 #define CFI_MODE_JEDEC 0
284 int cfi_mode; /* Are we a JEDEC device pretending to be CFI? */
287 struct mtd_info *(*cmdset_setup)(struct map_info *);
288 struct cfi_ident *cfiq; /* For now only one. We insist that all devs
289 must be of the same type. */
292 unsigned long chipshift; /* Because they're of the same type */
293 const char *im_name; /* inter_module name for cmdset_setup */
294 struct flchip chips[0]; /* per-chip data structure for each chip */
298 * Returns the command address according to the given geometry.
300 static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs,
301 struct map_info *map, struct cfi_private *cfi)
303 unsigned bankwidth = map_bankwidth(map);
304 unsigned interleave = cfi_interleave(cfi);
305 unsigned type = cfi->device_type;
308 addr = (cmd_ofs * type) * interleave;
310 /* Modify the unlock address if we are in compatiblity mode.
311 * For 16bit devices on 8 bit busses
312 * and 32bit devices on 16 bit busses
313 * set the low bit of the alternating bit sequence of the address.
315 if (((type * interleave) > bankwidth) && ((cmd_ofs & 0xff) == 0xaa))
316 addr |= (type >> 1)*interleave;
322 * Transforms the CFI command for the given geometry (bus width & interleave).
323 * It looks too long to be inline, but in the common case it should almost all
324 * get optimised away.
326 static inline map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi)
328 map_word val = { {0} };
329 int wordwidth, words_per_bus, chip_mode, chips_per_word;
330 unsigned long onecmd;
333 /* We do it this way to give the compiler a fighting chance
334 of optimising away all the crap for 'bankwidth' larger than
335 an unsigned long, in the common case where that support is
337 if (map_bankwidth_is_large(map)) {
338 wordwidth = sizeof(unsigned long);
339 words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
341 wordwidth = map_bankwidth(map);
345 chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
346 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);
348 /* First, determine what the bit-pattern should be for a single
349 device, according to chip mode and endianness... */
356 onecmd = cpu_to_cfi16(cmd);
359 onecmd = cpu_to_cfi32(cmd);
363 /* Now replicate it across the size of an unsigned long, or
364 just to the bus width as appropriate */
365 switch (chips_per_word) {
367 #if BITS_PER_LONG >= 64
369 onecmd |= (onecmd << (chip_mode * 32));
372 onecmd |= (onecmd << (chip_mode * 16));
374 onecmd |= (onecmd << (chip_mode * 8));
379 /* And finally, for the multi-word case, replicate it
380 in all words in the structure */
381 for (i=0; i < words_per_bus; i++) {
387 #define CMD(x) cfi_build_cmd((x), map, cfi)
390 static inline unsigned long cfi_merge_status(map_word val, struct map_info *map,
391 struct cfi_private *cfi)
393 int wordwidth, words_per_bus, chip_mode, chips_per_word;
394 unsigned long onestat, res = 0;
397 /* We do it this way to give the compiler a fighting chance
398 of optimising away all the crap for 'bankwidth' larger than
399 an unsigned long, in the common case where that support is
401 if (map_bankwidth_is_large(map)) {
402 wordwidth = sizeof(unsigned long);
403 words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
405 wordwidth = map_bankwidth(map);
409 chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
410 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);
413 /* Or all status words together */
414 for (i=1; i < words_per_bus; i++) {
419 switch(chips_per_word) {
421 #if BITS_PER_LONG >= 64
423 res |= (onestat >> (chip_mode * 32));
426 res |= (onestat >> (chip_mode * 16));
428 res |= (onestat >> (chip_mode * 8));
433 /* Last, determine what the bit-pattern should be for a single
434 device, according to chip mode and endianness... */
439 res = cfi16_to_cpu(res);
442 res = cfi32_to_cpu(res);
449 #define MERGESTATUS(x) cfi_merge_status((x), map, cfi)
453 * Sends a CFI command to a bank of flash for the given geometry.
455 * Returns the offset in flash where the command was written.
456 * If prev_val is non-null, it will be set to the value at the command address,
457 * before the command was written.
459 static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base,
460 struct map_info *map, struct cfi_private *cfi,
461 int type, map_word *prev_val)
464 uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, map, cfi);
465 val = cfi_build_cmd(cmd, map, cfi);
468 *prev_val = map_read(map, addr);
470 map_write(map, val, addr);
475 static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr)
477 map_word val = map_read(map, addr);
479 if (map_bankwidth_is_1(map)) {
481 } else if (map_bankwidth_is_2(map)) {
482 return cfi16_to_cpu(val.x[0]);
484 /* No point in a 64-bit byteswap since that would just be
485 swapping the responses from different chips, and we are
486 only interested in one chip (a representative sample) */
487 return cfi32_to_cpu(val.x[0]);
491 static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr)
493 map_word val = map_read(map, addr);
495 if (map_bankwidth_is_1(map)) {
496 return val.x[0] & 0xff;
497 } else if (map_bankwidth_is_2(map)) {
498 return cfi16_to_cpu(val.x[0]);
500 /* No point in a 64-bit byteswap since that would just be
501 swapping the responses from different chips, and we are
502 only interested in one chip (a representative sample) */
503 return cfi32_to_cpu(val.x[0]);
507 static inline void cfi_udelay(int us)
510 msleep((us+999)/1000);
517 int __xipram cfi_qry_present(struct map_info *map, __u32 base,
518 struct cfi_private *cfi);
519 int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map,
520 struct cfi_private *cfi);
521 void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map,
522 struct cfi_private *cfi);
524 struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size,
529 void (*fixup)(struct mtd_info *mtd, void* param);
533 #define CFI_MFR_ANY 0xFFFF
534 #define CFI_ID_ANY 0xFFFF
535 #define CFI_MFR_CONTINUATION 0x007F
537 #define CFI_MFR_AMD 0x0001
538 #define CFI_MFR_ATMEL 0x001F
539 #define CFI_MFR_EON 0x001C
540 #define CFI_MFR_FUJITSU 0x0004
541 #define CFI_MFR_HYUNDAI 0x00AD
542 #define CFI_MFR_INTEL 0x0089
543 #define CFI_MFR_MACRONIX 0x00C2
544 #define CFI_MFR_NEC 0x0010
545 #define CFI_MFR_PMC 0x009D
546 #define CFI_MFR_SAMSUNG 0x00EC
547 #define CFI_MFR_SHARP 0x00B0
548 #define CFI_MFR_SST 0x00BF
549 #define CFI_MFR_ST 0x0020 /* STMicroelectronics */
550 #define CFI_MFR_TOSHIBA 0x0098
551 #define CFI_MFR_WINBOND 0x00DA
553 void cfi_fixup(struct mtd_info *mtd, struct cfi_fixup* fixups);
555 typedef int (*varsize_frob_t)(struct map_info *map, struct flchip *chip,
556 unsigned long adr, int len, void *thunk);
558 int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob,
559 loff_t ofs, size_t len, void *thunk);
562 #endif /* __MTD_CFI_H__ */