2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * Contains standard defines and IDs for NAND flash devices
20 #ifndef __LINUX_MTD_NAND_H
21 #define __LINUX_MTD_NAND_H
23 #include <linux/config.h>
24 #include <linux/wait.h>
25 #include <linux/spinlock.h>
26 #include <linux/mtd/mtd.h>
29 /* Scan and identify a NAND device */
30 extern int nand_scan (struct mtd_info *mtd, int max_chips);
31 /* Free resources held by the NAND device */
32 extern void nand_release (struct mtd_info *mtd);
34 /* Read raw data from the device without ECC */
35 extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from,
36 size_t len, size_t ooblen);
39 /* The maximum number of NAND chips in an array */
40 #define NAND_MAX_CHIPS 8
42 /* This constant declares the max. oobsize / page, which
43 * is supported now. If you add a chip with bigger oobsize/page
44 * adjust this accordingly.
46 #define NAND_MAX_OOBSIZE 64
49 * Constants for hardware specific CLE/ALE/NCE function
51 /* Select the chip by setting nCE to low */
52 #define NAND_CTL_SETNCE 1
53 /* Deselect the chip by setting nCE to high */
54 #define NAND_CTL_CLRNCE 2
55 /* Select the command latch by setting CLE to high */
56 #define NAND_CTL_SETCLE 3
57 /* Deselect the command latch by setting CLE to low */
58 #define NAND_CTL_CLRCLE 4
59 /* Select the address latch by setting ALE to high */
60 #define NAND_CTL_SETALE 5
61 /* Deselect the address latch by setting ALE to low */
62 #define NAND_CTL_CLRALE 6
63 /* Set write protection by setting WP to high. Not used! */
64 #define NAND_CTL_SETWP 7
65 /* Clear write protection by setting WP to low. Not used! */
66 #define NAND_CTL_CLRWP 8
69 * Standard NAND flash commands
71 #define NAND_CMD_READ0 0
72 #define NAND_CMD_READ1 1
73 #define NAND_CMD_PAGEPROG 0x10
74 #define NAND_CMD_READOOB 0x50
75 #define NAND_CMD_ERASE1 0x60
76 #define NAND_CMD_STATUS 0x70
77 #define NAND_CMD_STATUS_MULTI 0x71
78 #define NAND_CMD_SEQIN 0x80
79 #define NAND_CMD_READID 0x90
80 #define NAND_CMD_ERASE2 0xd0
81 #define NAND_CMD_RESET 0xff
83 /* Extended commands for large page devices */
84 #define NAND_CMD_READSTART 0x30
85 #define NAND_CMD_CACHEDPROG 0x15
87 /* Extended commands for AG-AND device */
89 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
90 * there is no way to distinguish that from NAND_CMD_READ0
91 * until the remaining sequence of commands has been completed
92 * so add a high order bit and mask it off in the command.
94 #define NAND_CMD_DEPLETE1 0x100
95 #define NAND_CMD_DEPLETE2 0x38
96 #define NAND_CMD_STATUS_MULTI 0x71
97 #define NAND_CMD_STATUS_ERROR 0x72
98 /* multi-bank error status (banks 0-3) */
99 #define NAND_CMD_STATUS_ERROR0 0x73
100 #define NAND_CMD_STATUS_ERROR1 0x74
101 #define NAND_CMD_STATUS_ERROR2 0x75
102 #define NAND_CMD_STATUS_ERROR3 0x76
103 #define NAND_CMD_STATUS_RESET 0x7f
104 #define NAND_CMD_STATUS_CLEAR 0xff
107 #define NAND_STATUS_FAIL 0x01
108 #define NAND_STATUS_FAIL_N1 0x02
109 #define NAND_STATUS_TRUE_READY 0x20
110 #define NAND_STATUS_READY 0x40
111 #define NAND_STATUS_WP 0x80
114 * Constants for ECC_MODES
117 /* No ECC. Usage is not recommended ! */
118 #define NAND_ECC_NONE 0
119 /* Software ECC 3 byte ECC per 256 Byte data */
120 #define NAND_ECC_SOFT 1
121 /* Hardware ECC 3 byte ECC per 256 Byte data */
122 #define NAND_ECC_HW3_256 2
123 /* Hardware ECC 3 byte ECC per 512 Byte data */
124 #define NAND_ECC_HW3_512 3
125 /* Hardware ECC 3 byte ECC per 512 Byte data */
126 #define NAND_ECC_HW6_512 4
127 /* Hardware ECC 8 byte ECC per 512 Byte data */
128 #define NAND_ECC_HW8_512 6
129 /* Hardware ECC 12 byte ECC per 2048 Byte data */
130 #define NAND_ECC_HW12_2048 7
133 * Constants for Hardware ECC
135 /* Reset Hardware ECC for read */
136 #define NAND_ECC_READ 0
137 /* Reset Hardware ECC for write */
138 #define NAND_ECC_WRITE 1
139 /* Enable Hardware ECC before syndrom is read back from flash */
140 #define NAND_ECC_READSYN 2
142 /* Bit mask for flags passed to do_nand_read_ecc */
143 #define NAND_GET_DEVICE 0x80
146 /* Option constants for bizarre disfunctionality and real
149 /* Chip can not auto increment pages */
150 #define NAND_NO_AUTOINCR 0x00000001
151 /* Buswitdh is 16 bit */
152 #define NAND_BUSWIDTH_16 0x00000002
153 /* Device supports partial programming without padding */
154 #define NAND_NO_PADDING 0x00000004
155 /* Chip has cache program function */
156 #define NAND_CACHEPRG 0x00000008
157 /* Chip has copy back function */
158 #define NAND_COPYBACK 0x00000010
159 /* AND Chip which has 4 banks and a confusing page / block
160 * assignment. See Renesas datasheet for further information */
161 #define NAND_IS_AND 0x00000020
162 /* Chip has a array of 4 pages which can be read without
163 * additional ready /busy waits */
164 #define NAND_4PAGE_ARRAY 0x00000040
165 /* Chip requires that BBT is periodically rewritten to prevent
166 * bits from adjacent blocks from 'leaking' in altering data.
167 * This happens with the Renesas AG-AND chips, possibly others. */
168 #define BBT_AUTO_REFRESH 0x00000080
170 /* Options valid for Samsung large page devices */
171 #define NAND_SAMSUNG_LP_OPTIONS \
172 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
174 /* Macros to identify the above */
175 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
176 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
177 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
178 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
180 /* Mask to zero out the chip options, which come from the id table */
181 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
183 /* Non chip related options */
184 /* Use a flash based bad block table. This option is passed to the
185 * default bad block table function. */
186 #define NAND_USE_FLASH_BBT 0x00010000
187 /* The hw ecc generator provides a syndrome instead a ecc value on read
188 * This can only work if we have the ecc bytes directly behind the
189 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
190 #define NAND_HWECC_SYNDROME 0x00020000
191 /* This option skips the bbt scan during initialization. */
192 #define NAND_SKIP_BBTSCAN 0x00040000
194 /* Options set by nand scan */
195 /* Nand scan has allocated controller struct */
196 #define NAND_CONTROLLER_ALLOC 0x20000000
197 /* Nand scan has allocated oob_buf */
198 #define NAND_OOBBUF_ALLOC 0x40000000
199 /* Nand scan has allocated data_buf */
200 #define NAND_DATABUF_ALLOC 0x80000000
204 * nand_state_t - chip states
205 * Enumeration for NAND flash chip state
221 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
222 * @lock: protection lock
223 * @active: the mtd device which holds the controller currently
224 * @wq: wait queue to sleep on if a NAND operation is in progress
225 * used instead of the per chip wait queue when a hw controller is available
227 struct nand_hw_control {
229 struct nand_chip *active;
230 wait_queue_head_t wq;
234 * struct nand_chip - NAND Private Flash Chip Data
235 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
236 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
237 * @read_byte: [REPLACEABLE] read one byte from the chip
238 * @write_byte: [REPLACEABLE] write one byte to the chip
239 * @read_word: [REPLACEABLE] read one word from the chip
240 * @write_word: [REPLACEABLE] write one word to the chip
241 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
242 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
243 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
244 * @select_chip: [REPLACEABLE] select chip nr
245 * @block_bad: [REPLACEABLE] check, if the block is bad
246 * @block_markbad: [REPLACEABLE] mark the block bad
247 * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
248 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
249 * If set to NULL no access to ready/busy is available and the ready/busy information
250 * is read from the chip status register
251 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
252 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
253 * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
254 * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
255 * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
256 * be provided if a hardware ECC is available
257 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
258 * @scan_bbt: [REPLACEABLE] function to scan bad block table
259 * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
260 * @eccsize: [INTERN] databytes used per ecc-calculation
261 * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
262 * @eccsteps: [INTERN] number of ecc calculation steps per page
263 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
264 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
265 * @state: [INTERN] the current state of the NAND device
266 * @page_shift: [INTERN] number of address bits in a page (column address bits)
267 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
268 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
269 * @chip_shift: [INTERN] number of address bits in one chip
270 * @data_buf: [INTERN] internal buffer for one page + oob
271 * @oob_buf: [INTERN] oob buffer for one eraseblock
272 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
273 * @data_poi: [INTERN] pointer to a data buffer
274 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
275 * special functionality. See the defines for further explanation
276 * @badblockpos: [INTERN] position of the bad block marker in the oob area
277 * @numchips: [INTERN] number of physical chips
278 * @chipsize: [INTERN] the size of one chip for multichip arrays
279 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
280 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
281 * @autooob: [REPLACEABLE] the default (auto)placement scheme
282 * @bbt: [INTERN] bad block table pointer
283 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
284 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
285 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
286 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
287 * which is shared among multiple independend devices
288 * @priv: [OPTIONAL] pointer to private chip date
289 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
290 * (determine if errors are correctable)
294 void __iomem *IO_ADDR_R;
295 void __iomem *IO_ADDR_W;
297 uint8_t (*read_byte)(struct mtd_info *mtd);
298 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
299 u16 (*read_word)(struct mtd_info *mtd);
300 void (*write_word)(struct mtd_info *mtd, u16 word);
302 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
303 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
304 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
305 void (*select_chip)(struct mtd_info *mtd, int chip);
306 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
307 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
308 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
309 int (*dev_ready)(struct mtd_info *mtd);
310 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
311 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
312 int (*calculate_ecc)(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code);
313 int (*correct_data)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc);
314 void (*enable_hwecc)(struct mtd_info *mtd, int mode);
315 void (*erase_cmd)(struct mtd_info *mtd, int page);
316 int (*scan_bbt)(struct mtd_info *mtd);
322 wait_queue_head_t wq;
325 int phys_erase_shift;
332 unsigned int options;
335 unsigned long chipsize;
338 struct nand_oobinfo *autooob;
340 struct nand_bbt_descr *bbt_td;
341 struct nand_bbt_descr *bbt_md;
342 struct nand_bbt_descr *badblock_pattern;
343 struct nand_hw_control *controller;
345 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
349 * NAND Flash Manufacturer ID Codes
351 #define NAND_MFR_TOSHIBA 0x98
352 #define NAND_MFR_SAMSUNG 0xec
353 #define NAND_MFR_FUJITSU 0x04
354 #define NAND_MFR_NATIONAL 0x8f
355 #define NAND_MFR_RENESAS 0x07
356 #define NAND_MFR_STMICRO 0x20
357 #define NAND_MFR_HYNIX 0xad
360 * struct nand_flash_dev - NAND Flash Device ID Structure
362 * @name: Identify the device type
363 * @id: device ID code
364 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
365 * If the pagesize is 0, then the real pagesize
366 * and the eraseize are determined from the
367 * extended id bytes in the chip
368 * @erasesize: Size of an erase block in the flash device.
369 * @chipsize: Total chipsize in Mega Bytes
370 * @options: Bitfield to store chip relevant options
372 struct nand_flash_dev {
375 unsigned long pagesize;
376 unsigned long chipsize;
377 unsigned long erasesize;
378 unsigned long options;
382 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
383 * @name: Manufacturer name
384 * @id: manufacturer ID code of device.
386 struct nand_manufacturers {
391 extern struct nand_flash_dev nand_flash_ids[];
392 extern struct nand_manufacturers nand_manuf_ids[];
395 * struct nand_bbt_descr - bad block table descriptor
396 * @options: options for this descriptor
397 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
398 * when bbt is searched, then we store the found bbts pages here.
399 * Its an array and supports up to 8 chips now
400 * @offs: offset of the pattern in the oob area of the page
401 * @veroffs: offset of the bbt version counter in the oob are of the page
402 * @version: version read from the bbt page during scan
403 * @len: length of the pattern, if 0 no pattern check is performed
404 * @maxblocks: maximum number of blocks to search for a bbt. This number of
405 * blocks is reserved at the end of the device where the tables are
407 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
408 * bad) block in the stored bbt
409 * @pattern: pattern to identify bad block table or factory marked good /
410 * bad blocks, can be NULL, if len = 0
412 * Descriptor for the bad block table marker and the descriptor for the
413 * pattern which identifies good and bad blocks. The assumption is made
414 * that the pattern and the version count are always located in the oob area
415 * of the first block.
417 struct nand_bbt_descr {
419 int pages[NAND_MAX_CHIPS];
422 uint8_t version[NAND_MAX_CHIPS];
425 int reserved_block_code;
429 /* Options for the bad block table descriptors */
431 /* The number of bits used per block in the bbt on the device */
432 #define NAND_BBT_NRBITS_MSK 0x0000000F
433 #define NAND_BBT_1BIT 0x00000001
434 #define NAND_BBT_2BIT 0x00000002
435 #define NAND_BBT_4BIT 0x00000004
436 #define NAND_BBT_8BIT 0x00000008
437 /* The bad block table is in the last good block of the device */
438 #define NAND_BBT_LASTBLOCK 0x00000010
439 /* The bbt is at the given page, else we must scan for the bbt */
440 #define NAND_BBT_ABSPAGE 0x00000020
441 /* The bbt is at the given page, else we must scan for the bbt */
442 #define NAND_BBT_SEARCH 0x00000040
443 /* bbt is stored per chip on multichip devices */
444 #define NAND_BBT_PERCHIP 0x00000080
445 /* bbt has a version counter at offset veroffs */
446 #define NAND_BBT_VERSION 0x00000100
447 /* Create a bbt if none axists */
448 #define NAND_BBT_CREATE 0x00000200
449 /* Search good / bad pattern through all pages of a block */
450 #define NAND_BBT_SCANALLPAGES 0x00000400
451 /* Scan block empty during good / bad block scan */
452 #define NAND_BBT_SCANEMPTY 0x00000800
453 /* Write bbt if neccecary */
454 #define NAND_BBT_WRITE 0x00001000
455 /* Read and write back block contents when writing bbt */
456 #define NAND_BBT_SAVECONTENT 0x00002000
457 /* Search good / bad pattern on the first and the second page */
458 #define NAND_BBT_SCAN2NDPAGE 0x00004000
460 /* The maximum number of blocks to scan for a bbt */
461 #define NAND_BBT_SCAN_MAXBLOCKS 4
463 extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
464 extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
465 extern int nand_default_bbt (struct mtd_info *mtd);
466 extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
467 extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
468 extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
469 size_t * retlen, uint8_t * buf, uint8_t * oob_buf,
470 struct nand_oobinfo *oobsel, int flags);
473 * Constants for oob configuration
475 #define NAND_SMALL_BADBLOCK_POS 5
476 #define NAND_LARGE_BADBLOCK_POS 0
479 * struct platform_nand_chip - chip level device structure
481 * @nr_chips: max. number of chips to scan for
482 * @chip_offs: chip number offset
483 * @nr_partitions: number of partitions pointed to be partitoons (or zero)
484 * @partitions: mtd partition list
485 * @chip_delay: R/B delay value in us
486 * @options: Option flags, e.g. 16bit buswidth
487 * @priv: hardware controller specific settings
489 struct platform_nand_chip {
493 struct mtd_partition *partitions;
495 unsigned int options;
500 * struct platform_nand_ctrl - controller level device structure
502 * @hwcontrol: platform specific hardware control structure
503 * @dev_ready: platform specific function to read ready/busy pin
504 * @select_chip: platform specific chip select function
505 * @priv_data: private data to transport driver specific settings
507 * All fields are optional and depend on the hardware driver requirements
509 struct platform_nand_ctrl {
510 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
511 int (*dev_ready)(struct mtd_info *mtd);
512 void (*select_chip)(struct mtd_info *mtd, int chip);
516 /* Some helpers to access the data structures */
518 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
520 struct nand_chip *chip = mtd->priv;
525 #endif /* __LINUX_MTD_NAND_H */