2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * Contains standard defines and IDs for NAND flash devices
20 #ifndef __LINUX_MTD_NAND_H
21 #define __LINUX_MTD_NAND_H
23 #include <linux/wait.h>
24 #include <linux/spinlock.h>
25 #include <linux/mtd/mtd.h>
28 /* Scan and identify a NAND device */
29 extern int nand_scan (struct mtd_info *mtd, int max_chips);
30 /* Separate phases of nand_scan(), allowing board driver to intervene
31 * and override command or ECC setup according to flash type */
32 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
33 extern int nand_scan_tail(struct mtd_info *mtd);
35 /* Free resources held by the NAND device */
36 extern void nand_release (struct mtd_info *mtd);
38 /* Internal helper for board drivers which need to override command function */
39 extern void nand_wait_ready(struct mtd_info *mtd);
41 /* The maximum number of NAND chips in an array */
42 #define NAND_MAX_CHIPS 8
44 /* This constant declares the max. oobsize / page, which
45 * is supported now. If you add a chip with bigger oobsize/page
46 * adjust this accordingly.
48 #define NAND_MAX_OOBSIZE 64
49 #define NAND_MAX_PAGESIZE 2048
52 * Constants for hardware specific CLE/ALE/NCE function
54 * These are bits which can be or'ed to set/clear multiple
57 /* Select the chip by setting nCE to low */
59 /* Select the command latch by setting CLE to high */
61 /* Select the address latch by setting ALE to high */
64 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
65 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
66 #define NAND_CTRL_CHANGE 0x80
69 * Standard NAND flash commands
71 #define NAND_CMD_READ0 0
72 #define NAND_CMD_READ1 1
73 #define NAND_CMD_RNDOUT 5
74 #define NAND_CMD_PAGEPROG 0x10
75 #define NAND_CMD_READOOB 0x50
76 #define NAND_CMD_ERASE1 0x60
77 #define NAND_CMD_STATUS 0x70
78 #define NAND_CMD_STATUS_MULTI 0x71
79 #define NAND_CMD_SEQIN 0x80
80 #define NAND_CMD_RNDIN 0x85
81 #define NAND_CMD_READID 0x90
82 #define NAND_CMD_ERASE2 0xd0
83 #define NAND_CMD_RESET 0xff
85 /* Extended commands for large page devices */
86 #define NAND_CMD_READSTART 0x30
87 #define NAND_CMD_RNDOUTSTART 0xE0
88 #define NAND_CMD_CACHEDPROG 0x15
90 /* Extended commands for AG-AND device */
92 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
93 * there is no way to distinguish that from NAND_CMD_READ0
94 * until the remaining sequence of commands has been completed
95 * so add a high order bit and mask it off in the command.
97 #define NAND_CMD_DEPLETE1 0x100
98 #define NAND_CMD_DEPLETE2 0x38
99 #define NAND_CMD_STATUS_MULTI 0x71
100 #define NAND_CMD_STATUS_ERROR 0x72
101 /* multi-bank error status (banks 0-3) */
102 #define NAND_CMD_STATUS_ERROR0 0x73
103 #define NAND_CMD_STATUS_ERROR1 0x74
104 #define NAND_CMD_STATUS_ERROR2 0x75
105 #define NAND_CMD_STATUS_ERROR3 0x76
106 #define NAND_CMD_STATUS_RESET 0x7f
107 #define NAND_CMD_STATUS_CLEAR 0xff
109 #define NAND_CMD_NONE -1
112 #define NAND_STATUS_FAIL 0x01
113 #define NAND_STATUS_FAIL_N1 0x02
114 #define NAND_STATUS_TRUE_READY 0x20
115 #define NAND_STATUS_READY 0x40
116 #define NAND_STATUS_WP 0x80
119 * Constants for ECC_MODES
125 NAND_ECC_HW_SYNDROME,
129 * Constants for Hardware ECC
131 /* Reset Hardware ECC for read */
132 #define NAND_ECC_READ 0
133 /* Reset Hardware ECC for write */
134 #define NAND_ECC_WRITE 1
135 /* Enable Hardware ECC before syndrom is read back from flash */
136 #define NAND_ECC_READSYN 2
138 /* Bit mask for flags passed to do_nand_read_ecc */
139 #define NAND_GET_DEVICE 0x80
142 /* Option constants for bizarre disfunctionality and real
145 /* Chip can not auto increment pages */
146 #define NAND_NO_AUTOINCR 0x00000001
147 /* Buswitdh is 16 bit */
148 #define NAND_BUSWIDTH_16 0x00000002
149 /* Device supports partial programming without padding */
150 #define NAND_NO_PADDING 0x00000004
151 /* Chip has cache program function */
152 #define NAND_CACHEPRG 0x00000008
153 /* Chip has copy back function */
154 #define NAND_COPYBACK 0x00000010
155 /* AND Chip which has 4 banks and a confusing page / block
156 * assignment. See Renesas datasheet for further information */
157 #define NAND_IS_AND 0x00000020
158 /* Chip has a array of 4 pages which can be read without
159 * additional ready /busy waits */
160 #define NAND_4PAGE_ARRAY 0x00000040
161 /* Chip requires that BBT is periodically rewritten to prevent
162 * bits from adjacent blocks from 'leaking' in altering data.
163 * This happens with the Renesas AG-AND chips, possibly others. */
164 #define BBT_AUTO_REFRESH 0x00000080
165 /* Chip does not require ready check on read. True
166 * for all large page devices, as they do not support
168 #define NAND_NO_READRDY 0x00000100
170 /* Options valid for Samsung large page devices */
171 #define NAND_SAMSUNG_LP_OPTIONS \
172 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
174 /* Macros to identify the above */
175 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
176 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
177 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
178 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
180 /* Mask to zero out the chip options, which come from the id table */
181 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
183 /* Non chip related options */
184 /* Use a flash based bad block table. This option is passed to the
185 * default bad block table function. */
186 #define NAND_USE_FLASH_BBT 0x00010000
187 /* This option skips the bbt scan during initialization. */
188 #define NAND_SKIP_BBTSCAN 0x00020000
189 /* This option is defined if the board driver allocates its own buffers
190 (e.g. because it needs them DMA-coherent */
191 #define NAND_OWN_BUFFERS 0x00040000
192 /* Options set by nand scan */
193 /* Nand scan has allocated controller struct */
194 #define NAND_CONTROLLER_ALLOC 0x80000000
198 * nand_state_t - chip states
199 * Enumeration for NAND flash chip state
215 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
216 * @lock: protection lock
217 * @active: the mtd device which holds the controller currently
218 * @wq: wait queue to sleep on if a NAND operation is in progress
219 * used instead of the per chip wait queue when a hw controller is available
221 struct nand_hw_control {
223 struct nand_chip *active;
224 wait_queue_head_t wq;
228 * struct nand_ecc_ctrl - Control structure for ecc
230 * @steps: number of ecc steps per page
231 * @size: data bytes per ecc step
232 * @bytes: ecc bytes per step
233 * @total: total number of ecc bytes per page
234 * @prepad: padding information for syndrome based ecc generators
235 * @postpad: padding information for syndrome based ecc generators
236 * @layout: ECC layout control struct pointer
237 * @hwctl: function to control hardware ecc generator. Must only
238 * be provided if an hardware ECC is available
239 * @calculate: function for ecc calculation or readback from ecc hardware
240 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
241 * @read_page_raw: function to read a raw page without ECC
242 * @write_page_raw: function to write a raw page without ECC
243 * @read_page: function to read a page according to the ecc generator requirements
244 * @write_page: function to write a page according to the ecc generator requirements
245 * @read_oob: function to read chip OOB data
246 * @write_oob: function to write chip OOB data
248 struct nand_ecc_ctrl {
249 nand_ecc_modes_t mode;
256 struct nand_ecclayout *layout;
257 void (*hwctl)(struct mtd_info *mtd, int mode);
258 int (*calculate)(struct mtd_info *mtd,
261 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
264 int (*read_page_raw)(struct mtd_info *mtd,
265 struct nand_chip *chip,
267 void (*write_page_raw)(struct mtd_info *mtd,
268 struct nand_chip *chip,
270 int (*read_page)(struct mtd_info *mtd,
271 struct nand_chip *chip,
273 void (*write_page)(struct mtd_info *mtd,
274 struct nand_chip *chip,
276 int (*read_oob)(struct mtd_info *mtd,
277 struct nand_chip *chip,
280 int (*write_oob)(struct mtd_info *mtd,
281 struct nand_chip *chip,
286 * struct nand_buffers - buffer structure for read/write
287 * @ecccalc: buffer for calculated ecc
288 * @ecccode: buffer for ecc read from flash
289 * @databuf: buffer for data - dynamically sized
291 * Do not change the order of buffers. databuf and oobrbuf must be in
294 struct nand_buffers {
295 uint8_t ecccalc[NAND_MAX_OOBSIZE];
296 uint8_t ecccode[NAND_MAX_OOBSIZE];
297 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
301 * struct nand_chip - NAND Private Flash Chip Data
302 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
303 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
304 * @read_byte: [REPLACEABLE] read one byte from the chip
305 * @read_word: [REPLACEABLE] read one word from the chip
306 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
307 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
308 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
309 * @select_chip: [REPLACEABLE] select chip nr
310 * @block_bad: [REPLACEABLE] check, if the block is bad
311 * @block_markbad: [REPLACEABLE] mark the block bad
312 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
313 * ALE/CLE/nCE. Also used to write command and address
314 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
315 * If set to NULL no access to ready/busy is available and the ready/busy information
316 * is read from the chip status register
317 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
318 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
319 * @ecc: [BOARDSPECIFIC] ecc control ctructure
320 * @buffers: buffer structure for read/write
321 * @hwcontrol: platform-specific hardware control structure
322 * @ops: oob operation operands
323 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
324 * @scan_bbt: [REPLACEABLE] function to scan bad block table
325 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
326 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
327 * @state: [INTERN] the current state of the NAND device
328 * @oob_poi: poison value buffer
329 * @page_shift: [INTERN] number of address bits in a page (column address bits)
330 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
331 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
332 * @chip_shift: [INTERN] number of address bits in one chip
333 * @datbuf: [INTERN] internal buffer for one page + oob
334 * @oobbuf: [INTERN] oob buffer for one eraseblock
335 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
336 * @data_poi: [INTERN] pointer to a data buffer
337 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
338 * special functionality. See the defines for further explanation
339 * @badblockpos: [INTERN] position of the bad block marker in the oob area
340 * @numchips: [INTERN] number of physical chips
341 * @chipsize: [INTERN] the size of one chip for multichip arrays
342 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
343 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
344 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
345 * @bbt: [INTERN] bad block table pointer
346 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
347 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
348 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
349 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
350 * which is shared among multiple independend devices
351 * @priv: [OPTIONAL] pointer to private chip date
352 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
353 * (determine if errors are correctable)
354 * @write_page [REPLACEABLE] High-level page write function
358 void __iomem *IO_ADDR_R;
359 void __iomem *IO_ADDR_W;
361 uint8_t (*read_byte)(struct mtd_info *mtd);
362 u16 (*read_word)(struct mtd_info *mtd);
363 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
364 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
365 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
366 void (*select_chip)(struct mtd_info *mtd, int chip);
367 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
368 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
369 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
371 int (*dev_ready)(struct mtd_info *mtd);
372 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
373 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
374 void (*erase_cmd)(struct mtd_info *mtd, int page);
375 int (*scan_bbt)(struct mtd_info *mtd);
376 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
377 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
378 const uint8_t *buf, int page, int cached, int raw);
381 unsigned int options;
384 int phys_erase_shift;
388 unsigned long chipsize;
396 struct nand_hw_control *controller;
397 struct nand_ecclayout *ecclayout;
399 struct nand_ecc_ctrl ecc;
400 struct nand_buffers *buffers;
401 struct nand_hw_control hwcontrol;
403 struct mtd_oob_ops ops;
406 struct nand_bbt_descr *bbt_td;
407 struct nand_bbt_descr *bbt_md;
409 struct nand_bbt_descr *badblock_pattern;
415 * NAND Flash Manufacturer ID Codes
417 #define NAND_MFR_TOSHIBA 0x98
418 #define NAND_MFR_SAMSUNG 0xec
419 #define NAND_MFR_FUJITSU 0x04
420 #define NAND_MFR_NATIONAL 0x8f
421 #define NAND_MFR_RENESAS 0x07
422 #define NAND_MFR_STMICRO 0x20
423 #define NAND_MFR_HYNIX 0xad
426 * struct nand_flash_dev - NAND Flash Device ID Structure
427 * @name: Identify the device type
428 * @id: device ID code
429 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
430 * If the pagesize is 0, then the real pagesize
431 * and the eraseize are determined from the
432 * extended id bytes in the chip
433 * @erasesize: Size of an erase block in the flash device.
434 * @chipsize: Total chipsize in Mega Bytes
435 * @options: Bitfield to store chip relevant options
437 struct nand_flash_dev {
440 unsigned long pagesize;
441 unsigned long chipsize;
442 unsigned long erasesize;
443 unsigned long options;
447 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
448 * @name: Manufacturer name
449 * @id: manufacturer ID code of device.
451 struct nand_manufacturers {
456 extern struct nand_flash_dev nand_flash_ids[];
457 extern struct nand_manufacturers nand_manuf_ids[];
460 * struct nand_bbt_descr - bad block table descriptor
461 * @options: options for this descriptor
462 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
463 * when bbt is searched, then we store the found bbts pages here.
464 * Its an array and supports up to 8 chips now
465 * @offs: offset of the pattern in the oob area of the page
466 * @veroffs: offset of the bbt version counter in the oob are of the page
467 * @version: version read from the bbt page during scan
468 * @len: length of the pattern, if 0 no pattern check is performed
469 * @maxblocks: maximum number of blocks to search for a bbt. This number of
470 * blocks is reserved at the end of the device where the tables are
472 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
473 * bad) block in the stored bbt
474 * @pattern: pattern to identify bad block table or factory marked good /
475 * bad blocks, can be NULL, if len = 0
477 * Descriptor for the bad block table marker and the descriptor for the
478 * pattern which identifies good and bad blocks. The assumption is made
479 * that the pattern and the version count are always located in the oob area
480 * of the first block.
482 struct nand_bbt_descr {
484 int pages[NAND_MAX_CHIPS];
487 uint8_t version[NAND_MAX_CHIPS];
490 int reserved_block_code;
494 /* Options for the bad block table descriptors */
496 /* The number of bits used per block in the bbt on the device */
497 #define NAND_BBT_NRBITS_MSK 0x0000000F
498 #define NAND_BBT_1BIT 0x00000001
499 #define NAND_BBT_2BIT 0x00000002
500 #define NAND_BBT_4BIT 0x00000004
501 #define NAND_BBT_8BIT 0x00000008
502 /* The bad block table is in the last good block of the device */
503 #define NAND_BBT_LASTBLOCK 0x00000010
504 /* The bbt is at the given page, else we must scan for the bbt */
505 #define NAND_BBT_ABSPAGE 0x00000020
506 /* The bbt is at the given page, else we must scan for the bbt */
507 #define NAND_BBT_SEARCH 0x00000040
508 /* bbt is stored per chip on multichip devices */
509 #define NAND_BBT_PERCHIP 0x00000080
510 /* bbt has a version counter at offset veroffs */
511 #define NAND_BBT_VERSION 0x00000100
512 /* Create a bbt if none axists */
513 #define NAND_BBT_CREATE 0x00000200
514 /* Search good / bad pattern through all pages of a block */
515 #define NAND_BBT_SCANALLPAGES 0x00000400
516 /* Scan block empty during good / bad block scan */
517 #define NAND_BBT_SCANEMPTY 0x00000800
518 /* Write bbt if neccecary */
519 #define NAND_BBT_WRITE 0x00001000
520 /* Read and write back block contents when writing bbt */
521 #define NAND_BBT_SAVECONTENT 0x00002000
522 /* Search good / bad pattern on the first and the second page */
523 #define NAND_BBT_SCAN2NDPAGE 0x00004000
525 /* The maximum number of blocks to scan for a bbt */
526 #define NAND_BBT_SCAN_MAXBLOCKS 4
528 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
529 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
530 extern int nand_default_bbt(struct mtd_info *mtd);
531 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
532 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
534 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
535 size_t * retlen, uint8_t * buf);
538 * Constants for oob configuration
540 #define NAND_SMALL_BADBLOCK_POS 5
541 #define NAND_LARGE_BADBLOCK_POS 0
544 * struct platform_nand_chip - chip level device structure
545 * @nr_chips: max. number of chips to scan for
546 * @chip_offset: chip number offset
547 * @nr_partitions: number of partitions pointed to by partitions (or zero)
548 * @partitions: mtd partition list
549 * @chip_delay: R/B delay value in us
550 * @options: Option flags, e.g. 16bit buswidth
551 * @ecclayout: ecc layout info structure
552 * @priv: hardware controller specific settings
554 struct platform_nand_chip {
558 struct mtd_partition *partitions;
559 struct nand_ecclayout *ecclayout;
561 unsigned int options;
566 * struct platform_nand_ctrl - controller level device structure
567 * @hwcontrol: platform specific hardware control structure
568 * @dev_ready: platform specific function to read ready/busy pin
569 * @select_chip: platform specific chip select function
570 * @priv: private data to transport driver specific settings
572 * All fields are optional and depend on the hardware driver requirements
574 struct platform_nand_ctrl {
575 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
576 int (*dev_ready)(struct mtd_info *mtd);
577 void (*select_chip)(struct mtd_info *mtd, int chip);
581 /* Some helpers to access the data structures */
583 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
585 struct nand_chip *chip = mtd->priv;
590 #endif /* __LINUX_MTD_NAND_H */