2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev;
31 /* Scan and identify a NAND device */
32 int nand_scan(struct mtd_info *mtd, int max_chips);
34 * Separate phases of nand_scan(), allowing board driver to intervene
35 * and override command or ECC setup according to flash type.
37 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
38 struct nand_flash_dev *table);
39 int nand_scan_tail(struct mtd_info *mtd);
41 /* Free resources held by the NAND device */
42 void nand_release(struct mtd_info *mtd);
44 /* Internal helper for board drivers which need to override command function */
45 void nand_wait_ready(struct mtd_info *mtd);
47 /* locks all blocks present in the device */
48 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
50 /* unlocks specified locked blocks */
51 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
53 /* The maximum number of NAND chips in an array */
54 #define NAND_MAX_CHIPS 8
57 * Constants for hardware specific CLE/ALE/NCE function
59 * These are bits which can be or'ed to set/clear multiple
62 /* Select the chip by setting nCE to low */
64 /* Select the command latch by setting CLE to high */
66 /* Select the address latch by setting ALE to high */
69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
71 #define NAND_CTRL_CHANGE 0x80
74 * Standard NAND flash commands
76 #define NAND_CMD_READ0 0
77 #define NAND_CMD_READ1 1
78 #define NAND_CMD_RNDOUT 5
79 #define NAND_CMD_PAGEPROG 0x10
80 #define NAND_CMD_READOOB 0x50
81 #define NAND_CMD_ERASE1 0x60
82 #define NAND_CMD_STATUS 0x70
83 #define NAND_CMD_SEQIN 0x80
84 #define NAND_CMD_RNDIN 0x85
85 #define NAND_CMD_READID 0x90
86 #define NAND_CMD_ERASE2 0xd0
87 #define NAND_CMD_PARAM 0xec
88 #define NAND_CMD_GET_FEATURES 0xee
89 #define NAND_CMD_SET_FEATURES 0xef
90 #define NAND_CMD_RESET 0xff
92 #define NAND_CMD_LOCK 0x2a
93 #define NAND_CMD_UNLOCK1 0x23
94 #define NAND_CMD_UNLOCK2 0x24
96 /* Extended commands for large page devices */
97 #define NAND_CMD_READSTART 0x30
98 #define NAND_CMD_RNDOUTSTART 0xE0
99 #define NAND_CMD_CACHEDPROG 0x15
101 #define NAND_CMD_NONE -1
104 #define NAND_STATUS_FAIL 0x01
105 #define NAND_STATUS_FAIL_N1 0x02
106 #define NAND_STATUS_TRUE_READY 0x20
107 #define NAND_STATUS_READY 0x40
108 #define NAND_STATUS_WP 0x80
111 * Constants for ECC_MODES
117 NAND_ECC_HW_SYNDROME,
118 NAND_ECC_HW_OOB_FIRST,
128 * Constants for Hardware ECC
130 /* Reset Hardware ECC for read */
131 #define NAND_ECC_READ 0
132 /* Reset Hardware ECC for write */
133 #define NAND_ECC_WRITE 1
134 /* Enable Hardware ECC before syndrome is read back from flash */
135 #define NAND_ECC_READSYN 2
138 * Enable generic NAND 'page erased' check. This check is only done when
139 * ecc.correct() returns -EBADMSG.
140 * Set this flag if your implementation does not fix bitflips in erased
141 * pages and you want to rely on the default implementation.
143 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
145 /* Bit mask for flags passed to do_nand_read_ecc */
146 #define NAND_GET_DEVICE 0x80
150 * Option constants for bizarre disfunctionality and real
153 /* Buswidth is 16 bit */
154 #define NAND_BUSWIDTH_16 0x00000002
155 /* Chip has cache program function */
156 #define NAND_CACHEPRG 0x00000008
158 * Chip requires ready check on read (for auto-incremented sequential read).
159 * True only for small page devices; large page devices do not support
162 #define NAND_NEED_READRDY 0x00000100
164 /* Chip does not allow subpage writes */
165 #define NAND_NO_SUBPAGE_WRITE 0x00000200
167 /* Device is one of 'new' xD cards that expose fake nand command set */
168 #define NAND_BROKEN_XD 0x00000400
170 /* Device behaves just like nand, but is readonly */
171 #define NAND_ROM 0x00000800
173 /* Device supports subpage reads */
174 #define NAND_SUBPAGE_READ 0x00001000
177 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
180 #define NAND_NEED_SCRAMBLING 0x00002000
182 /* Options valid for Samsung large page devices */
183 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
185 /* Macros to identify the above */
186 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
187 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
189 /* Non chip related options */
190 /* This option skips the bbt scan during initialization. */
191 #define NAND_SKIP_BBTSCAN 0x00010000
193 * This option is defined if the board driver allocates its own buffers
194 * (e.g. because it needs them DMA-coherent).
196 #define NAND_OWN_BUFFERS 0x00020000
197 /* Chip may not exist, so silence any errors in scan */
198 #define NAND_SCAN_SILENT_NODEV 0x00040000
200 * Autodetect nand buswidth with readid/onfi.
201 * This suppose the driver will configure the hardware in 8 bits mode
202 * when calling nand_scan_ident, and update its configuration
203 * before calling nand_scan_tail.
205 #define NAND_BUSWIDTH_AUTO 0x00080000
207 * This option could be defined by controller drivers to protect against
208 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
210 #define NAND_USE_BOUNCE_BUFFER 0x00100000
212 /* Options set by nand scan */
213 /* Nand scan has allocated controller struct */
214 #define NAND_CONTROLLER_ALLOC 0x80000000
216 /* Cell info constants */
217 #define NAND_CI_CHIPNR_MSK 0x03
218 #define NAND_CI_CELLTYPE_MSK 0x0C
219 #define NAND_CI_CELLTYPE_SHIFT 2
225 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
226 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
228 /* ONFI timing mode, used in both asynchronous and synchronous mode */
229 #define ONFI_TIMING_MODE_0 (1 << 0)
230 #define ONFI_TIMING_MODE_1 (1 << 1)
231 #define ONFI_TIMING_MODE_2 (1 << 2)
232 #define ONFI_TIMING_MODE_3 (1 << 3)
233 #define ONFI_TIMING_MODE_4 (1 << 4)
234 #define ONFI_TIMING_MODE_5 (1 << 5)
235 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
237 /* ONFI feature address */
238 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
240 /* Vendor-specific feature address (Micron) */
241 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
243 /* ONFI subfeature parameters length */
244 #define ONFI_SUBFEATURE_PARAM_LEN 4
246 /* ONFI optional commands SET/GET FEATURES supported? */
247 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
249 struct nand_onfi_params {
250 /* rev info and features block */
251 /* 'O' 'N' 'F' 'I' */
257 __le16 ext_param_page_length; /* since ONFI 2.1 */
258 u8 num_of_param_pages; /* since ONFI 2.1 */
261 /* manufacturer information block */
262 char manufacturer[12];
268 /* memory organization block */
269 __le32 byte_per_page;
270 __le16 spare_bytes_per_page;
271 __le32 data_bytes_per_ppage;
272 __le16 spare_bytes_per_ppage;
273 __le32 pages_per_block;
274 __le32 blocks_per_lun;
279 __le16 block_endurance;
280 u8 guaranteed_good_blocks;
281 __le16 guaranteed_block_endurance;
282 u8 programs_per_page;
289 /* electrical parameter block */
290 u8 io_pin_capacitance_max;
291 __le16 async_timing_mode;
292 __le16 program_cache_timing_mode;
297 __le16 src_sync_timing_mode;
298 u8 src_ssync_features;
299 __le16 clk_pin_capacitance_typ;
300 __le16 io_pin_capacitance_typ;
301 __le16 input_pin_capacitance_typ;
302 u8 input_pin_capacitance_max;
303 u8 driver_strength_support;
309 __le16 vendor_revision;
315 #define ONFI_CRC_BASE 0x4F4E
317 /* Extended ECC information Block Definition (since ONFI 2.1) */
318 struct onfi_ext_ecc_info {
322 __le16 block_endurance;
326 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
327 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
328 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
329 struct onfi_ext_section {
334 #define ONFI_EXT_SECTION_MAX 8
336 /* Extended Parameter Page Definition (since ONFI 2.1) */
337 struct onfi_ext_param_page {
339 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
341 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
344 * The actual size of the Extended Parameter Page is in
345 * @ext_param_page_length of nand_onfi_params{}.
346 * The following are the variable length sections.
347 * So we do not add any fields below. Please see the ONFI spec.
351 struct nand_onfi_vendor_micron {
356 u8 dq_imped_num_settings;
357 u8 dq_imped_feat_addr;
358 u8 rb_pulldown_strength;
359 u8 rb_pulldown_strength_feat_addr;
360 u8 rb_pulldown_strength_num_settings;
363 u8 otp_data_prot_addr;
366 u8 read_retry_options;
371 struct jedec_ecc_info {
375 __le16 block_endurance;
380 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
382 struct nand_jedec_params {
383 /* rev info and features block */
384 /* 'J' 'E' 'S' 'D' */
390 u8 num_of_param_pages;
393 /* manufacturer information block */
394 char manufacturer[12];
399 /* memory organization block */
400 __le32 byte_per_page;
401 __le16 spare_bytes_per_page;
403 __le32 pages_per_block;
404 __le32 blocks_per_lun;
408 u8 programs_per_page;
410 u8 multi_plane_op_attr;
413 /* electrical parameter block */
414 __le16 async_sdr_speed_grade;
415 __le16 toggle_ddr_speed_grade;
416 __le16 sync_ddr_speed_grade;
417 u8 async_sdr_features;
418 u8 toggle_ddr_features;
419 u8 sync_ddr_features;
423 __le16 t_r_multi_plane;
425 __le16 io_pin_capacitance_typ;
426 __le16 input_pin_capacitance_typ;
427 __le16 clk_pin_capacitance_typ;
428 u8 driver_strength_support;
432 /* ECC and endurance block */
433 u8 guaranteed_good_blocks;
434 __le16 guaranteed_block_endurance;
435 struct jedec_ecc_info ecc_info[4];
442 __le16 vendor_rev_num;
445 /* CRC for Parameter Page */
450 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
451 * @lock: protection lock
452 * @active: the mtd device which holds the controller currently
453 * @wq: wait queue to sleep on if a NAND operation is in
454 * progress used instead of the per chip wait queue
455 * when a hw controller is available.
457 struct nand_hw_control {
459 struct nand_chip *active;
460 wait_queue_head_t wq;
463 static inline void nand_hw_control_init(struct nand_hw_control *nfc)
466 spin_lock_init(&nfc->lock);
467 init_waitqueue_head(&nfc->wq);
471 * struct nand_ecc_ctrl - Control structure for ECC
473 * @algo: ECC algorithm
474 * @steps: number of ECC steps per page
475 * @size: data bytes per ECC step
476 * @bytes: ECC bytes per step
477 * @strength: max number of correctible bits per ECC step
478 * @total: total number of ECC bytes per page
479 * @prepad: padding information for syndrome based ECC generators
480 * @postpad: padding information for syndrome based ECC generators
481 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
482 * @priv: pointer to private ECC control data
483 * @hwctl: function to control hardware ECC generator. Must only
484 * be provided if an hardware ECC is available
485 * @calculate: function for ECC calculation or readback from ECC hardware
486 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
487 * Should return a positive number representing the number of
488 * corrected bitflips, -EBADMSG if the number of bitflips exceed
489 * ECC strength, or any other error code if the error is not
490 * directly related to correction.
491 * If -EBADMSG is returned the input buffers should be left
493 * @read_page_raw: function to read a raw page without ECC. This function
494 * should hide the specific layout used by the ECC
495 * controller and always return contiguous in-band and
496 * out-of-band data even if they're not stored
497 * contiguously on the NAND chip (e.g.
498 * NAND_ECC_HW_SYNDROME interleaves in-band and
500 * @write_page_raw: function to write a raw page without ECC. This function
501 * should hide the specific layout used by the ECC
502 * controller and consider the passed data as contiguous
503 * in-band and out-of-band data. ECC controller is
504 * responsible for doing the appropriate transformations
505 * to adapt to its specific layout (e.g.
506 * NAND_ECC_HW_SYNDROME interleaves in-band and
508 * @read_page: function to read a page according to the ECC generator
509 * requirements; returns maximum number of bitflips corrected in
510 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
511 * @read_subpage: function to read parts of the page covered by ECC;
512 * returns same as read_page()
513 * @write_subpage: function to write parts of the page covered by ECC.
514 * @write_page: function to write a page according to the ECC generator
516 * @write_oob_raw: function to write chip OOB data without ECC
517 * @read_oob_raw: function to read chip OOB data without ECC
518 * @read_oob: function to read chip OOB data
519 * @write_oob: function to write chip OOB data
521 struct nand_ecc_ctrl {
522 nand_ecc_modes_t mode;
523 enum nand_ecc_algo algo;
531 unsigned int options;
533 void (*hwctl)(struct mtd_info *mtd, int mode);
534 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
536 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
538 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
539 uint8_t *buf, int oob_required, int page);
540 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
541 const uint8_t *buf, int oob_required, int page);
542 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
543 uint8_t *buf, int oob_required, int page);
544 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
545 uint32_t offs, uint32_t len, uint8_t *buf, int page);
546 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
547 uint32_t offset, uint32_t data_len,
548 const uint8_t *data_buf, int oob_required, int page);
549 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
550 const uint8_t *buf, int oob_required, int page);
551 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
553 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
555 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
556 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
561 * struct nand_buffers - buffer structure for read/write
562 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
563 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
564 * @databuf: buffer pointer for data, size is (page size + oobsize).
566 * Do not change the order of buffers. databuf and oobrbuf must be in
569 struct nand_buffers {
576 * struct nand_sdr_timings - SDR NAND chip timings
578 * This struct defines the timing requirements of a SDR NAND chip.
579 * These information can be found in every NAND datasheets and the timings
580 * meaning are described in the ONFI specifications:
581 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
584 * All these timings are expressed in picoseconds.
586 * @tALH_min: ALE hold time
587 * @tADL_min: ALE to data loading time
588 * @tALS_min: ALE setup time
589 * @tAR_min: ALE to RE# delay
590 * @tCEA_max: CE# access time
592 * @tCH_min: CE# hold time
593 * @tCHZ_max: CE# high to output hi-Z
594 * @tCLH_min: CLE hold time
595 * @tCLR_min: CLE to RE# delay
596 * @tCLS_min: CLE setup time
597 * @tCOH_min: CE# high to output hold
598 * @tCS_min: CE# setup time
599 * @tDH_min: Data hold time
600 * @tDS_min: Data setup time
601 * @tFEAT_max: Busy time for Set Features and Get Features
602 * @tIR_min: Output hi-Z to RE# low
603 * @tITC_max: Interface and Timing Mode Change time
604 * @tRC_min: RE# cycle time
605 * @tREA_max: RE# access time
606 * @tREH_min: RE# high hold time
607 * @tRHOH_min: RE# high to output hold
608 * @tRHW_min: RE# high to WE# low
609 * @tRHZ_max: RE# high to output hi-Z
610 * @tRLOH_min: RE# low to output hold
611 * @tRP_min: RE# pulse width
612 * @tRR_min: Ready to RE# low (data only)
613 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
614 * rising edge of R/B#.
615 * @tWB_max: WE# high to SR[6] low
616 * @tWC_min: WE# cycle time
617 * @tWH_min: WE# high hold time
618 * @tWHR_min: WE# high to RE# low
619 * @tWP_min: WE# pulse width
620 * @tWW_min: WP# transition to WE# low
622 struct nand_sdr_timings {
660 * enum nand_data_interface_type - NAND interface timing type
661 * @NAND_SDR_IFACE: Single Data Rate interface
663 enum nand_data_interface_type {
668 * struct nand_data_interface - NAND interface timing
669 * @type: type of the timing
670 * @timings: The timing, type according to @type
672 struct nand_data_interface {
673 enum nand_data_interface_type type;
675 struct nand_sdr_timings sdr;
680 * nand_get_sdr_timings - get SDR timing from data interface
681 * @conf: The data interface
683 static inline const struct nand_sdr_timings *
684 nand_get_sdr_timings(const struct nand_data_interface *conf)
686 if (conf->type != NAND_SDR_IFACE)
687 return ERR_PTR(-EINVAL);
689 return &conf->timings.sdr;
693 * struct nand_chip - NAND Private Flash Chip Data
694 * @mtd: MTD device registered to the MTD framework
695 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
697 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
699 * @read_byte: [REPLACEABLE] read one byte from the chip
700 * @read_word: [REPLACEABLE] read one word from the chip
701 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
703 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
704 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
705 * @select_chip: [REPLACEABLE] select chip nr
706 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
707 * @block_markbad: [REPLACEABLE] mark a block bad
708 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
709 * ALE/CLE/nCE. Also used to write command and address
710 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
711 * device ready/busy line. If set to NULL no access to
712 * ready/busy is available and the ready/busy information
713 * is read from the chip status register.
714 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
715 * commands to the chip.
716 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
718 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
719 * setting the read-retry mode. Mostly needed for MLC NAND.
720 * @ecc: [BOARDSPECIFIC] ECC control structure
721 * @buffers: buffer structure for read/write
722 * @hwcontrol: platform-specific hardware control structure
723 * @erase: [REPLACEABLE] erase function
724 * @scan_bbt: [REPLACEABLE] function to scan bad block table
725 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
726 * data from array to read regs (tR).
727 * @state: [INTERN] the current state of the NAND device
728 * @oob_poi: "poison value buffer," used for laying out OOB data
730 * @page_shift: [INTERN] number of address bits in a page (column
732 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
733 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
734 * @chip_shift: [INTERN] number of address bits in one chip
735 * @options: [BOARDSPECIFIC] various chip options. They can partly
736 * be set to inform nand_scan about special functionality.
737 * See the defines for further explanation.
738 * @bbt_options: [INTERN] bad block specific options. All options used
739 * here must come from bbm.h. By default, these options
740 * will be copied to the appropriate nand_bbt_descr's.
741 * @badblockpos: [INTERN] position of the bad block marker in the oob
743 * @badblockbits: [INTERN] minimum number of set bits in a good block's
744 * bad block marker position; i.e., BBM == 11110111b is
745 * not bad when badblockbits == 7
746 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
747 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
748 * Minimum amount of bit errors per @ecc_step_ds guaranteed
749 * to be correctable. If unknown, set to zero.
750 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
751 * also from the datasheet. It is the recommended ECC step
752 * size, if known; if unknown, set to zero.
753 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
754 * set to the actually used ONFI mode if the chip is
755 * ONFI compliant or deduced from the datasheet if
756 * the NAND chip is not ONFI compliant.
757 * @numchips: [INTERN] number of physical chips
758 * @chipsize: [INTERN] the size of one chip for multichip arrays
759 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
760 * @pagebuf: [INTERN] holds the pagenumber which is currently in
762 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
763 * currently in data_buf.
764 * @subpagesize: [INTERN] holds the subpagesize
765 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
766 * non 0 if ONFI supported.
767 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
768 * non 0 if JEDEC supported.
769 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
770 * supported, 0 otherwise.
771 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
772 * supported, 0 otherwise.
773 * @read_retries: [INTERN] the number of read retry modes supported
774 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
775 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
776 * @setup_data_interface: [OPTIONAL] setup the data interface and timing
777 * @bbt: [INTERN] bad block table pointer
778 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
780 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
781 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
783 * @controller: [REPLACEABLE] a pointer to a hardware controller
784 * structure which is shared among multiple independent
786 * @priv: [OPTIONAL] pointer to private chip data
787 * @errstat: [OPTIONAL] hardware specific function to perform
788 * additional error status checks (determine if errors are
790 * @write_page: [REPLACEABLE] High-level page write function
795 void __iomem *IO_ADDR_R;
796 void __iomem *IO_ADDR_W;
798 uint8_t (*read_byte)(struct mtd_info *mtd);
799 u16 (*read_word)(struct mtd_info *mtd);
800 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
801 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
802 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
803 void (*select_chip)(struct mtd_info *mtd, int chip);
804 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
805 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
806 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
807 int (*dev_ready)(struct mtd_info *mtd);
808 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
810 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
811 int (*erase)(struct mtd_info *mtd, int page);
812 int (*scan_bbt)(struct mtd_info *mtd);
813 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
814 int status, int page);
815 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
816 uint32_t offset, int data_len, const uint8_t *buf,
817 int oob_required, int page, int cached, int raw);
818 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
819 int feature_addr, uint8_t *subfeature_para);
820 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
821 int feature_addr, uint8_t *subfeature_para);
822 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
823 int (*setup_data_interface)(struct mtd_info *mtd,
824 const struct nand_data_interface *conf,
829 unsigned int options;
830 unsigned int bbt_options;
833 int phys_erase_shift;
840 unsigned int pagebuf_bitflips;
842 uint8_t bits_per_cell;
843 uint16_t ecc_strength_ds;
844 uint16_t ecc_step_ds;
845 int onfi_timing_mode_default;
852 struct nand_onfi_params onfi_params;
853 struct nand_jedec_params jedec_params;
856 struct nand_data_interface *data_interface;
863 struct nand_hw_control *controller;
865 struct nand_ecc_ctrl ecc;
866 struct nand_buffers *buffers;
867 struct nand_hw_control hwcontrol;
870 struct nand_bbt_descr *bbt_td;
871 struct nand_bbt_descr *bbt_md;
873 struct nand_bbt_descr *badblock_pattern;
878 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
879 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
881 static inline void nand_set_flash_node(struct nand_chip *chip,
882 struct device_node *np)
884 mtd_set_of_node(&chip->mtd, np);
887 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
889 return mtd_get_of_node(&chip->mtd);
892 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
894 return container_of(mtd, struct nand_chip, mtd);
897 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
902 static inline void *nand_get_controller_data(struct nand_chip *chip)
907 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
913 * NAND Flash Manufacturer ID Codes
915 #define NAND_MFR_TOSHIBA 0x98
916 #define NAND_MFR_ESMT 0xc8
917 #define NAND_MFR_SAMSUNG 0xec
918 #define NAND_MFR_FUJITSU 0x04
919 #define NAND_MFR_NATIONAL 0x8f
920 #define NAND_MFR_RENESAS 0x07
921 #define NAND_MFR_STMICRO 0x20
922 #define NAND_MFR_HYNIX 0xad
923 #define NAND_MFR_MICRON 0x2c
924 #define NAND_MFR_AMD 0x01
925 #define NAND_MFR_MACRONIX 0xc2
926 #define NAND_MFR_EON 0x92
927 #define NAND_MFR_SANDISK 0x45
928 #define NAND_MFR_INTEL 0x89
929 #define NAND_MFR_ATO 0x9b
931 /* The maximum expected count of bytes in the NAND ID sequence */
932 #define NAND_MAX_ID_LEN 8
935 * A helper for defining older NAND chips where the second ID byte fully
936 * defined the chip, including the geometry (chip size, eraseblock size, page
937 * size). All these chips have 512 bytes NAND page size.
939 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
940 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
941 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
944 * A helper for defining newer chips which report their page size and
945 * eraseblock size via the extended ID bytes.
947 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
948 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
949 * device ID now only represented a particular total chip size (and voltage,
950 * buswidth), and the page size, eraseblock size, and OOB size could vary while
951 * using the same device ID.
953 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
954 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
957 #define NAND_ECC_INFO(_strength, _step) \
958 { .strength_ds = (_strength), .step_ds = (_step) }
959 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
960 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
963 * struct nand_flash_dev - NAND Flash Device ID Structure
964 * @name: a human-readable name of the NAND chip
965 * @dev_id: the device ID (the second byte of the full chip ID array)
966 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
967 * memory address as @id[0])
968 * @dev_id: device ID part of the full chip ID array (refers the same memory
970 * @id: full device ID array
971 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
972 * well as the eraseblock size) is determined from the extended NAND
974 * @chipsize: total chip size in MiB
975 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
976 * @options: stores various chip bit options
977 * @id_len: The valid length of the @id.
979 * @ecc: ECC correctability and step information from the datasheet.
980 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
981 * @ecc_strength_ds in nand_chip{}.
982 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
983 * @ecc_step_ds in nand_chip{}, also from the datasheet.
984 * For example, the "4bit ECC for each 512Byte" can be set with
985 * NAND_ECC_INFO(4, 512).
986 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
987 * reset. Should be deduced from timings described
991 struct nand_flash_dev {
998 uint8_t id[NAND_MAX_ID_LEN];
1000 unsigned int pagesize;
1001 unsigned int chipsize;
1002 unsigned int erasesize;
1003 unsigned int options;
1007 uint16_t strength_ds;
1010 int onfi_timing_mode_default;
1014 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1015 * @name: Manufacturer name
1016 * @id: manufacturer ID code of device.
1018 struct nand_manufacturers {
1023 extern struct nand_flash_dev nand_flash_ids[];
1024 extern struct nand_manufacturers nand_manuf_ids[];
1026 int nand_default_bbt(struct mtd_info *mtd);
1027 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1028 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1029 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1030 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1032 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1033 size_t *retlen, uint8_t *buf);
1036 * struct platform_nand_chip - chip level device structure
1037 * @nr_chips: max. number of chips to scan for
1038 * @chip_offset: chip number offset
1039 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1040 * @partitions: mtd partition list
1041 * @chip_delay: R/B delay value in us
1042 * @options: Option flags, e.g. 16bit buswidth
1043 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1044 * @part_probe_types: NULL-terminated array of probe types
1046 struct platform_nand_chip {
1050 struct mtd_partition *partitions;
1052 unsigned int options;
1053 unsigned int bbt_options;
1054 const char **part_probe_types;
1057 /* Keep gcc happy */
1058 struct platform_device;
1061 * struct platform_nand_ctrl - controller level device structure
1062 * @probe: platform specific function to probe/setup hardware
1063 * @remove: platform specific function to remove/teardown hardware
1064 * @hwcontrol: platform specific hardware control structure
1065 * @dev_ready: platform specific function to read ready/busy pin
1066 * @select_chip: platform specific chip select function
1067 * @cmd_ctrl: platform specific function for controlling
1068 * ALE/CLE/nCE. Also used to write command and address
1069 * @write_buf: platform specific function for write buffer
1070 * @read_buf: platform specific function for read buffer
1071 * @read_byte: platform specific function to read one byte from chip
1072 * @priv: private data to transport driver specific settings
1074 * All fields are optional and depend on the hardware driver requirements
1076 struct platform_nand_ctrl {
1077 int (*probe)(struct platform_device *pdev);
1078 void (*remove)(struct platform_device *pdev);
1079 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1080 int (*dev_ready)(struct mtd_info *mtd);
1081 void (*select_chip)(struct mtd_info *mtd, int chip);
1082 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1083 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1084 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1085 unsigned char (*read_byte)(struct mtd_info *mtd);
1090 * struct platform_nand_data - container structure for platform-specific data
1091 * @chip: chip level chip structure
1092 * @ctrl: controller level device structure
1094 struct platform_nand_data {
1095 struct platform_nand_chip chip;
1096 struct platform_nand_ctrl ctrl;
1099 /* return the supported features. */
1100 static inline int onfi_feature(struct nand_chip *chip)
1102 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1105 /* return the supported asynchronous timing mode. */
1106 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1108 if (!chip->onfi_version)
1109 return ONFI_TIMING_MODE_UNKNOWN;
1110 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1113 /* return the supported synchronous timing mode. */
1114 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1116 if (!chip->onfi_version)
1117 return ONFI_TIMING_MODE_UNKNOWN;
1118 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1121 int onfi_init_data_interface(struct nand_chip *chip,
1122 struct nand_data_interface *iface,
1123 enum nand_data_interface_type type,
1127 * Check if it is a SLC nand.
1128 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1129 * We do not distinguish the MLC and TLC now.
1131 static inline bool nand_is_slc(struct nand_chip *chip)
1133 return chip->bits_per_cell == 1;
1137 * Check if the opcode's address should be sent only on the lower 8 bits
1138 * @command: opcode to check
1140 static inline int nand_opcode_8bits(unsigned int command)
1143 case NAND_CMD_READID:
1144 case NAND_CMD_PARAM:
1145 case NAND_CMD_GET_FEATURES:
1146 case NAND_CMD_SET_FEATURES:
1154 /* return the supported JEDEC features. */
1155 static inline int jedec_feature(struct nand_chip *chip)
1157 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1161 /* get timing characteristics from ONFI timing mode. */
1162 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1163 /* get data interface from ONFI timing mode 0, used after reset. */
1164 const struct nand_data_interface *nand_get_default_data_interface(void);
1166 int nand_check_erased_ecc_chunk(void *data, int datalen,
1167 void *ecc, int ecclen,
1168 void *extraoob, int extraooblen,
1171 /* Default write_oob implementation */
1172 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1174 /* Default write_oob syndrome implementation */
1175 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1178 /* Default read_oob implementation */
1179 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1181 /* Default read_oob syndrome implementation */
1182 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1185 /* Reset and initialize a NAND device */
1186 int nand_reset(struct nand_chip *chip);
1188 #endif /* __LINUX_MTD_NAND_H */